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Eachlink H6 Mini Android DT

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May 8th, 2021
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  1. /dts-v1/;
  2.  
  3. /memreserve/ 0x0000000040020000 0x0000000000000800;
  4. /memreserve/ 0x0000000048000000 0x0000000001000000;
  5. /memreserve/ 0x0000000048100000 0x0000000000004000;
  6. /memreserve/ 0x0000000048104000 0x0000000000001000;
  7. /memreserve/ 0x0000000048105000 0x0000000000001000;
  8. / {
  9. model = "sun50iw6";
  10. compatible = "arm,sun50iw6p1";
  11. interrupt-parent = <0x01>;
  12. #address-cells = <0x02>;
  13. #size-cells = <0x02>;
  14.  
  15. clocks {
  16. compatible = "allwinner,sunxi-clk-init";
  17. device_type = "clocks";
  18. #address-cells = <0x02>;
  19. #size-cells = <0x02>;
  20. ranges;
  21. reg = <0x00 0x3001000 0x00 0x1000 0x00 0x7010000 0x00 0x400 0x00 0x7000000 0x00 0x04>;
  22.  
  23. losc {
  24. #clock-cells = <0x00>;
  25. compatible = "allwinner,fixed-clock";
  26. clock-frequency = <0x8000>;
  27. clock-output-names = "losc";
  28. linux,phandle = <0x0d>;
  29. phandle = <0x0d>;
  30. };
  31.  
  32. iosc {
  33. #clock-cells = <0x00>;
  34. compatible = "allwinner,fixed-clock";
  35. clock-frequency = <0xf42400>;
  36. clock-output-names = "iosc";
  37. linux,phandle = <0x0e>;
  38. phandle = <0x0e>;
  39. };
  40.  
  41. hosc {
  42. #clock-cells = <0x00>;
  43. compatible = "allwinner,fixed-clock";
  44. clock-frequency = <0x16e3600>;
  45. clock-output-names = "hosc";
  46. linux,phandle = <0x07>;
  47. phandle = <0x07>;
  48. };
  49.  
  50. osc48m {
  51. #clock-cells = <0x00>;
  52. compatible = "allwinner,fixed-clock";
  53. clock-frequency = <0x2dc6c00>;
  54. clock-output-names = "osc48m";
  55. linux,phandle = <0x08>;
  56. phandle = <0x08>;
  57. };
  58.  
  59. pll_cpu {
  60. #clock-cells = <0x00>;
  61. compatible = "allwinner,sunxi-pll-clock";
  62. lock-mode = "new";
  63. clock-output-names = "pll_cpu";
  64. };
  65.  
  66. pll_ddr0 {
  67. #clock-cells = <0x00>;
  68. compatible = "allwinner,sunxi-pll-clock";
  69. lock-mode = "new";
  70. clock-output-names = "pll_ddr0";
  71. linux,phandle = <0xd7>;
  72. phandle = <0xd7>;
  73. };
  74.  
  75. pll_periph0 {
  76. #clock-cells = <0x00>;
  77. compatible = "allwinner,sunxi-pll-clock";
  78. assigned-clock-rates = <0x23c34600>;
  79. lock-mode = "new";
  80. clock-output-names = "pll_periph0";
  81. linux,phandle = <0x02>;
  82. phandle = <0x02>;
  83. };
  84.  
  85. pll_periph1 {
  86. #clock-cells = <0x00>;
  87. compatible = "allwinner,sunxi-pll-clock";
  88. assigned-clock-rates = <0x23c34600>;
  89. lock-mode = "new";
  90. clock-output-names = "pll_periph1";
  91. linux,phandle = <0x03>;
  92. phandle = <0x03>;
  93. };
  94.  
  95. pll_gpu {
  96. #clock-cells = <0x00>;
  97. compatible = "allwinner,sunxi-pll-clock";
  98. lock-mode = "new";
  99. clock-output-names = "pll_gpu";
  100. linux,phandle = <0xd9>;
  101. phandle = <0xd9>;
  102. };
  103.  
  104. pll_video0 {
  105. #clock-cells = <0x00>;
  106. compatible = "allwinner,sunxi-pll-clock";
  107. lock-mode = "new";
  108. clock-output-names = "pll_video0";
  109. linux,phandle = <0x05>;
  110. phandle = <0x05>;
  111. };
  112.  
  113. pll_video1 {
  114. #clock-cells = <0x00>;
  115. compatible = "allwinner,sunxi-pll-clock";
  116. lock-mode = "new";
  117. assigned-clock-rates = <0x2367b880>;
  118. clock-output-names = "pll_video1";
  119. linux,phandle = <0x06>;
  120. phandle = <0x06>;
  121. };
  122.  
  123. pll_ve {
  124. #clock-cells = <0x00>;
  125. compatible = "allwinner,sunxi-pll-clock";
  126. device_type = "clk_pll_ve";
  127. lock-mode = "new";
  128. clock-output-names = "pll_ve";
  129. linux,phandle = <0x17>;
  130. phandle = <0x17>;
  131. };
  132.  
  133. pll_de {
  134. #clock-cells = <0x00>;
  135. compatible = "allwinner,sunxi-pll-clock";
  136. assigned-clock-rates = <0x297c1e00>;
  137. lock-mode = "new";
  138. clock-output-names = "pll_de";
  139. linux,phandle = <0x09>;
  140. phandle = <0x09>;
  141. };
  142.  
  143. pll_hsic {
  144. #clock-cells = <0x00>;
  145. compatible = "allwinner,sunxi-pll-clock";
  146. lock-mode = "new";
  147. clock-output-names = "pll_hsic";
  148. linux,phandle = <0x3f>;
  149. phandle = <0x3f>;
  150. };
  151.  
  152. pll_audio {
  153. #clock-cells = <0x00>;
  154. compatible = "allwinner,sunxi-pll-clock";
  155. lock-mode = "new";
  156. clock-output-names = "pll_audio";
  157. linux,phandle = <0x04>;
  158. phandle = <0x04>;
  159. };
  160.  
  161. pll_periph0x2 {
  162. #clock-cells = <0x00>;
  163. compatible = "allwinner,fixed-factor-clock";
  164. clocks = <0x02>;
  165. clock-mult = <0x02>;
  166. clock-div = <0x01>;
  167. clock-output-names = "pll_periph0x2";
  168. linux,phandle = <0x1b>;
  169. phandle = <0x1b>;
  170. };
  171.  
  172. pll_periph0x4 {
  173. #clock-cells = <0x00>;
  174. compatible = "allwinner,fixed-factor-clock";
  175. clocks = <0x02>;
  176. clock-mult = <0x04>;
  177. clock-div = <0x01>;
  178. clock-output-names = "pll_periph0x4";
  179. };
  180.  
  181. periph32k {
  182. #clock-cells = <0x00>;
  183. compatible = "allwinner,fixed-factor-clock";
  184. clocks = <0x02>;
  185. clock-mult = <0x02>;
  186. clock-div = <0x8f0d>;
  187. clock-output-names = "periph32k";
  188. };
  189.  
  190. pll_periph1x2 {
  191. #clock-cells = <0x00>;
  192. compatible = "allwinner,fixed-factor-clock";
  193. clocks = <0x03>;
  194. clock-mult = <0x02>;
  195. clock-div = <0x01>;
  196. clock-output-names = "pll_periph1x2";
  197. linux,phandle = <0x75>;
  198. phandle = <0x75>;
  199. };
  200.  
  201. pll_audiox4 {
  202. #clock-cells = <0x00>;
  203. compatible = "allwinner,fixed-factor-clock";
  204. clocks = <0x04>;
  205. clock-mult = <0x04>;
  206. clock-div = <0x01>;
  207. clock-output-names = "pll_audiox4";
  208. };
  209.  
  210. pll_audiox2 {
  211. #clock-cells = <0x00>;
  212. compatible = "allwinner,fixed-factor-clock";
  213. clocks = <0x04>;
  214. clock-mult = <0x02>;
  215. clock-div = <0x01>;
  216. clock-output-names = "pll_audiox2";
  217. };
  218.  
  219. pll_video0x4 {
  220. #clock-cells = <0x00>;
  221. compatible = "allwinner,fixed-factor-clock";
  222. clocks = <0x05>;
  223. clock-mult = <0x04>;
  224. clock-div = <0x01>;
  225. clock-output-names = "pll_video0x4";
  226. };
  227.  
  228. pll_video1x4 {
  229. #clock-cells = <0x00>;
  230. compatible = "allwinner,fixed-factor-clock";
  231. clocks = <0x06>;
  232. clock-mult = <0x04>;
  233. clock-div = <0x01>;
  234. clock-output-names = "pll_video1x4";
  235. };
  236.  
  237. hoscd2 {
  238. #clock-cells = <0x00>;
  239. compatible = "allwinner,fixed-factor-clock";
  240. clocks = <0x07>;
  241. clock-mult = <0x01>;
  242. clock-div = <0x02>;
  243. clock-output-names = "hoscd2";
  244. };
  245.  
  246. osc48md4 {
  247. #clock-cells = <0x00>;
  248. compatible = "allwinner,fixed-factor-clock";
  249. clocks = <0x08>;
  250. clock-mult = <0x01>;
  251. clock-div = <0x04>;
  252. clock-output-names = "osc48md4";
  253. linux,phandle = <0x39>;
  254. phandle = <0x39>;
  255. };
  256.  
  257. pll_periph0d6 {
  258. #clock-cells = <0x00>;
  259. compatible = "allwinner,fixed-factor-clock";
  260. clocks = <0x02>;
  261. clock-mult = <0x01>;
  262. clock-div = <0x06>;
  263. clock-output-names = "pll_periph0d6";
  264. };
  265.  
  266. cpu {
  267. #clock-cells = <0x00>;
  268. compatible = "allwinner,sunxi-periph-clock";
  269. clock-output-names = "cpu";
  270. };
  271.  
  272. axi {
  273. #clock-cells = <0x00>;
  274. compatible = "allwinner,sunxi-periph-clock";
  275. clock-output-names = "axi";
  276. };
  277.  
  278. cpuapb {
  279. #clock-cells = <0x00>;
  280. compatible = "allwinner,sunxi-periph-clock";
  281. clock-output-names = "cpuapb";
  282. };
  283.  
  284. psi {
  285. #clock-cells = <0x00>;
  286. compatible = "allwinner,sunxi-periph-clock";
  287. clock-output-names = "psi";
  288. };
  289.  
  290. ahb1 {
  291. #clock-cells = <0x00>;
  292. compatible = "allwinner,sunxi-periph-clock";
  293. clock-output-names = "ahb1";
  294. };
  295.  
  296. ahb2 {
  297. #clock-cells = <0x00>;
  298. compatible = "allwinner,sunxi-periph-clock";
  299. clock-output-names = "ahb2";
  300. };
  301.  
  302. ahb3 {
  303. #clock-cells = <0x00>;
  304. compatible = "allwinner,sunxi-periph-clock";
  305. clock-output-names = "ahb3";
  306. };
  307.  
  308. apb1 {
  309. #clock-cells = <0x00>;
  310. compatible = "allwinner,sunxi-periph-clock";
  311. clock-output-names = "apb1";
  312. };
  313.  
  314. apb2 {
  315. #clock-cells = <0x00>;
  316. compatible = "allwinner,sunxi-periph-clock";
  317. clock-output-names = "apb2";
  318. linux,phandle = <0xae>;
  319. phandle = <0xae>;
  320. };
  321.  
  322. mbus {
  323. #clock-cells = <0x00>;
  324. compatible = "allwinner,sunxi-periph-clock";
  325. clock-output-names = "mbus";
  326. };
  327.  
  328. de {
  329. #clock-cells = <0x00>;
  330. compatible = "allwinner,sunxi-periph-clock";
  331. assigned-clock-parents = <0x09>;
  332. assigned-clock-rates = <0x297c1e00>;
  333. clock-output-names = "de";
  334. linux,phandle = <0x87>;
  335. phandle = <0x87>;
  336. };
  337.  
  338. di {
  339. #clock-cells = <0x00>;
  340. compatible = "allwinner,sunxi-periph-clock";
  341. clock-output-names = "di";
  342. linux,phandle = <0xac>;
  343. phandle = <0xac>;
  344. };
  345.  
  346. gpu {
  347. #clock-cells = <0x00>;
  348. compatible = "allwinner,sunxi-periph-clock";
  349. clock-output-names = "gpu";
  350. linux,phandle = <0xda>;
  351. phandle = <0xda>;
  352. };
  353.  
  354. ce {
  355. #clock-cells = <0x00>;
  356. compatible = "allwinner,sunxi-periph-clock";
  357. clock-output-names = "ce";
  358. linux,phandle = <0xab>;
  359. phandle = <0xab>;
  360. };
  361.  
  362. ve {
  363. #clock-cells = <0x00>;
  364. compatible = "allwinner,sunxi-periph-clock";
  365. clock-output-names = "ve";
  366. linux,phandle = <0x18>;
  367. phandle = <0x18>;
  368. };
  369.  
  370. emce {
  371. #clock-cells = <0x00>;
  372. compatible = "allwinner,sunxi-periph-clock";
  373. clock-output-names = "emce";
  374. linux,phandle = <0xaa>;
  375. phandle = <0xaa>;
  376. };
  377.  
  378. vp9 {
  379. #clock-cells = <0x00>;
  380. compatible = "allwinner,sunxi-periph-clock";
  381. clock-output-names = "vp9";
  382. linux,phandle = <0x1a>;
  383. phandle = <0x1a>;
  384. };
  385.  
  386. dma {
  387. #clock-cells = <0x00>;
  388. compatible = "allwinner,sunxi-periph-clock";
  389. clock-output-names = "dma";
  390. linux,phandle = <0x0c>;
  391. phandle = <0x0c>;
  392. };
  393.  
  394. msgbox {
  395. #clock-cells = <0x00>;
  396. compatible = "allwinner,sunxi-periph-clock";
  397. clock-output-names = "msgbox";
  398. linux,phandle = <0x0f>;
  399. phandle = <0x0f>;
  400. };
  401.  
  402. hwspinlock_rst {
  403. #clock-cells = <0x00>;
  404. compatible = "allwinner,sunxi-periph-clock";
  405. clock-output-names = "hwspinlock_rst";
  406. linux,phandle = <0x10>;
  407. phandle = <0x10>;
  408. };
  409.  
  410. hwspinlock_bus {
  411. #clock-cells = <0x00>;
  412. compatible = "allwinner,sunxi-periph-clock";
  413. clock-output-names = "hwspinlock_bus";
  414. linux,phandle = <0x11>;
  415. phandle = <0x11>;
  416. };
  417.  
  418. hstimer {
  419. #clock-cells = <0x00>;
  420. compatible = "allwinner,sunxi-periph-clock";
  421. clock-output-names = "hstimer";
  422. };
  423.  
  424. avs {
  425. #clock-cells = <0x00>;
  426. compatible = "allwinner,sunxi-periph-clock";
  427. clock-output-names = "avs";
  428. };
  429.  
  430. dbgsys {
  431. #clock-cells = <0x00>;
  432. compatible = "allwinner,sunxi-periph-clock";
  433. clock-output-names = "dbgsys";
  434. };
  435.  
  436. pwm {
  437. #clock-cells = <0x00>;
  438. compatible = "allwinner,sunxi-periph-clock";
  439. clock-output-names = "pwm";
  440. linux,phandle = <0x93>;
  441. phandle = <0x93>;
  442. };
  443.  
  444. iommu {
  445. #clock-cells = <0x00>;
  446. compatible = "allwinner,sunxi-periph-clock";
  447. clock-output-names = "iommu";
  448. linux,phandle = <0xd8>;
  449. phandle = <0xd8>;
  450. };
  451.  
  452. sdram {
  453. #clock-cells = <0x00>;
  454. compatible = "allwinner,sunxi-periph-clock";
  455. clock-output-names = "sdram";
  456. };
  457.  
  458. nand0 {
  459. #clock-cells = <0x00>;
  460. compatible = "allwinner,sunxi-periph-clock";
  461. clock-output-names = "nand0";
  462. linux,phandle = <0xb6>;
  463. phandle = <0xb6>;
  464. };
  465.  
  466. nand1 {
  467. #clock-cells = <0x00>;
  468. compatible = "allwinner,sunxi-periph-clock";
  469. clock-output-names = "nand1";
  470. linux,phandle = <0xb7>;
  471. phandle = <0xb7>;
  472. };
  473.  
  474. sdmmc0_mod {
  475. #clock-cells = <0x00>;
  476. compatible = "allwinner,sunxi-periph-clock";
  477. clock-output-names = "sdmmc0_mod";
  478. linux,phandle = <0x7b>;
  479. phandle = <0x7b>;
  480. };
  481.  
  482. sdmmc0_bus {
  483. #clock-cells = <0x00>;
  484. compatible = "allwinner,sunxi-periph-clock";
  485. clock-output-names = "sdmmc0_bus";
  486. linux,phandle = <0x7c>;
  487. phandle = <0x7c>;
  488. };
  489.  
  490. sdmmc0_rst {
  491. #clock-cells = <0x00>;
  492. compatible = "allwinner,sunxi-periph-clock";
  493. clock-output-names = "sdmmc0_rst";
  494. linux,phandle = <0x7d>;
  495. phandle = <0x7d>;
  496. };
  497.  
  498. sdmmc1_mod {
  499. #clock-cells = <0x00>;
  500. compatible = "allwinner,sunxi-periph-clock";
  501. clock-output-names = "sdmmc1_mod";
  502. linux,phandle = <0x82>;
  503. phandle = <0x82>;
  504. };
  505.  
  506. sdmmc1_bus {
  507. #clock-cells = <0x00>;
  508. compatible = "allwinner,sunxi-periph-clock";
  509. clock-output-names = "sdmmc1_bus";
  510. linux,phandle = <0x83>;
  511. phandle = <0x83>;
  512. };
  513.  
  514. sdmmc1_rst {
  515. #clock-cells = <0x00>;
  516. compatible = "allwinner,sunxi-periph-clock";
  517. clock-output-names = "sdmmc1_rst";
  518. linux,phandle = <0x84>;
  519. phandle = <0x84>;
  520. };
  521.  
  522. sdmmc2_mod {
  523. #clock-cells = <0x00>;
  524. compatible = "allwinner,sunxi-periph-clock";
  525. clock-output-names = "sdmmc2_mod";
  526. linux,phandle = <0x76>;
  527. phandle = <0x76>;
  528. };
  529.  
  530. sdmmc2_bus {
  531. #clock-cells = <0x00>;
  532. compatible = "allwinner,sunxi-periph-clock";
  533. clock-output-names = "sdmmc2_bus";
  534. linux,phandle = <0x77>;
  535. phandle = <0x77>;
  536. };
  537.  
  538. sdmmc2_rst {
  539. #clock-cells = <0x00>;
  540. compatible = "allwinner,sunxi-periph-clock";
  541. clock-output-names = "sdmmc2_rst";
  542. linux,phandle = <0x78>;
  543. phandle = <0x78>;
  544. };
  545.  
  546. uart0 {
  547. #clock-cells = <0x00>;
  548. compatible = "allwinner,sunxi-periph-clock";
  549. clock-output-names = "uart0";
  550. linux,phandle = <0x1c>;
  551. phandle = <0x1c>;
  552. };
  553.  
  554. uart1 {
  555. #clock-cells = <0x00>;
  556. compatible = "allwinner,sunxi-periph-clock";
  557. clock-output-names = "uart1";
  558. linux,phandle = <0x1f>;
  559. phandle = <0x1f>;
  560. };
  561.  
  562. uart2 {
  563. #clock-cells = <0x00>;
  564. compatible = "allwinner,sunxi-periph-clock";
  565. clock-output-names = "uart2";
  566. linux,phandle = <0x22>;
  567. phandle = <0x22>;
  568. };
  569.  
  570. uart3 {
  571. #clock-cells = <0x00>;
  572. compatible = "allwinner,sunxi-periph-clock";
  573. clock-output-names = "uart3";
  574. linux,phandle = <0x25>;
  575. phandle = <0x25>;
  576. };
  577.  
  578. twi0 {
  579. #clock-cells = <0x00>;
  580. compatible = "allwinner,sunxi-periph-clock";
  581. clock-output-names = "twi0";
  582. linux,phandle = <0x28>;
  583. phandle = <0x28>;
  584. };
  585.  
  586. twi1 {
  587. #clock-cells = <0x00>;
  588. compatible = "allwinner,sunxi-periph-clock";
  589. clock-output-names = "twi1";
  590. linux,phandle = <0x2b>;
  591. phandle = <0x2b>;
  592. };
  593.  
  594. twi2 {
  595. #clock-cells = <0x00>;
  596. compatible = "allwinner,sunxi-periph-clock";
  597. clock-output-names = "twi2";
  598. linux,phandle = <0x2e>;
  599. phandle = <0x2e>;
  600. };
  601.  
  602. twi3 {
  603. #clock-cells = <0x00>;
  604. compatible = "allwinner,sunxi-periph-clock";
  605. clock-output-names = "twi3";
  606. linux,phandle = <0x31>;
  607. phandle = <0x31>;
  608. };
  609.  
  610. scr0 {
  611. #clock-cells = <0x00>;
  612. compatible = "allwinner,sunxi-periph-clock";
  613. clock-output-names = "scr0";
  614. linux,phandle = <0xad>;
  615. phandle = <0xad>;
  616. };
  617.  
  618. scr1 {
  619. #clock-cells = <0x00>;
  620. compatible = "allwinner,sunxi-periph-clock";
  621. clock-output-names = "scr1";
  622. linux,phandle = <0xb2>;
  623. phandle = <0xb2>;
  624. };
  625.  
  626. spi0 {
  627. #clock-cells = <0x00>;
  628. compatible = "allwinner,sunxi-periph-clock";
  629. clock-output-names = "spi0";
  630. linux,phandle = <0x67>;
  631. phandle = <0x67>;
  632. };
  633.  
  634. spi1 {
  635. #clock-cells = <0x00>;
  636. compatible = "allwinner,sunxi-periph-clock";
  637. clock-output-names = "spi1";
  638. linux,phandle = <0x6b>;
  639. phandle = <0x6b>;
  640. };
  641.  
  642. gmac {
  643. #clock-cells = <0x00>;
  644. compatible = "allwinner,sunxi-periph-clock";
  645. clock-output-names = "gmac";
  646. linux,phandle = <0xd2>;
  647. phandle = <0xd2>;
  648. };
  649.  
  650. sata {
  651. #clock-cells = <0x00>;
  652. compatible = "allwinner,sunxi-periph-clock";
  653. clock-output-names = "sata";
  654. };
  655.  
  656. sata_24m {
  657. #clock-cells = <0x00>;
  658. compatible = "allwinner,sunxi-periph-clock";
  659. clock-output-names = "sata_24m";
  660. };
  661.  
  662. ts {
  663. #clock-cells = <0x00>;
  664. compatible = "allwinner,sunxi-periph-clock";
  665. clock-output-names = "ts";
  666. linux,phandle = <0xbb>;
  667. phandle = <0xbb>;
  668. };
  669.  
  670. irtx {
  671. #clock-cells = <0x00>;
  672. compatible = "allwinner,sunxi-periph-clock";
  673. clock-output-names = "irtx";
  674. };
  675.  
  676. ths {
  677. #clock-cells = <0x00>;
  678. compatible = "allwinner,sunxi-periph-clock";
  679. clock-output-names = "ths";
  680. linux,phandle = <0xc4>;
  681. phandle = <0xc4>;
  682. };
  683.  
  684. i2s0 {
  685. #clock-cells = <0x00>;
  686. compatible = "allwinner,sunxi-periph-clock";
  687. clock-output-names = "i2s0";
  688. linux,phandle = <0x42>;
  689. phandle = <0x42>;
  690. };
  691.  
  692. i2s1 {
  693. #clock-cells = <0x00>;
  694. compatible = "allwinner,sunxi-periph-clock";
  695. clock-output-names = "i2s1";
  696. linux,phandle = <0x45>;
  697. phandle = <0x45>;
  698. };
  699.  
  700. i2s2 {
  701. #clock-cells = <0x00>;
  702. compatible = "allwinner,sunxi-periph-clock";
  703. clock-output-names = "i2s2";
  704. linux,phandle = <0x46>;
  705. phandle = <0x46>;
  706. };
  707.  
  708. i2s3 {
  709. #clock-cells = <0x00>;
  710. compatible = "allwinner,sunxi-periph-clock";
  711. clock-output-names = "i2s3";
  712. linux,phandle = <0x49>;
  713. phandle = <0x49>;
  714. };
  715.  
  716. spdif {
  717. #clock-cells = <0x00>;
  718. compatible = "allwinner,sunxi-periph-clock";
  719. clock-output-names = "spdif";
  720. linux,phandle = <0x4c>;
  721. phandle = <0x4c>;
  722. };
  723.  
  724. dmic {
  725. #clock-cells = <0x00>;
  726. compatible = "allwinner,sunxi-periph-clock";
  727. clock-output-names = "dmic";
  728. linux,phandle = <0x4f>;
  729. phandle = <0x4f>;
  730. };
  731.  
  732. ahub {
  733. #clock-cells = <0x00>;
  734. compatible = "allwinner,sunxi-periph-clock";
  735. clock-output-names = "ahub";
  736. linux,phandle = <0x52>;
  737. phandle = <0x52>;
  738. };
  739.  
  740. usbphy0 {
  741. #clock-cells = <0x00>;
  742. compatible = "allwinner,sunxi-periph-clock";
  743. clock-output-names = "usbphy0";
  744. linux,phandle = <0x34>;
  745. phandle = <0x34>;
  746. };
  747.  
  748. usbphy1 {
  749. #clock-cells = <0x00>;
  750. compatible = "allwinner,sunxi-periph-clock";
  751. clock-output-names = "usbphy1";
  752. linux,phandle = <0x3a>;
  753. phandle = <0x3a>;
  754. };
  755.  
  756. usbphy3 {
  757. #clock-cells = <0x00>;
  758. compatible = "allwinner,sunxi-periph-clock";
  759. clock-output-names = "usbphy3";
  760. linux,phandle = <0x3c>;
  761. phandle = <0x3c>;
  762. };
  763.  
  764. usbohci0 {
  765. #clock-cells = <0x00>;
  766. compatible = "allwinner,sunxi-periph-clock";
  767. clock-output-names = "usbohci0";
  768. linux,phandle = <0x37>;
  769. phandle = <0x37>;
  770. };
  771.  
  772. usbohci0_12m {
  773. #clock-cells = <0x00>;
  774. compatible = "allwinner,sunxi-periph-clock";
  775. clock-output-names = "usbohci0_12m";
  776. linux,phandle = <0x38>;
  777. phandle = <0x38>;
  778. };
  779.  
  780. usbohci3 {
  781. #clock-cells = <0x00>;
  782. compatible = "allwinner,sunxi-periph-clock";
  783. clock-output-names = "usbohci3";
  784. linux,phandle = <0x40>;
  785. phandle = <0x40>;
  786. };
  787.  
  788. usbohci3_12m {
  789. #clock-cells = <0x00>;
  790. compatible = "allwinner,sunxi-periph-clock";
  791. clock-output-names = "usbohci3_12m";
  792. linux,phandle = <0x41>;
  793. phandle = <0x41>;
  794. };
  795.  
  796. usbehci0 {
  797. #clock-cells = <0x00>;
  798. compatible = "allwinner,sunxi-periph-clock";
  799. clock-output-names = "usbehci0";
  800. linux,phandle = <0x36>;
  801. phandle = <0x36>;
  802. };
  803.  
  804. usbehci3 {
  805. #clock-cells = <0x00>;
  806. compatible = "allwinner,sunxi-periph-clock";
  807. clock-output-names = "usbehci3";
  808. linux,phandle = <0x3d>;
  809. phandle = <0x3d>;
  810. };
  811.  
  812. usb3_0_host {
  813. #clock-cells = <0x00>;
  814. compatible = "allwinner,sunxi-periph-clock";
  815. clock-output-names = "usb3_0_host";
  816. linux,phandle = <0x3b>;
  817. phandle = <0x3b>;
  818. };
  819.  
  820. usbotg {
  821. #clock-cells = <0x00>;
  822. compatible = "allwinner,sunxi-periph-clock";
  823. clock-output-names = "usbotg";
  824. linux,phandle = <0x35>;
  825. phandle = <0x35>;
  826. };
  827.  
  828. usbhsic {
  829. #clock-cells = <0x00>;
  830. compatible = "allwinner,sunxi-periph-clock";
  831. clock-output-names = "usbhsic";
  832. linux,phandle = <0x3e>;
  833. phandle = <0x3e>;
  834. };
  835.  
  836. pcieref {
  837. #clock-cells = <0x00>;
  838. compatible = "allwinner,sunxi-periph-clock";
  839. clock-output-names = "pcieref";
  840. linux,phandle = <0x6f>;
  841. phandle = <0x6f>;
  842. };
  843.  
  844. pciemaxi {
  845. #clock-cells = <0x00>;
  846. compatible = "allwinner,sunxi-periph-clock";
  847. assigned-clock-rates = <0xbebc200>;
  848. clock-output-names = "pciemaxi";
  849. linux,phandle = <0x70>;
  850. phandle = <0x70>;
  851. };
  852.  
  853. pcieaux {
  854. #clock-cells = <0x00>;
  855. compatible = "allwinner,sunxi-periph-clock";
  856. assigned-clock-rates = <0xf4240>;
  857. clock-output-names = "pcieaux";
  858. linux,phandle = <0x71>;
  859. phandle = <0x71>;
  860. };
  861.  
  862. pcie_bus {
  863. #clock-cells = <0x00>;
  864. compatible = "allwinner,sunxi-periph-clock";
  865. clock-output-names = "pcie_bus";
  866. linux,phandle = <0x72>;
  867. phandle = <0x72>;
  868. };
  869.  
  870. pcie_power {
  871. #clock-cells = <0x00>;
  872. compatible = "allwinner,sunxi-periph-clock";
  873. clock-output-names = "pcie_power";
  874. linux,phandle = <0x73>;
  875. phandle = <0x73>;
  876. };
  877.  
  878. pcie_rst {
  879. #clock-cells = <0x00>;
  880. compatible = "allwinner,sunxi-periph-clock";
  881. clock-output-names = "pcie_rst";
  882. linux,phandle = <0x74>;
  883. phandle = <0x74>;
  884. };
  885.  
  886. hdmi {
  887. #clock-cells = <0x00>;
  888. compatible = "allwinner,sunxi-periph-clock";
  889. assigned-clock-parents = <0x06>;
  890. clock-output-names = "hdmi";
  891. linux,phandle = <0x8b>;
  892. phandle = <0x8b>;
  893. };
  894.  
  895. hdmi_slow {
  896. #clock-cells = <0x00>;
  897. compatible = "allwinner,sunxi-periph-clock";
  898. clock-output-names = "hdmi_slow";
  899. linux,phandle = <0x8c>;
  900. phandle = <0x8c>;
  901. };
  902.  
  903. hdmi_cec {
  904. #clock-cells = <0x00>;
  905. compatible = "allwinner,sunxi-periph-clock";
  906. clock-output-names = "hdmi_cec";
  907. linux,phandle = <0x8e>;
  908. phandle = <0x8e>;
  909. };
  910.  
  911. display_top {
  912. #clock-cells = <0x00>;
  913. compatible = "allwinner,sunxi-periph-clock";
  914. clock-output-names = "display_top";
  915. linux,phandle = <0x88>;
  916. phandle = <0x88>;
  917. };
  918.  
  919. tcon_lcd {
  920. #clock-cells = <0x00>;
  921. compatible = "allwinner,sunxi-periph-clock";
  922. clock-output-names = "tcon_lcd";
  923. linux,phandle = <0x89>;
  924. phandle = <0x89>;
  925. };
  926.  
  927. tcon_tv {
  928. #clock-cells = <0x00>;
  929. compatible = "allwinner,sunxi-periph-clock";
  930. assigned-clock-parents = <0x06>;
  931. clock-output-names = "tcon_tv";
  932. linux,phandle = <0x8a>;
  933. phandle = <0x8a>;
  934. };
  935.  
  936. csi_misc {
  937. #clock-cells = <0x00>;
  938. compatible = "allwinner,sunxi-periph-clock";
  939. clock-output-names = "csi_misc";
  940. linux,phandle = <0x9e>;
  941. phandle = <0x9e>;
  942. };
  943.  
  944. csi_top {
  945. #clock-cells = <0x00>;
  946. compatible = "allwinner,sunxi-periph-clock";
  947. clock-output-names = "csi_top";
  948. linux,phandle = <0x9a>;
  949. phandle = <0x9a>;
  950. };
  951.  
  952. csi_master0 {
  953. #clock-cells = <0x00>;
  954. compatible = "allwinner,sunxi-periph-clock";
  955. clock-output-names = "csi_master0";
  956. linux,phandle = <0x9b>;
  957. phandle = <0x9b>;
  958. };
  959.  
  960. hdmi_hdcp {
  961. #clock-cells = <0x00>;
  962. compatible = "allwinner,sunxi-periph-clock";
  963. assigned-clock-parents = <0x03>;
  964. clock-output-names = "hdmi_hdcp";
  965. linux,phandle = <0x8d>;
  966. phandle = <0x8d>;
  967. };
  968.  
  969. pio {
  970. #clock-cells = <0x00>;
  971. compatible = "allwinner,sunxi-periph-clock";
  972. clock-output-names = "pio";
  973. linux,phandle = <0x0b>;
  974. phandle = <0x0b>;
  975. };
  976.  
  977. cpurcir {
  978. #clock-cells = <0x00>;
  979. compatible = "allwinner,sunxi-periph-cpus-clock";
  980. clock-output-names = "cpurcir";
  981. linux,phandle = <0x13>;
  982. phandle = <0x13>;
  983. };
  984.  
  985. losc_out {
  986. #clock-cells = <0x00>;
  987. compatible = "allwinner,sunxi-periph-cpus-clock";
  988. clock-output-names = "losc_out";
  989. linux,phandle = <0xdb>;
  990. phandle = <0xdb>;
  991. };
  992.  
  993. cpurcpus_pll {
  994. #clock-cells = <0x00>;
  995. compatible = "allwinner,sunxi-periph-cpus-clock";
  996. clock-output-names = "cpurcpus_pll";
  997. };
  998.  
  999. cpurcpus {
  1000. #clock-cells = <0x00>;
  1001. compatible = "allwinner,sunxi-periph-cpus-clock";
  1002. clock-output-names = "cpurcpus";
  1003. };
  1004.  
  1005. cpurahbs {
  1006. #clock-cells = <0x00>;
  1007. compatible = "allwinner,sunxi-periph-cpus-clock";
  1008. clock-output-names = "cpurahbs";
  1009. };
  1010.  
  1011. cpurapbs1 {
  1012. #clock-cells = <0x00>;
  1013. compatible = "allwinner,sunxi-periph-cpus-clock";
  1014. clock-output-names = "cpurapbs1";
  1015. };
  1016.  
  1017. cpurapbs2_pll {
  1018. #clock-cells = <0x00>;
  1019. compatible = "allwinner,sunxi-periph-cpus-clock";
  1020. clock-output-names = "cpurapbs2_pll";
  1021. };
  1022.  
  1023. cpurapbs2 {
  1024. #clock-cells = <0x00>;
  1025. compatible = "allwinner,sunxi-periph-cpus-clock";
  1026. clock-output-names = "cpurapbs2";
  1027. };
  1028.  
  1029. cpurpio {
  1030. #clock-cells = <0x00>;
  1031. compatible = "allwinner,sunxi-periph-cpus-clock";
  1032. clock-output-names = "cpurpio";
  1033. linux,phandle = <0x0a>;
  1034. phandle = <0x0a>;
  1035. };
  1036.  
  1037. spwm {
  1038. #clock-cells = <0x00>;
  1039. compatible = "allwinner,sunxi-periph-cpus-clock";
  1040. clock-output-names = "spwm";
  1041. linux,phandle = <0x96>;
  1042. phandle = <0x96>;
  1043. };
  1044.  
  1045. dcxo_out {
  1046. #clock-cells = <0x00>;
  1047. compatible = "allwinner,sunxi-periph-cpus-clock";
  1048. clock-output-names = "dcxo_out";
  1049. };
  1050. };
  1051.  
  1052. soc@03000000 {
  1053. compatible = "simple-bus";
  1054. #address-cells = <0x02>;
  1055. #size-cells = <0x02>;
  1056. ranges;
  1057. device_type = "soc";
  1058.  
  1059. pinctrl@07022000 {
  1060. compatible = "allwinner,sun50iw6p1-r-pinctrl";
  1061. reg = <0x00 0x7022000 0x00 0x400>;
  1062. interrupts = <0x00 0x69 0x04 0x00 0x6f 0x04>;
  1063. clocks = <0x0a>;
  1064. device_type = "r_pio";
  1065. gpio-controller;
  1066. interrupt-controller;
  1067. #interrupt-cells = <0x02>;
  1068. #size-cells = <0x00>;
  1069. #gpio-cells = <0x06>;
  1070. linux,phandle = <0xdc>;
  1071. phandle = <0xdc>;
  1072.  
  1073. s_twi0@0 {
  1074. allwinner,pins = "PL0\0PL1";
  1075. allwinner,function = "s_twi0";
  1076. allwinner,muxsel = <0x03>;
  1077. allwinner,drive = <0x00>;
  1078. allwinner,pull = <0x01>;
  1079. linux,phandle = <0x15>;
  1080. phandle = <0x15>;
  1081. };
  1082.  
  1083. s_cir0@0 {
  1084. allwinner,pins = "PL9";
  1085. allwinner,function = "s_cir0";
  1086. allwinner,muxsel = <0x02>;
  1087. allwinner,drive = <0x02>;
  1088. allwinner,pull = <0x01>;
  1089. linux,phandle = <0x12>;
  1090. phandle = <0x12>;
  1091. };
  1092.  
  1093. twi_para@0 {
  1094. linux,phandle = <0xdf>;
  1095. phandle = <0xdf>;
  1096. allwinner,pins = "PL0\0PL1";
  1097. allwinner,function = "twi_para";
  1098. allwinner,pname = "twi_scl\0twi_sda";
  1099. allwinner,muxsel = <0x03>;
  1100. allwinner,pull = <0x01>;
  1101. allwinner,drive = <0x00>;
  1102. allwinner,data = <0xffffffff>;
  1103. };
  1104.  
  1105. pwm16@0 {
  1106. linux,phandle = <0x106>;
  1107. phandle = <0x106>;
  1108. allwinner,pins = "PL8";
  1109. allwinner,function = "pwm16";
  1110. allwinner,pname = "pwm_positive";
  1111. allwinner,muxsel = <0x02>;
  1112. allwinner,pull = <0x00>;
  1113. allwinner,drive = <0xffffffff>;
  1114. allwinner,data = <0xffffffff>;
  1115. };
  1116.  
  1117. pwm16@1 {
  1118. linux,phandle = <0x107>;
  1119. phandle = <0x107>;
  1120. allwinner,pins = "PL8";
  1121. allwinner,function = "pwm16";
  1122. allwinner,pname = "pwm_positive";
  1123. allwinner,muxsel = <0x07>;
  1124. allwinner,pull = <0x00>;
  1125. allwinner,drive = <0xffffffff>;
  1126. allwinner,data = <0xffffffff>;
  1127. };
  1128.  
  1129. s_uart0@0 {
  1130. linux,phandle = <0x10d>;
  1131. phandle = <0x10d>;
  1132. allwinner,pins = "PL2\0PL3";
  1133. allwinner,function = "s_uart0";
  1134. allwinner,pname = "s_uart0_tx\0s_uart0_rx";
  1135. allwinner,muxsel = <0x02>;
  1136. allwinner,pull = <0xffffffff>;
  1137. allwinner,drive = <0xffffffff>;
  1138. allwinner,data = <0xffffffff>;
  1139. };
  1140.  
  1141. s_rsb0@0 {
  1142. linux,phandle = <0x10e>;
  1143. phandle = <0x10e>;
  1144. allwinner,pins = "PL0\0PL1";
  1145. allwinner,function = "s_rsb0";
  1146. allwinner,pname = "s_rsb0_sck\0s_rsb0_sda";
  1147. allwinner,muxsel = <0x02>;
  1148. allwinner,pull = <0x01>;
  1149. allwinner,drive = <0x02>;
  1150. allwinner,data = <0xffffffff>;
  1151. };
  1152.  
  1153. s_jtag0@0 {
  1154. linux,phandle = <0x10f>;
  1155. phandle = <0x10f>;
  1156. allwinner,pins = "PL4\0PL5\0PL6\0PL7";
  1157. allwinner,function = "s_jtag0";
  1158. allwinner,pname = "s_jtag0_tms\0s_jtag0_tck\0s_jtag0_tdo\0s_jtag0_tdi";
  1159. allwinner,muxsel = <0x02>;
  1160. allwinner,pull = <0x01>;
  1161. allwinner,drive = <0x02>;
  1162. allwinner,data = <0xffffffff>;
  1163. };
  1164. };
  1165.  
  1166. pinctrl@0300b000 {
  1167. compatible = "allwinner,sun50iw6p1-pinctrl";
  1168. reg = <0x00 0x300b000 0x00 0x400>;
  1169. interrupts = <0x00 0x33 0x04 0x00 0x35 0x04 0x00 0x36 0x04 0x00 0x3b 0x04>;
  1170. device_type = "pio";
  1171. clocks = <0x0b>;
  1172. gpio-controller;
  1173. interrupt-controller;
  1174. #interrupt-cells = <0x02>;
  1175. #size-cells = <0x00>;
  1176. #gpio-cells = <0x06>;
  1177. linux,phandle = <0x81>;
  1178. phandle = <0x81>;
  1179.  
  1180. twi3@1 {
  1181. allwinner,pins = "PB17\0PB18";
  1182. allwinner,function = "io_disabled";
  1183. allwinner,muxsel = <0x07>;
  1184. allwinner,drive = <0x01>;
  1185. allwinner,pull = <0x00>;
  1186. linux,phandle = <0x33>;
  1187. phandle = <0x33>;
  1188. };
  1189.  
  1190. ts0@0 {
  1191. allwinner,pins = "PD0\0PD1\0PD2\0PD3\0PD4\0PD5\0PD6\0PD7\0PD8\0PD9\0PD10\0PD11";
  1192. allwinner,pname = "ts0_clk\0ts0_err\0ts0_sync\0ts0_dvld\0ts0_d0\0ts0_d1\0ts0_d2\0ts0_d3\0ts0_d4\0ts0_d5\0ts0_d6\0ts0_d7";
  1193. allwinner,function = "ts0";
  1194. allwinner,muxsel = <0x03>;
  1195. allwinner,drive = <0x01>;
  1196. allwinner,pull = <0x00>;
  1197. linux,phandle = <0xbc>;
  1198. phandle = <0xbc>;
  1199. };
  1200.  
  1201. ts0_sleep@0 {
  1202. allwinner,pins = "PD0\0PD1\0PD2\0PD3\0PD4\0PD5\0PD6\0PD7\0PD8\0PD9\0PD10\0PD11";
  1203. allwinner,pname = "ts0_clk\0ts0_err\0ts0_sync\0ts0_dvld\0ts0_d0\0ts0_d1\0ts0_d2\0ts0_d3\0ts0_d4\0ts0_d5\0ts0_d6\0ts0_d7";
  1204. allwinner,function = "io_disabled";
  1205. allwinner,muxsel = <0x07>;
  1206. allwinner,drive = <0x01>;
  1207. allwinner,pull = <0x00>;
  1208. linux,phandle = <0xc0>;
  1209. phandle = <0xc0>;
  1210. };
  1211.  
  1212. ts1@0 {
  1213. allwinner,pins = "PD12\0PD13\0PD14\0PD15\0PD16";
  1214. allwinner,pname = "ts1_clk\0ts1_err\0ts1_sync\0ts1_dvld\0ts1_d0";
  1215. allwinner,function = "ts1";
  1216. allwinner,muxsel = <0x03>;
  1217. allwinner,drive = <0x01>;
  1218. allwinner,pull = <0x00>;
  1219. linux,phandle = <0xbd>;
  1220. phandle = <0xbd>;
  1221. };
  1222.  
  1223. ts1_sleep@0 {
  1224. allwinner,pins = "PD12\0PD13\0PD14\0PD15\0PD16";
  1225. allwinner,pname = "ts1_clk\0ts1_err\0ts1_sync\0ts1_dvld\0ts1_d0";
  1226. allwinner,function = "io_disabled";
  1227. allwinner,muxsel = <0x07>;
  1228. allwinner,drive = <0x01>;
  1229. allwinner,pull = <0x00>;
  1230. linux,phandle = <0xc1>;
  1231. phandle = <0xc1>;
  1232. };
  1233.  
  1234. ts2@0 {
  1235. allwinner,pins = "PD17\0PD18\0PD19\0PD20\0PD21";
  1236. allwinner,pname = "ts2_clk\0ts2_err\0ts2_sync\0ts2_dvld\0ts2_d0";
  1237. allwinner,function = "ts2";
  1238. allwinner,muxsel = <0x03>;
  1239. allwinner,drive = <0x01>;
  1240. allwinner,pull = <0x00>;
  1241. linux,phandle = <0xbe>;
  1242. phandle = <0xbe>;
  1243. };
  1244.  
  1245. ts2_sleep@0 {
  1246. allwinner,pins = "PD17\0PD18\0PD19\0PD20\0PD21";
  1247. allwinner,pname = "ts2_clk\0ts2_err\0ts2_sync\0ts2_dvld\0ts2_d0";
  1248. allwinner,function = "io_disabled";
  1249. allwinner,muxsel = <0x07>;
  1250. allwinner,drive = <0x01>;
  1251. allwinner,pull = <0x00>;
  1252. linux,phandle = <0xc2>;
  1253. phandle = <0xc2>;
  1254. };
  1255.  
  1256. ts3@0 {
  1257. allwinner,pins = "PD22\0PD23\0PD24\0PD25\0PD26";
  1258. allwinner,pname = "ts3_clk\0ts3_err\0ts3_sync\0ts3_dvld\0ts3_d0";
  1259. allwinner,function = "ts3";
  1260. allwinner,muxsel = <0x03>;
  1261. allwinner,drive = <0x01>;
  1262. allwinner,pull = <0x00>;
  1263. linux,phandle = <0xbf>;
  1264. phandle = <0xbf>;
  1265. };
  1266.  
  1267. ts3_sleep@0 {
  1268. allwinner,pins = "PD22\0PD23\0PD24\0PD25\0PD26";
  1269. allwinner,pname = "ts3_clk\0ts3_err\0ts3_sync\0ts3_dvld\0ts3_d0";
  1270. allwinner,function = "io_disabled";
  1271. allwinner,muxsel = <0x07>;
  1272. allwinner,drive = <0x01>;
  1273. allwinner,pull = <0x00>;
  1274. linux,phandle = <0xc3>;
  1275. phandle = <0xc3>;
  1276. };
  1277.  
  1278. sdc0@1 {
  1279. allwinner,pins = "PF0\0PF1\0PF2\0PF3\0PF4\0PF5";
  1280. allwinner,function = "io_disabled";
  1281. allwinner,muxsel = <0x07>;
  1282. allwinner,drive = <0x01>;
  1283. allwinner,pull = <0x01>;
  1284. linux,phandle = <0x7f>;
  1285. phandle = <0x7f>;
  1286. };
  1287.  
  1288. sdc0@2 {
  1289. allwinner,pins = "PF2\0PF4";
  1290. allwinner,function = "uart0";
  1291. allwinner,muxsel = <0x03>;
  1292. allwinner,drive = <0x01>;
  1293. allwinner,pull = <0x01>;
  1294. linux,phandle = <0x80>;
  1295. phandle = <0x80>;
  1296. };
  1297.  
  1298. sdc1@1 {
  1299. allwinner,pins = "PG0\0PG1\0PG2\0PG3\0PG4\0PG5";
  1300. allwinner,function = "io_disabled";
  1301. allwinner,muxsel = <0x07>;
  1302. allwinner,drive = <0x01>;
  1303. allwinner,pull = <0x01>;
  1304. linux,phandle = <0x86>;
  1305. phandle = <0x86>;
  1306. };
  1307.  
  1308. sdc2@1 {
  1309. allwinner,pins = "PC1\0PC4\0PC5\0PC6\0PC7\0PC8\0PC9\0PC10\0PC11\0PC12\0PC13\0PC14";
  1310. allwinner,function = "io_disabled";
  1311. allwinner,muxsel = <0x07>;
  1312. allwinner,drive = <0x01>;
  1313. allwinner,pull = <0x01>;
  1314. linux,phandle = <0x7a>;
  1315. phandle = <0x7a>;
  1316. };
  1317.  
  1318. daudio0@0 {
  1319. allwinner,pins = "PH0\0PH1\0PH2\0PH3\0PH4";
  1320. allwinner,function = "pcm0";
  1321. allwinner,muxsel = <0x03>;
  1322. allwinner,drive = <0x01>;
  1323. allwinner,pull = <0x00>;
  1324. linux,phandle = <0x43>;
  1325. phandle = <0x43>;
  1326. };
  1327.  
  1328. daudio0_sleep@0 {
  1329. allwinner,pins = "PH0\0PH1\0PH2\0PH3\0PH4";
  1330. allwinner,function = "io_disabled";
  1331. allwinner,muxsel = <0x07>;
  1332. allwinner,drive = <0x01>;
  1333. allwinner,pull = <0x00>;
  1334. linux,phandle = <0x44>;
  1335. phandle = <0x44>;
  1336. };
  1337.  
  1338. daudio2@0 {
  1339. allwinner,pins = "PG10\0PG11\0PG12\0PG13\0PG14";
  1340. allwinner,function = "pcm2";
  1341. allwinner,muxsel = <0x02>;
  1342. allwinner,drive = <0x01>;
  1343. allwinner,pull = <0x00>;
  1344. linux,phandle = <0x47>;
  1345. phandle = <0x47>;
  1346. };
  1347.  
  1348. daudio2_sleep@0 {
  1349. allwinner,pins = "PG10\0PG11\0PG12\0PG13\0PG14";
  1350. allwinner,function = "io_disabled";
  1351. allwinner,muxsel = <0x07>;
  1352. allwinner,drive = <0x01>;
  1353. allwinner,pull = <0x00>;
  1354. linux,phandle = <0x48>;
  1355. phandle = <0x48>;
  1356. };
  1357.  
  1358. daudio3@0 {
  1359. allwinner,pins = "PB12\0PB13\0PB14\0PB15\0PB16";
  1360. allwinner,function = "pcm3";
  1361. allwinner,muxsel = <0x02>;
  1362. allwinner,driver = <0x01>;
  1363. allwinner,pull = <0x00>;
  1364. linux,phandle = <0x4a>;
  1365. phandle = <0x4a>;
  1366. };
  1367.  
  1368. daudio3_sleep@0 {
  1369. allwinner,pins = "PB12\0PB13\0PB14\0PB15\0PB16";
  1370. allwinner,function = "io_disabled";
  1371. allwinner,muxsel = <0x07>;
  1372. allwinner,driver = <0x01>;
  1373. allwinner,pull = <0x00>;
  1374. linux,phandle = <0x4b>;
  1375. phandle = <0x4b>;
  1376. };
  1377.  
  1378. spdif@0 {
  1379. allwinner,pins = "PH5\0PH6\0PH7";
  1380. allwinner,function = "spdif0";
  1381. allwinner,muxsel = <0x03>;
  1382. allwinner,drive = <0x01>;
  1383. allwinner,pull = <0x00>;
  1384. linux,phandle = <0x4d>;
  1385. phandle = <0x4d>;
  1386. };
  1387.  
  1388. spdif_sleep@0 {
  1389. allwinner,pins = "PH5\0PH6\0PH7";
  1390. allwinner,function = "io_disabled";
  1391. allwinner,muxsel = <0x07>;
  1392. allwinner,drive = <0x01>;
  1393. allwinner,pull = <0x00>;
  1394. linux,phandle = <0x4e>;
  1395. phandle = <0x4e>;
  1396. };
  1397.  
  1398. dmic@0 {
  1399. allwinner,pins = "PD14\0PD15\0PD16\0PD17\0PD18";
  1400. allwinner,function = "dmic";
  1401. allwinner,muxsel = <0x04>;
  1402. allwinner,driver = <0x01>;
  1403. allwinner,pull = <0x00>;
  1404. linux,phandle = <0x50>;
  1405. phandle = <0x50>;
  1406. };
  1407.  
  1408. dmic_sleep@0 {
  1409. allwinner,pins = "PD14\0PD15\0PD16\0PD17\0PD18";
  1410. allwinner,function = "io_disabled";
  1411. allwinner,muxsel = <0x07>;
  1412. allwinner,driver = <0x01>;
  1413. allwinner,pull = <0x00>;
  1414. linux,phandle = <0x51>;
  1415. phandle = <0x51>;
  1416. };
  1417.  
  1418. ahub_daudio0@0 {
  1419. allwinner,pins = "PH0\0PH1\0PH2\0PH3\0PH4";
  1420. allwinner,function = "pcm0";
  1421. allwinner,muxsel = <0x04>;
  1422. allwinner,driver = <0x01>;
  1423. allwinner,pull = <0x00>;
  1424. linux,phandle = <0x53>;
  1425. phandle = <0x53>;
  1426. };
  1427.  
  1428. ahub_daudio0_sleep@0 {
  1429. allwinner,pins = "PH0\0PH1\0PH2\0PH3\0PH4";
  1430. allwinner,function = "io_disabled";
  1431. allwinner,muxsel = <0x07>;
  1432. allwinner,driver = <0x01>;
  1433. allwinner,pull = <0x00>;
  1434. linux,phandle = <0x54>;
  1435. phandle = <0x54>;
  1436. };
  1437.  
  1438. ahub_daudio2@0 {
  1439. allwinner,pins = "PG10\0PG11\0PG12\0PG13\0PG14";
  1440. allwinner,function = "pcm2";
  1441. allwinner,muxsel = <0x03>;
  1442. allwinner,drive = <0x01>;
  1443. allwinner,pull = <0x00>;
  1444. linux,phandle = <0x55>;
  1445. phandle = <0x55>;
  1446. };
  1447.  
  1448. ahub_daudio2_sleep@0 {
  1449. allwinner,pins = "PG10\0PG11\0PG12\0PG13\0PG14";
  1450. allwinner,function = "io_disabled";
  1451. allwinner,muxsel = <0x07>;
  1452. allwinner,drive = <0x01>;
  1453. allwinner,pull = <0x00>;
  1454. linux,phandle = <0x56>;
  1455. phandle = <0x56>;
  1456. };
  1457.  
  1458. ahub_daudio3@0 {
  1459. allwinner,pins = "PB12\0PB13\0PB14\0PB15\0PB16";
  1460. allwinner,function = "pcm3";
  1461. allwinner,muxsel = <0x04>;
  1462. allwinner,driver = <0x01>;
  1463. allwinner,pull = <0x00>;
  1464. linux,phandle = <0x57>;
  1465. phandle = <0x57>;
  1466. };
  1467.  
  1468. ahub_daudio3_sleep@0 {
  1469. allwinner,pins = "PB12\0PB13\0PB14\0PB15\0PB16";
  1470. allwinner,function = "io_disabled";
  1471. allwinner,muxsel = <0x07>;
  1472. allwinner,driver = <0x01>;
  1473. allwinner,pull = <0x00>;
  1474. linux,phandle = <0x58>;
  1475. phandle = <0x58>;
  1476. };
  1477.  
  1478. csi0@1 {
  1479. allwinner,pins = "PD0\0PD2\0PD3\0PD4\0PD5\0PD6\0PD7\0PD8\0PD9\0PD10\0PD11";
  1480. allwinner,pname = "csi0_pck\0csi0_hsync\0csi0_vsync\0csi0_d0\0csi0_d1\0csi0_d2\0csi0_d3\0csi0_d4\0csi0_d5\0csi0_d6\0csi0_d7";
  1481. allwinner,function = "io_disabled";
  1482. allwinner,muxsel = <0x07>;
  1483. allwinner,drive = <0x01>;
  1484. allwinner,pull = <0x00>;
  1485. allwinner,data = <0x00>;
  1486. linux,phandle = <0xa2>;
  1487. phandle = <0xa2>;
  1488. };
  1489.  
  1490. csi_mclk0@0 {
  1491. allwinner,pins = "PD1";
  1492. allwinner,pname = "csi_mclk0";
  1493. allwinner,function = "csi_mclk0";
  1494. allwinner,muxsel = <0x04>;
  1495. allwinner,drive = <0x01>;
  1496. allwinner,pull = <0x00>;
  1497. allwinner,data = <0x00>;
  1498. linux,phandle = <0x9c>;
  1499. phandle = <0x9c>;
  1500. };
  1501.  
  1502. csi_mclk0@1 {
  1503. allwinner,pins = "PD1";
  1504. allwinner,pname = "csi_mclk0";
  1505. allwinner,function = "io_disabled";
  1506. allwinner,muxsel = <0x07>;
  1507. allwinner,drive = <0x01>;
  1508. allwinner,pull = <0x00>;
  1509. allwinner,data = <0x00>;
  1510. linux,phandle = <0x9d>;
  1511. phandle = <0x9d>;
  1512. };
  1513.  
  1514. csi_cci0@0 {
  1515. allwinner,pins = "PD12\0PD13";
  1516. allwinner,pname = "csi_cci0_sck\0csi_cci0_sda";
  1517. allwinner,function = "csi_cci0";
  1518. allwinner,muxsel = <0x04>;
  1519. allwinner,drive = <0x01>;
  1520. allwinner,pull = <0x00>;
  1521. allwinner,data = <0x00>;
  1522. linux,phandle = <0x9f>;
  1523. phandle = <0x9f>;
  1524. };
  1525.  
  1526. csi_cci0@1 {
  1527. allwinner,pins = "PD12\0PD13";
  1528. allwinner,pname = "csi_cci0_sck\0csi_cci0_sda";
  1529. allwinner,function = "io_disabled";
  1530. allwinner,muxsel = <0x07>;
  1531. allwinner,drive = <0x01>;
  1532. allwinner,pull = <0x00>;
  1533. allwinner,data = <0x00>;
  1534. linux,phandle = <0xa0>;
  1535. phandle = <0xa0>;
  1536. };
  1537.  
  1538. scr0@0 {
  1539. allwinner,pins = "PG13\0PG14\0PG10\0PG11\0PG12";
  1540. allwinner,pname = "scr0_rst\0scr0_det\0scr0_vccen\0scr0_sck\0scr0_sda";
  1541. allwinner,function = "sim0";
  1542. allwinner,muxsel = <0x04>;
  1543. allwinner,drive = <0x00>;
  1544. allwinner,pull = <0x01>;
  1545. linux,phandle = <0xaf>;
  1546. phandle = <0xaf>;
  1547. };
  1548.  
  1549. scr0@1 {
  1550. allwinner,pins = "PG8\0PG9";
  1551. allwinner,pname = "scr0_vppen\0scr0_vppp";
  1552. allwinner,function = "sim0";
  1553. allwinner,muxsel = <0x04>;
  1554. allwinner,drive = <0x00>;
  1555. allwinner,pull = <0x01>;
  1556. linux,phandle = <0xb0>;
  1557. phandle = <0xb0>;
  1558. };
  1559.  
  1560. scr0@2 {
  1561. allwinner,pins = "PG8\0PG9\0PG10\0PG11\0PG12\0PG13\0PG14";
  1562. allwinner,function = "io_disabled";
  1563. allwinner,muxsel = <0x07>;
  1564. allwinner,drive = <0x00>;
  1565. allwinner,pull = <0x00>;
  1566. linux,phandle = <0xb1>;
  1567. phandle = <0xb1>;
  1568. };
  1569.  
  1570. scr1@0 {
  1571. allwinner,pins = "PH5\0PH6\0PH2\0PH3\0PH4";
  1572. allwinner,pname = "scr1_rst\0scr1_det\0scr1_vccen\0scr1_sck\0scr1_sda";
  1573. allwinner,function = "sim1";
  1574. allwinner,muxsel = <0x05>;
  1575. allwinner,drive = <0x01>;
  1576. allwinner,pull = <0x01>;
  1577. linux,phandle = <0xb3>;
  1578. phandle = <0xb3>;
  1579. };
  1580.  
  1581. scr1@1 {
  1582. allwinner,pins = "PH0\0PH1";
  1583. allwinner,pname = "scr1_vppen\0scr1_vppp";
  1584. allwinner,function = "sim1";
  1585. allwinner,muxsel = <0x05>;
  1586. allwinner,drive = <0x01>;
  1587. allwinner,pull = <0x01>;
  1588. linux,phandle = <0xb4>;
  1589. phandle = <0xb4>;
  1590. };
  1591.  
  1592. scr1@2 {
  1593. allwinner,pins = "PH0\0PH1\0PH2\0PH3\0PH4\0PH5\0PH6";
  1594. allwinner,function = "io_disabled";
  1595. allwinner,muxsel = <0x07>;
  1596. allwinner,drive = <0x01>;
  1597. allwinner,pull = <0x00>;
  1598. linux,phandle = <0xb5>;
  1599. phandle = <0xb5>;
  1600. };
  1601.  
  1602. nand0@2 {
  1603. allwinner,pins = "PC0\0PC1\0PC2\0PC3\0PC4\0PC5\0PC6\0PC7\0PC8\0PC9\0PC10\0PC11\0PC12\0PC13\0PC14\0PC15\0PC16";
  1604. allwinner,function = "io_disabled";
  1605. allwinner,muxsel = <0x07>;
  1606. allwinner,drive = <0x01>;
  1607. allwinner,pull = <0x00>;
  1608. linux,phandle = <0xba>;
  1609. phandle = <0xba>;
  1610. };
  1611.  
  1612. hdmi@1 {
  1613. allwinner,pins = "PH8\0PH9";
  1614. allwinner,function = "io_disabled";
  1615. allwinner,muxsel = <0x07>;
  1616. allwinner,drive = <0x01>;
  1617. allwinner,pull = <0x00>;
  1618. linux,phandle = <0x90>;
  1619. phandle = <0x90>;
  1620. };
  1621.  
  1622. hdmi@2 {
  1623. allwinner,pins = "PH10";
  1624. allwinner,function = "cec0";
  1625. allwinner,muxsel = <0x02>;
  1626. allwinner,drive = <0x01>;
  1627. allwinner,pull = <0x00>;
  1628. linux,phandle = <0x91>;
  1629. phandle = <0x91>;
  1630. };
  1631.  
  1632. hdmi@3 {
  1633. allwinner,pins = "PH10";
  1634. allwinner,function = "io_disabled";
  1635. allwinner,muxsel = <0x07>;
  1636. allwinner,drive = <0x01>;
  1637. allwinner,pull = <0x00>;
  1638. linux,phandle = <0x92>;
  1639. phandle = <0x92>;
  1640. };
  1641.  
  1642. ac200@2 {
  1643. allwinner,pins = "PB0";
  1644. allwinner,function = "ccir_clk";
  1645. allwinner,muxsel = <0x02>;
  1646. allwinner,drive = <0x01>;
  1647. allwinner,pull = <0x00>;
  1648. linux,phandle = <0x98>;
  1649. phandle = <0x98>;
  1650. };
  1651.  
  1652. ac200@3 {
  1653. allwinner,pins = "PB0";
  1654. allwinner,function = "io_disabled";
  1655. allwinner,muxsel = <0x07>;
  1656. allwinner,drive = <0x01>;
  1657. allwinner,pull = <0x00>;
  1658. linux,phandle = <0x99>;
  1659. phandle = <0x99>;
  1660. };
  1661.  
  1662. card0_boot_para@0 {
  1663. linux,phandle = <0xdd>;
  1664. phandle = <0xdd>;
  1665. allwinner,pins = "PF0\0PF1\0PF2\0PF3\0PF4\0PF5";
  1666. allwinner,function = "card0_boot_para";
  1667. allwinner,pname = "sdc_d1\0sdc_d0\0sdc_clk\0sdc_cmd\0sdc_d3\0sdc_d2";
  1668. allwinner,muxsel = <0x02>;
  1669. allwinner,pull = <0x01>;
  1670. allwinner,drive = <0x02>;
  1671. allwinner,data = <0xffffffff>;
  1672. };
  1673.  
  1674. card2_boot_para@0 {
  1675. linux,phandle = <0xde>;
  1676. phandle = <0xde>;
  1677. allwinner,pins = "PC1\0PC4\0PC5\0PC6\0PC7\0PC8\0PC9\0PC10\0PC11\0PC12\0PC13\0PC14";
  1678. allwinner,function = "card2_boot_para";
  1679. allwinner,pname = "sdc_ds\0sdc_clk\0sdc_cmd\0sdc_d0\0sdc_d1\0sdc_d2\0sdc_d3\0sdc_d4\0sdc_d5\0sdc_d6\0sdc_d7\0sdc_emmc_rst";
  1680. allwinner,muxsel = <0x03>;
  1681. allwinner,pull = <0x01>;
  1682. allwinner,drive = <0x03>;
  1683. allwinner,data = <0xffffffff>;
  1684. };
  1685.  
  1686. uart_para@0 {
  1687. linux,phandle = <0xe0>;
  1688. phandle = <0xe0>;
  1689. allwinner,pins = "PH0\0PH1";
  1690. allwinner,function = "uart_para";
  1691. allwinner,pname = "uart_debug_tx\0uart_debug_rx";
  1692. allwinner,muxsel = <0x02>;
  1693. allwinner,pull = <0x01>;
  1694. allwinner,drive = <0xffffffff>;
  1695. allwinner,data = <0xffffffff>;
  1696. };
  1697.  
  1698. jtag_para@0 {
  1699. linux,phandle = <0xe1>;
  1700. phandle = <0xe1>;
  1701. allwinner,pins = "PD23\0PD24\0PD25\0PD26";
  1702. allwinner,function = "jtag_para";
  1703. allwinner,pname = "jtag_ms\0jtag_ck\0jtag_do\0jtag_di";
  1704. allwinner,muxsel = <0x05>;
  1705. allwinner,pull = <0xffffffff>;
  1706. allwinner,drive = <0xffffffff>;
  1707. allwinner,data = <0xffffffff>;
  1708. };
  1709.  
  1710. gmac0@0 {
  1711. linux,phandle = <0xe2>;
  1712. phandle = <0xe2>;
  1713. allwinner,pins = "PA0\0PA1\0PA2\0PA3\0PA4\0PA5\0PA6\0PA7\0PA8\0PA9";
  1714. allwinner,function = "gmac0";
  1715. allwinner,pname = "gmac_rxd1\0gmac_rxd0\0gmac_crs\0gmac_rxerr\0gmac_txd1\0gmac_txd0\0gmac_txclk\0gmac_txen\0gmac_mdc\0gmac_mdio";
  1716. allwinner,muxsel = <0x02>;
  1717. allwinner,pull = <0xffffffff>;
  1718. allwinner,drive = <0x03>;
  1719. allwinner,data = <0xffffffff>;
  1720. };
  1721.  
  1722. twi0@0 {
  1723. linux,phandle = <0xe3>;
  1724. phandle = <0xe3>;
  1725. allwinner,pins = "PD25\0PD26";
  1726. allwinner,function = "twi0";
  1727. allwinner,pname = "twi0_scl\0twi0_sda";
  1728. allwinner,muxsel = <0x02>;
  1729. allwinner,pull = <0xffffffff>;
  1730. allwinner,drive = <0xffffffff>;
  1731. allwinner,data = <0xffffffff>;
  1732. };
  1733.  
  1734. twi0@1 {
  1735. linux,phandle = <0xe4>;
  1736. phandle = <0xe4>;
  1737. allwinner,pins = "PD25\0PD26";
  1738. allwinner,function = "twi0";
  1739. allwinner,pname = "twi0_scl\0twi0_sda";
  1740. allwinner,muxsel = <0x07>;
  1741. allwinner,pull = <0xffffffff>;
  1742. allwinner,drive = <0xffffffff>;
  1743. allwinner,data = <0xffffffff>;
  1744. };
  1745.  
  1746. twi1@0 {
  1747. linux,phandle = <0xe5>;
  1748. phandle = <0xe5>;
  1749. allwinner,pins = "PH5\0PH6";
  1750. allwinner,function = "twi1";
  1751. allwinner,pname = "twi1_scl\0twi1_sda";
  1752. allwinner,muxsel = <0x04>;
  1753. allwinner,pull = <0xffffffff>;
  1754. allwinner,drive = <0xffffffff>;
  1755. allwinner,data = <0xffffffff>;
  1756. };
  1757.  
  1758. twi1@1 {
  1759. linux,phandle = <0xe6>;
  1760. phandle = <0xe6>;
  1761. allwinner,pins = "PH5\0PH6";
  1762. allwinner,function = "twi1";
  1763. allwinner,pname = "twi1_scl\0twi1_sda";
  1764. allwinner,muxsel = <0x07>;
  1765. allwinner,pull = <0xffffffff>;
  1766. allwinner,drive = <0xffffffff>;
  1767. allwinner,data = <0xffffffff>;
  1768. };
  1769.  
  1770. twi2@0 {
  1771. linux,phandle = <0xe7>;
  1772. phandle = <0xe7>;
  1773. allwinner,pins = "PD23\0PD24";
  1774. allwinner,function = "twi2";
  1775. allwinner,pname = "twi2_scl\0twi2_sda";
  1776. allwinner,muxsel = <0x02>;
  1777. allwinner,pull = <0xffffffff>;
  1778. allwinner,drive = <0xffffffff>;
  1779. allwinner,data = <0xffffffff>;
  1780. };
  1781.  
  1782. twi2@1 {
  1783. linux,phandle = <0xe8>;
  1784. phandle = <0xe8>;
  1785. allwinner,pins = "PD23\0PD24";
  1786. allwinner,function = "twi2";
  1787. allwinner,pname = "twi2_scl\0twi2_sda";
  1788. allwinner,muxsel = <0x07>;
  1789. allwinner,pull = <0xffffffff>;
  1790. allwinner,drive = <0xffffffff>;
  1791. allwinner,data = <0xffffffff>;
  1792. };
  1793.  
  1794. twi3@0 {
  1795. linux,phandle = <0xe9>;
  1796. phandle = <0xe9>;
  1797. allwinner,pins = "PB17\0PB18";
  1798. allwinner,function = "twi3";
  1799. allwinner,pname = "twi3_scl\0twi3_sda";
  1800. allwinner,muxsel = <0x02>;
  1801. allwinner,pull = <0xffffffff>;
  1802. allwinner,drive = <0xffffffff>;
  1803. allwinner,data = <0xffffffff>;
  1804. };
  1805.  
  1806. uart0@0 {
  1807. linux,phandle = <0xea>;
  1808. phandle = <0xea>;
  1809. allwinner,pins = "PH0\0PH1";
  1810. allwinner,function = "uart0";
  1811. allwinner,pname = "uart0_tx\0uart0_rx";
  1812. allwinner,muxsel = <0x02>;
  1813. allwinner,pull = <0x01>;
  1814. allwinner,drive = <0xffffffff>;
  1815. allwinner,data = <0xffffffff>;
  1816. };
  1817.  
  1818. uart0@1 {
  1819. linux,phandle = <0xeb>;
  1820. phandle = <0xeb>;
  1821. allwinner,pins = "PH0\0PH1";
  1822. allwinner,function = "uart0";
  1823. allwinner,pname = "uart0_tx\0uart0_rx";
  1824. allwinner,muxsel = <0x07>;
  1825. allwinner,pull = <0x01>;
  1826. allwinner,drive = <0xffffffff>;
  1827. allwinner,data = <0xffffffff>;
  1828. };
  1829.  
  1830. uart1@0 {
  1831. linux,phandle = <0xec>;
  1832. phandle = <0xec>;
  1833. allwinner,pins = "PG6\0PG7\0PG8\0PG9";
  1834. allwinner,function = "uart1";
  1835. allwinner,pname = "uart1_tx\0uart1_rx\0uart1_rts\0uart1_cts";
  1836. allwinner,muxsel = <0x02>;
  1837. allwinner,pull = <0x01>;
  1838. allwinner,drive = <0xffffffff>;
  1839. allwinner,data = <0xffffffff>;
  1840. };
  1841.  
  1842. uart1@1 {
  1843. linux,phandle = <0xed>;
  1844. phandle = <0xed>;
  1845. allwinner,pins = "PG6\0PG7\0PG8\0PG9";
  1846. allwinner,function = "uart1";
  1847. allwinner,pname = "uart1_tx\0uart1_rx\0uart1_rts\0uart1_cts";
  1848. allwinner,muxsel = <0x07>;
  1849. allwinner,pull = <0x01>;
  1850. allwinner,drive = <0xffffffff>;
  1851. allwinner,data = <0xffffffff>;
  1852. };
  1853.  
  1854. uart2@0 {
  1855. linux,phandle = <0xee>;
  1856. phandle = <0xee>;
  1857. allwinner,pins = "PD19\0PD20\0PD21\0PD22";
  1858. allwinner,function = "uart2";
  1859. allwinner,pname = "uart2_tx\0uart2_rx\0uart2_rts\0uart2_cts";
  1860. allwinner,muxsel = <0x04>;
  1861. allwinner,pull = <0x01>;
  1862. allwinner,drive = <0xffffffff>;
  1863. allwinner,data = <0xffffffff>;
  1864. };
  1865.  
  1866. uart2@1 {
  1867. linux,phandle = <0xef>;
  1868. phandle = <0xef>;
  1869. allwinner,pins = "PD19\0PD20\0PD21\0PD22";
  1870. allwinner,function = "uart2";
  1871. allwinner,pname = "uart2_tx\0uart2_rx\0uart2_rts\0uart2_cts";
  1872. allwinner,muxsel = <0x07>;
  1873. allwinner,pull = <0x01>;
  1874. allwinner,drive = <0xffffffff>;
  1875. allwinner,data = <0xffffffff>;
  1876. };
  1877.  
  1878. uart3@0 {
  1879. linux,phandle = <0xf0>;
  1880. phandle = <0xf0>;
  1881. allwinner,pins = "PD23\0PD24\0PD25\0PD26";
  1882. allwinner,function = "uart3";
  1883. allwinner,pname = "uart3_tx\0uart3_rx\0uart3_rts\0uart3_cts";
  1884. allwinner,muxsel = <0x04>;
  1885. allwinner,pull = <0x01>;
  1886. allwinner,drive = <0xffffffff>;
  1887. allwinner,data = <0xffffffff>;
  1888. };
  1889.  
  1890. uart3@1 {
  1891. linux,phandle = <0xf1>;
  1892. phandle = <0xf1>;
  1893. allwinner,pins = "PD23\0PD24\0PD25\0PD26";
  1894. allwinner,function = "uart3";
  1895. allwinner,pname = "uart3_tx\0uart3_rx\0uart3_rts\0uart3_cts";
  1896. allwinner,muxsel = <0x07>;
  1897. allwinner,pull = <0x01>;
  1898. allwinner,drive = <0xffffffff>;
  1899. allwinner,data = <0xffffffff>;
  1900. };
  1901.  
  1902. spi0@0 {
  1903. linux,phandle = <0xf2>;
  1904. phandle = <0xf2>;
  1905. allwinner,pins = "PC5";
  1906. allwinner,function = "spi0";
  1907. allwinner,pname = "spi0_cs0";
  1908. allwinner,muxsel = <0x04>;
  1909. allwinner,pull = <0x01>;
  1910. allwinner,drive = <0xffffffff>;
  1911. allwinner,data = <0xffffffff>;
  1912. };
  1913.  
  1914. spi0@1 {
  1915. linux,phandle = <0xf3>;
  1916. phandle = <0xf3>;
  1917. allwinner,pins = "PC0\0PC2\0PC3";
  1918. allwinner,function = "spi0";
  1919. allwinner,pname = "spi0_sclk\0spi0_mosi\0spi0_miso";
  1920. allwinner,muxsel = <0x04>;
  1921. allwinner,pull = <0xffffffff>;
  1922. allwinner,drive = <0xffffffff>;
  1923. allwinner,data = <0xffffffff>;
  1924. };
  1925.  
  1926. spi0@2 {
  1927. linux,phandle = <0xf4>;
  1928. phandle = <0xf4>;
  1929. allwinner,pins = "PC5";
  1930. allwinner,function = "spi0";
  1931. allwinner,pname = "spi0_cs0";
  1932. allwinner,muxsel = <0x07>;
  1933. allwinner,pull = <0x01>;
  1934. allwinner,drive = <0xffffffff>;
  1935. allwinner,data = <0xffffffff>;
  1936. };
  1937.  
  1938. spi0@3 {
  1939. linux,phandle = <0xf5>;
  1940. phandle = <0xf5>;
  1941. allwinner,pins = "PC0\0PC2\0PC3";
  1942. allwinner,function = "spi0";
  1943. allwinner,pname = "spi0_sclk\0spi0_mosi\0spi0_miso";
  1944. allwinner,muxsel = <0x07>;
  1945. allwinner,pull = <0xffffffff>;
  1946. allwinner,drive = <0xffffffff>;
  1947. allwinner,data = <0xffffffff>;
  1948. };
  1949.  
  1950. spi1@0 {
  1951. linux,phandle = <0xf6>;
  1952. phandle = <0xf6>;
  1953. allwinner,pins = "PH3";
  1954. allwinner,function = "spi1";
  1955. allwinner,pname = "spi1_cs0";
  1956. allwinner,muxsel = <0x02>;
  1957. allwinner,pull = <0x01>;
  1958. allwinner,drive = <0xffffffff>;
  1959. allwinner,data = <0xffffffff>;
  1960. };
  1961.  
  1962. spi1@1 {
  1963. linux,phandle = <0xf7>;
  1964. phandle = <0xf7>;
  1965. allwinner,pins = "PH4\0PH5\0PH6";
  1966. allwinner,function = "spi1";
  1967. allwinner,pname = "spi1_sclk\0spi1_mosi\0spi1_miso";
  1968. allwinner,muxsel = <0x02>;
  1969. allwinner,pull = <0xffffffff>;
  1970. allwinner,drive = <0xffffffff>;
  1971. allwinner,data = <0xffffffff>;
  1972. };
  1973.  
  1974. spi1@2 {
  1975. linux,phandle = <0xf8>;
  1976. phandle = <0xf8>;
  1977. allwinner,pins = "PH3";
  1978. allwinner,function = "spi1";
  1979. allwinner,pname = "spi1_cs0";
  1980. allwinner,muxsel = <0x07>;
  1981. allwinner,pull = <0x01>;
  1982. allwinner,drive = <0xffffffff>;
  1983. allwinner,data = <0xffffffff>;
  1984. };
  1985.  
  1986. spi1@3 {
  1987. linux,phandle = <0xf9>;
  1988. phandle = <0xf9>;
  1989. allwinner,pins = "PH4\0PH5\0PH6";
  1990. allwinner,function = "spi1";
  1991. allwinner,pname = "spi1_sclk\0spi1_mosi\0spi1_miso";
  1992. allwinner,muxsel = <0x07>;
  1993. allwinner,pull = <0xffffffff>;
  1994. allwinner,drive = <0xffffffff>;
  1995. allwinner,data = <0xffffffff>;
  1996. };
  1997.  
  1998. nand0@0 {
  1999. linux,phandle = <0xfb>;
  2000. phandle = <0xfb>;
  2001. allwinner,pins = "PC0\0PC1\0PC2\0PC4\0PC6\0PC7\0PC8\0PC9\0PC10\0PC11\0PC12\0PC13\0PC14";
  2002. allwinner,function = "nand0";
  2003. allwinner,pname = "nand0_we\0nand0_ale\0nand0_cle\0nand0_nre\0nand0_d0\0nand0_d1\0nand0_d2\0nand0_d3\0nand0_d4\0nand0_d5\0nand0_d6\0nand0_d7\0nand0_ndqs";
  2004. allwinner,muxsel = <0x02>;
  2005. allwinner,pull = <0x00>;
  2006. allwinner,drive = <0x01>;
  2007. allwinner,data = <0xffffffff>;
  2008. };
  2009.  
  2010. nand0@1 {
  2011. linux,phandle = <0xfc>;
  2012. phandle = <0xfc>;
  2013. allwinner,pins = "PC15\0PC3\0PC5\0PC16";
  2014. allwinner,function = "nand0";
  2015. allwinner,pname = "nand0_ce1\0nand0_ce0\0nand0_rb0\0nand0_rb1";
  2016. allwinner,muxsel = <0x02>;
  2017. allwinner,pull = <0x01>;
  2018. allwinner,drive = <0x01>;
  2019. allwinner,data = <0xffffffff>;
  2020. };
  2021.  
  2022. lcd0@0 {
  2023. linux,phandle = <0xfd>;
  2024. phandle = <0xfd>;
  2025. allwinner,pins = "PD0\0PD1\0PD2\0PD3\0PD4\0PD5\0PD6\0PD7\0PD8\0PD9\0PD10\0PD11\0PD12\0PD13\0PD14\0PD15\0PD16\0PD17\0PD18\0PD19\0PD20\0PD21";
  2026. allwinner,function = "lcd0";
  2027. allwinner,pname = "lcdd0\0lcdd1\0lcdd2\0lcdd3\0lcdd4\0lcdd5\0lcdd6\0lcdd7\0lcdd8\0lcdd9\0lcdd10\0lcdd11\0lcdd12\0lcdd13\0lcdd14\0lcdd15\0lcdd16\0lcdd17\0lcdd18\0lcdd19\0lcdd20\0lcdd21";
  2028. allwinner,muxsel = <0x02>;
  2029. allwinner,pull = <0x00>;
  2030. allwinner,drive = <0xffffffff>;
  2031. allwinner,data = <0xffffffff>;
  2032. };
  2033.  
  2034. lcd0@1 {
  2035. linux,phandle = <0xfe>;
  2036. phandle = <0xfe>;
  2037. allwinner,pins = "PD0\0PD1\0PD2\0PD3\0PD4\0PD5\0PD6\0PD7\0PD8\0PD9\0PD10\0PD11\0PD12\0PD13\0PD14\0PD15\0PD16\0PD17\0PD18\0PD19\0PD20\0PD21";
  2038. allwinner,function = "lcd0";
  2039. allwinner,pname = "lcdd0\0lcdd1\0lcdd2\0lcdd3\0lcdd4\0lcdd5\0lcdd6\0lcdd7\0lcdd8\0lcdd9\0lcdd10\0lcdd11\0lcdd12\0lcdd13\0lcdd14\0lcdd15\0lcdd16\0lcdd17\0lcdd18\0lcdd19\0lcdd20\0lcdd21";
  2040. allwinner,muxsel = <0x07>;
  2041. allwinner,pull = <0x00>;
  2042. allwinner,drive = <0xffffffff>;
  2043. allwinner,data = <0xffffffff>;
  2044. };
  2045.  
  2046. hdmi@0 {
  2047. linux,phandle = <0xff>;
  2048. phandle = <0xff>;
  2049. allwinner,pins = "PH8\0PH9\0PH10";
  2050. allwinner,function = "hdmi";
  2051. allwinner,pname = "ddc_scl\0ddc_sda\0cec_io";
  2052. allwinner,muxsel = <0x02>;
  2053. allwinner,pull = <0xffffffff>;
  2054. allwinner,drive = <0x01>;
  2055. allwinner,data = <0xffffffff>;
  2056. };
  2057.  
  2058. ac200@0 {
  2059. linux,phandle = <0x100>;
  2060. phandle = <0x100>;
  2061. allwinner,pins = "PB0\0PB1\0PB2\0PB3\0PB4\0PB5\0PB6\0PB7\0PB8\0PB9\0PB10\0PB11";
  2062. allwinner,function = "ac200";
  2063. allwinner,pname = "ccir_clk\0ccir_de\0ccir_hs\0ccir_vs\0ccir_do0\0ccir_do1\0ccir_do2\0ccir_do3\0ccir_do4\0ccir_do5\0ccir_do6\0ccir_do7";
  2064. allwinner,muxsel = <0x02>;
  2065. allwinner,pull = <0x00>;
  2066. allwinner,drive = <0xffffffff>;
  2067. allwinner,data = <0xffffffff>;
  2068. };
  2069.  
  2070. ac200@1 {
  2071. linux,phandle = <0x101>;
  2072. phandle = <0x101>;
  2073. allwinner,pins = "PB1\0PB2\0PB3\0PB4\0PB5\0PB6\0PB7\0PB8\0PB9\0PB10\0PB11";
  2074. allwinner,function = "ac200";
  2075. allwinner,pname = "ccir_de\0ccir_hs\0ccir_vs\0ccir_do0\0ccir_do1\0ccir_do2\0ccir_do3\0ccir_do4\0ccir_do5\0ccir_do6\0ccir_do7";
  2076. allwinner,muxsel = <0x07>;
  2077. allwinner,pull = <0x00>;
  2078. allwinner,drive = <0xffffffff>;
  2079. allwinner,data = <0xffffffff>;
  2080. };
  2081.  
  2082. pwm0@0 {
  2083. linux,phandle = <0x102>;
  2084. phandle = <0x102>;
  2085. allwinner,pins = "PD22";
  2086. allwinner,function = "pwm0";
  2087. allwinner,pname = "pwm_positive";
  2088. allwinner,muxsel = <0x02>;
  2089. allwinner,pull = <0x00>;
  2090. allwinner,drive = <0xffffffff>;
  2091. allwinner,data = <0xffffffff>;
  2092. };
  2093.  
  2094. pwm0@1 {
  2095. linux,phandle = <0x103>;
  2096. phandle = <0x103>;
  2097. allwinner,pins = "PD22";
  2098. allwinner,function = "pwm0";
  2099. allwinner,pname = "pwm_positive";
  2100. allwinner,muxsel = <0x07>;
  2101. allwinner,pull = <0x00>;
  2102. allwinner,drive = <0xffffffff>;
  2103. allwinner,data = <0xffffffff>;
  2104. };
  2105.  
  2106. pwm1@0 {
  2107. linux,phandle = <0x104>;
  2108. phandle = <0x104>;
  2109. allwinner,pins = "PB19";
  2110. allwinner,function = "pwm1";
  2111. allwinner,pname = "pwm_positive";
  2112. allwinner,muxsel = <0x02>;
  2113. allwinner,pull = <0x00>;
  2114. allwinner,drive = <0xffffffff>;
  2115. allwinner,data = <0xffffffff>;
  2116. };
  2117.  
  2118. pwm1@1 {
  2119. linux,phandle = <0x105>;
  2120. phandle = <0x105>;
  2121. allwinner,pins = "PB19";
  2122. allwinner,function = "pwm1";
  2123. allwinner,pname = "pwm_positive";
  2124. allwinner,muxsel = <0x07>;
  2125. allwinner,pull = <0x00>;
  2126. allwinner,drive = <0xffffffff>;
  2127. allwinner,data = <0xffffffff>;
  2128. };
  2129.  
  2130. csi0@0 {
  2131. linux,phandle = <0x108>;
  2132. phandle = <0x108>;
  2133. allwinner,pins = "PD0\0PD2\0PD3\0PD4\0PD5\0PD6\0PD7\0PD8\0PD9\0PD10\0PD11\0PD12\0PD13";
  2134. allwinner,function = "csi0";
  2135. allwinner,pname = "csi0_pck\0csi0_hsync\0csi0_vsync\0csi0_d0\0csi0_d1\0csi0_d2\0csi0_d3\0csi0_d4\0csi0_d5\0csi0_d6\0csi0_d7\0csi0_sck\0csi0_sda";
  2136. allwinner,muxsel = <0x04>;
  2137. allwinner,pull = <0xffffffff>;
  2138. allwinner,drive = <0xffffffff>;
  2139. allwinner,data = <0xffffffff>;
  2140. };
  2141.  
  2142. csi0@2 {
  2143. linux,phandle = <0x109>;
  2144. phandle = <0x109>;
  2145. allwinner,pins = "PD1";
  2146. allwinner,function = "csi0";
  2147. allwinner,pname = "csi0_mck";
  2148. allwinner,muxsel = <0x04>;
  2149. allwinner,pull = <0x00>;
  2150. allwinner,drive = <0x01>;
  2151. allwinner,data = <0x00>;
  2152. };
  2153.  
  2154. sdc0@0 {
  2155. linux,phandle = <0x10a>;
  2156. phandle = <0x10a>;
  2157. allwinner,pins = "PF0\0PF1\0PF2\0PF3\0PF4\0PF5";
  2158. allwinner,function = "sdc0";
  2159. allwinner,pname = "sdc0_d1\0sdc0_d0\0sdc0_clk\0sdc0_cmd\0sdc0_d3\0sdc0_d2";
  2160. allwinner,muxsel = <0x02>;
  2161. allwinner,pull = <0x01>;
  2162. allwinner,drive = <0x02>;
  2163. allwinner,data = <0xffffffff>;
  2164. };
  2165.  
  2166. sdc1@0 {
  2167. linux,phandle = <0x10b>;
  2168. phandle = <0x10b>;
  2169. allwinner,pins = "PG0\0PG1\0PG2\0PG3\0PG4\0PG5";
  2170. allwinner,function = "sdc1";
  2171. allwinner,pname = "sdc1_clk\0sdc1_cmd\0sdc1_d0\0sdc1_d1\0sdc1_d2\0sdc1_d3";
  2172. allwinner,muxsel = <0x02>;
  2173. allwinner,pull = <0x01>;
  2174. allwinner,drive = <0x03>;
  2175. allwinner,data = <0xffffffff>;
  2176. };
  2177.  
  2178. sdc2@0 {
  2179. linux,phandle = <0x10c>;
  2180. phandle = <0x10c>;
  2181. allwinner,pins = "PC1\0PC4\0PC5\0PC6\0PC7\0PC8\0PC9\0PC10\0PC11\0PC12\0PC13\0PC14";
  2182. allwinner,function = "sdc2";
  2183. allwinner,pname = "sdc2_ds\0sdc2_clk\0sdc2_cmd\0sdc2_d0\0sdc2_d1\0sdc2_d2\0sdc2_d3\0sdc2_d4\0sdc2_d5\0sdc2_d6\0sdc2_d7\0sdc2_emmc_rst";
  2184. allwinner,muxsel = <0x03>;
  2185. allwinner,pull = <0x01>;
  2186. allwinner,drive = <0x03>;
  2187. allwinner,data = <0xffffffff>;
  2188. };
  2189.  
  2190. Vdevice@0 {
  2191. linux,phandle = <0x110>;
  2192. phandle = <0x110>;
  2193. allwinner,pins = "PH9\0PH10";
  2194. allwinner,function = "Vdevice";
  2195. allwinner,pname = "Vdevice_0\0Vdevice_1";
  2196. allwinner,muxsel = <0x05>;
  2197. allwinner,pull = <0x01>;
  2198. allwinner,drive = <0x02>;
  2199. allwinner,data = <0xffffffff>;
  2200. };
  2201. };
  2202.  
  2203. dma-controller@03002000 {
  2204. compatible = "allwinner,sun50i-dma";
  2205. reg = <0x00 0x3002000 0x00 0x1000>;
  2206. interrupts = <0x00 0x2b 0x04>;
  2207. clocks = <0x0c>;
  2208. #dma-cells = <0x01>;
  2209. };
  2210.  
  2211. mbus-controller@04002000 {
  2212. compatible = "allwinner,sun50i-mbus";
  2213. reg = <0x00 0x4002000 0x00 0x1000>;
  2214. #mbus-cells = <0x01>;
  2215. };
  2216.  
  2217. arisc {
  2218. compatible = "allwinner,sunxi-arisc";
  2219. #address-cells = <0x02>;
  2220. #size-cells = <0x02>;
  2221. clocks = <0x0d 0x0e 0x07 0x02>;
  2222. clock-names = "losc\0iosc\0hosc\0pll_periph0";
  2223. powchk_used = <0x00>;
  2224. power_reg = <0x2309621>;
  2225. system_power = <0x32>;
  2226. };
  2227.  
  2228. arisc_space {
  2229. compatible = "allwinner,arisc_space";
  2230. space1 = <0x48040000 0x00 0x14000>;
  2231. space2 = <0x48100000 0x18000 0x4000>;
  2232. space3 = <0x48104000 0x00 0x1000>;
  2233. space4 = <0x48105000 0x00 0x1000>;
  2234. };
  2235.  
  2236. standby_space {
  2237. compatible = "allwinner,standby_space";
  2238. space1 = <0x40020000 0x00 0x800>;
  2239. };
  2240.  
  2241. msgbox@03003000 {
  2242. compatible = "allwinner,msgbox";
  2243. clocks = <0x0f>;
  2244. clock-names = "clk_msgbox";
  2245. reg = <0x00 0x3003000 0x00 0x1000>;
  2246. interrupts = <0x00 0x27 0x01>;
  2247. status = "okay";
  2248. };
  2249.  
  2250. hwspinlock@3004000 {
  2251. compatible = "allwinner,sunxi-hwspinlock";
  2252. clocks = <0x10 0x11>;
  2253. clock-names = "clk_hwspinlock_rst\0clk_hwspinlock_bus";
  2254. reg = <0x00 0x3004000 0x00 0x1000>;
  2255. num-locks = <0x08>;
  2256. status = "okay";
  2257. };
  2258.  
  2259. s_cir@07040000 {
  2260. compatible = "allwinner,s_cir";
  2261. reg = <0x00 0x7040000 0x00 0x400>;
  2262. interrupts = <0x00 0x6d 0x04>;
  2263. pinctrl-names = "default";
  2264. pinctrl-0 = <0x12>;
  2265. clocks = <0x07 0x13>;
  2266. supply = [00];
  2267. supply_vol = [00];
  2268. status = "okay";
  2269. device_type = "s_cir0";
  2270. ir_protocol_used = <0x00>;
  2271. ir_power_key_code0 = <0x40>;
  2272. ir_addr_code0 = <0xfe01>;
  2273. ir_power_key_code1 = <0x00>;
  2274. ir_addr_code1 = <0x1dcc>;
  2275. ir_power_key_code2 = <0x40>;
  2276. ir_addr_code2 = <0xff00>;
  2277. ir_power_key_code3 = <0x1c>;
  2278. ir_addr_code3 = <0xdf00>;
  2279. ir_power_key_code4 = <0x4d>;
  2280. ir_addr_code4 = <0x4040>;
  2281. ir_power_key_code5 = <0x03>;
  2282. ir_addr_code5 = <0xef>;
  2283. rc5_ir_power_key_code0 = <0x01>;
  2284. rc5_ir_addr_code0 = <0x04>;
  2285. };
  2286.  
  2287. s_uart@7080000 {
  2288. compatible = "allwinner,s_uart";
  2289. reg = <0x00 0x7080000 0x00 0xd0>;
  2290. interrupts = <0x00 0x6a 0x04>;
  2291. pinctrl-names = "default";
  2292. status = "disabled";
  2293. device_type = "s_uart0";
  2294. pinctrl-0 = <0x10d>;
  2295. };
  2296.  
  2297. s_twi@1f03400 {
  2298. compatible = "allwinner,s_twi";
  2299. reg = <0x00 0x1f02400 0x00 0x20>;
  2300. interrupts = <0x00 0x2c 0x04>;
  2301. pinctrl-names = "default";
  2302. pinctrl-0 = <0x15>;
  2303. status = "okay";
  2304. };
  2305.  
  2306. s_jtag0 {
  2307. compatible = "allwinner,s_jtag";
  2308. pinctrl-names = "default";
  2309. status = "disabled";
  2310. device_type = "s_jtag0";
  2311. pinctrl-0 = <0x10f>;
  2312. };
  2313.  
  2314. box_start_os0 {
  2315. compatible = "allwinner,box_start_os";
  2316. start_type = <0x01>;
  2317. irkey_used = <0x01>;
  2318. pmukey_used = <0x00>;
  2319. pmukey_num = <0x00>;
  2320. led_power = <0x00>;
  2321. led_state = <0x00>;
  2322. status = "okay";
  2323. device_type = "box_start_os";
  2324. };
  2325.  
  2326. timer@03009000 {
  2327. compatible = "allwinner,sunxi-timer";
  2328. device_type = "timer";
  2329. reg = <0x00 0x3009000 0x00 0x400>;
  2330. interrupts = <0x00 0x30 0x04>;
  2331. clock-frequency = <0x16e3600>;
  2332. timer-prescale = <0x10>;
  2333. };
  2334.  
  2335. rtc@07000000 {
  2336. compatible = "allwinner,sun50iw6-rtc";
  2337. device_type = "rtc";
  2338. reg = <0x00 0x7000000 0x00 0x200>;
  2339. interrupts = <0x00 0x65 0x04>;
  2340. gpr_offset = <0x100>;
  2341. gpr_len = <0x08>;
  2342. };
  2343.  
  2344. watchdog@030090a0 {
  2345. compatible = "allwinner,sun50i-wdt";
  2346. reg = <0x00 0x30090a0 0x00 0x20>;
  2347. interrupts = <0x00 0x32 0x04>;
  2348. };
  2349.  
  2350. ve@01c0e000 {
  2351. compatible = "allwinner,sunxi-cedar-ve";
  2352. reg = <0x00 0x1c0e000 0x00 0x1000 0x00 0x3000000 0x00 0x10 0x00 0x3001000 0x00 0x1000>;
  2353. interrupts = <0x00 0x59 0x04>;
  2354. clocks = <0x17 0x18>;
  2355. iommus = <0x19 0x03 0x01>;
  2356. };
  2357.  
  2358. vp9@01c00000 {
  2359. compatible = "allwinner,sunxi-google-vp9";
  2360. reg = <0x00 0x1c00000 0x00 0x1000 0x00 0x3000000 0x00 0x10 0x00 0x3001000 0x00 0x1000>;
  2361. interrupts = <0x00 0x5a 0x04>;
  2362. clocks = <0x17 0x1a>;
  2363. #clocks = <0x1b 0x1a>;
  2364. iommus = <0x19 0x05 0x01>;
  2365. };
  2366.  
  2367. uart@05000000 {
  2368. compatible = "allwinner,sun50i-uart";
  2369. device_type = "uart0";
  2370. reg = <0x00 0x5000000 0x00 0x400>;
  2371. interrupts = <0x00 0x00 0x04>;
  2372. clocks = <0x1c>;
  2373. pinctrl-names = "default\0sleep";
  2374. uart0_port = <0x00>;
  2375. uart0_type = <0x02>;
  2376. status = "okay";
  2377. pinctrl-0 = <0xea>;
  2378. pinctrl-1 = <0xeb>;
  2379. };
  2380.  
  2381. uart@05000400 {
  2382. compatible = "allwinner,sun50i-uart";
  2383. device_type = "uart1";
  2384. reg = <0x00 0x5000400 0x00 0x400>;
  2385. interrupts = <0x00 0x01 0x04>;
  2386. clocks = <0x1f>;
  2387. pinctrl-names = "default\0sleep";
  2388. uart1_port = <0x01>;
  2389. uart1_type = <0x04>;
  2390. status = "okay";
  2391. pinctrl-0 = <0xec>;
  2392. uart1_bt = <0x01>;
  2393. pinctrl-1 = <0xed>;
  2394. };
  2395.  
  2396. uart@05000800 {
  2397. compatible = "allwinner,sun50i-uart";
  2398. device_type = "uart2";
  2399. reg = <0x00 0x5000800 0x00 0x400>;
  2400. interrupts = <0x00 0x02 0x04>;
  2401. clocks = <0x22>;
  2402. pinctrl-names = "default\0sleep";
  2403. uart2_port = <0x02>;
  2404. uart2_type = <0x04>;
  2405. status = "disabled";
  2406. pinctrl-0 = <0xee>;
  2407. pinctrl-1 = <0xef>;
  2408. };
  2409.  
  2410. uart@05000c00 {
  2411. compatible = "allwinner,sun50i-uart";
  2412. device_type = "uart3";
  2413. reg = <0x00 0x5000c00 0x00 0x400>;
  2414. interrupts = <0x00 0x03 0x04>;
  2415. clocks = <0x25>;
  2416. pinctrl-names = "default\0sleep";
  2417. uart3_port = <0x03>;
  2418. uart3_type = <0x04>;
  2419. status = "disabled";
  2420. pinctrl-0 = <0xf0>;
  2421. pinctrl-1 = <0xf1>;
  2422. };
  2423.  
  2424. twi@0x05002000 {
  2425. #address-cells = <0x01>;
  2426. #size-cells = <0x00>;
  2427. compatible = "allwinner,sun50i-twi";
  2428. device_type = "twi0";
  2429. reg = <0x00 0x5002000 0x00 0x400>;
  2430. interrupts = <0x00 0x04 0x04>;
  2431. clocks = <0x28>;
  2432. clock-frequency = <0x61a80>;
  2433. pinctrl-names = "default\0sleep";
  2434. status = "disabled";
  2435. pinctrl-0 = <0xe3>;
  2436. pinctrl-1 = <0xe4>;
  2437. };
  2438.  
  2439. twi@0x05002400 {
  2440. #address-cells = <0x01>;
  2441. #size-cells = <0x00>;
  2442. compatible = "allwinner,sun50i-twi";
  2443. device_type = "twi1";
  2444. reg = <0x00 0x5002400 0x00 0x400>;
  2445. interrupts = <0x00 0x05 0x04>;
  2446. clocks = <0x2b>;
  2447. clock-frequency = <0x30d40>;
  2448. pinctrl-names = "default\0sleep";
  2449. status = "disabled";
  2450. pinctrl-0 = <0xe5>;
  2451. pinctrl-1 = <0xe6>;
  2452. };
  2453.  
  2454. twi@0x05002800 {
  2455. #address-cells = <0x01>;
  2456. #size-cells = <0x00>;
  2457. compatible = "allwinner,sun50i-twi";
  2458. device_type = "twi2";
  2459. reg = <0x00 0x5002800 0x00 0x400>;
  2460. interrupts = <0x00 0x06 0x04>;
  2461. clocks = <0x2e>;
  2462. clock-frequency = <0x30d40>;
  2463. pinctrl-names = "default\0sleep";
  2464. status = "disabled";
  2465. pinctrl-0 = <0xe7>;
  2466. pinctrl-1 = <0xe8>;
  2467. };
  2468.  
  2469. twi@0x05002c00 {
  2470. #address-cells = <0x01>;
  2471. #size-cells = <0x00>;
  2472. compatible = "allwinner,sun50i-twi";
  2473. device_type = "twi3";
  2474. reg = <0x00 0x5002c00 0x00 0x400>;
  2475. interrupts = <0x00 0x07 0x04>;
  2476. clocks = <0x31>;
  2477. clock-frequency = <0x30d40>;
  2478. pinctrl-names = "default\0sleep";
  2479. pinctrl-1 = <0x33>;
  2480. status = "okay";
  2481. pinctrl-0 = <0xe9>;
  2482. };
  2483.  
  2484. usbc0@0 {
  2485. device_type = "usbc0";
  2486. compatible = "allwinner,sunxi-otg-manager";
  2487. usb_port_type = <0x01>;
  2488. usb_detect_type = <0x01>;
  2489. usb_host_init_state = <0x01>;
  2490. usb_regulator_io = "nocare";
  2491. usb_wakeup_suspend = <0x01>;
  2492. usb_luns = <0x03>;
  2493. usb_serial_unique = <0x00>;
  2494. usb_serial_number = "20080411";
  2495. rndis_wceis = <0x01>;
  2496. status = "okay";
  2497. usb_detect_mode = <0x00>;
  2498. usb_id_gpio;
  2499. usb_det_vbus_gpio;
  2500. usb_drv_vbus_gpio;
  2501. };
  2502.  
  2503. udc-controller@0x05100000 {
  2504. compatible = "allwinner,sunxi-udc";
  2505. reg = <0x00 0x5100000 0x00 0x1000 0x00 0x00 0x00 0x100>;
  2506. interrupts = <0x00 0x17 0x04>;
  2507. clocks = <0x34 0x35>;
  2508. status = "okay";
  2509. };
  2510.  
  2511. ehci0-controller@0x05101000 {
  2512. compatible = "allwinner,sunxi-ehci0";
  2513. reg = <0x00 0x5101000 0x00 0xfff 0x00 0x00 0x00 0x100 0x00 0x5100000 0x00 0x1000>;
  2514. interrupts = <0x00 0x18 0x04>;
  2515. clocks = <0x34 0x36>;
  2516. hci_ctrl_no = <0x00>;
  2517. status = "okay";
  2518. };
  2519.  
  2520. ohci0-controller@0x05101400 {
  2521. compatible = "allwinner,sunxi-ohci0";
  2522. reg = <0x00 0x5101000 0x00 0xfff 0x00 0x00 0x00 0x100 0x00 0x5100000 0x00 0x1000>;
  2523. interrupts = <0x00 0x19 0x04>;
  2524. clocks = <0x34 0x37 0x38 0x39 0x07 0x0d>;
  2525. hci_ctrl_no = <0x00>;
  2526. status = "okay";
  2527. };
  2528.  
  2529. usbc1@0 {
  2530. device_type = "usbc1";
  2531. usb_host_init_state = <0x01>;
  2532. usb_regulator_io = "nocare";
  2533. usb_wakeup_suspend = <0x01>;
  2534. status = "okay";
  2535. usb_drv_vbus_gpio = <0xdc 0x0b 0x05 0x01 0x00 0xffffffff 0x01>;
  2536. };
  2537.  
  2538. xhci-controller@0x05200000 {
  2539. compatible = "allwinner,sunxi-xhci";
  2540. reg = <0x00 0x5200000 0x00 0xfffff 0x00 0x00 0x00 0x100 0x00 0x5100000 0x00 0x1000>;
  2541. interrupts = <0x00 0x1a 0x04>;
  2542. clocks = <0x3a 0x3b>;
  2543. hci_ctrl_no = <0x01>;
  2544. status = "okay";
  2545. };
  2546.  
  2547. usbc2@0 {
  2548. device_type = "usbc2";
  2549. usb_host_init_state = <0x01>;
  2550. usb_regulator_io = "nocare";
  2551. usb_wakeup_suspend = <0x01>;
  2552. status = "disabled";
  2553. usb_drv_vbus_gpio;
  2554. };
  2555.  
  2556. ehci3-controller@0x05311000 {
  2557. compatible = "allwinner,sunxi-ehci3";
  2558. reg = <0x00 0x5311000 0x00 0xfff 0x00 0x00 0x00 0x100 0x00 0x5100000 0x00 0x1000>;
  2559. interrupts = <0x00 0x1c 0x04>;
  2560. clocks = <0x3c 0x3d 0x3e 0x3e 0x3f>;
  2561. hci_ctrl_no = <0x03>;
  2562. status = "okay";
  2563. };
  2564.  
  2565. ohci3-controller@0x05311400 {
  2566. compatible = "allwinner,sunxi-ohci3";
  2567. reg = <0x00 0x5311000 0x00 0xfff 0x00 0x00 0x00 0x100 0x00 0x5100000 0x00 0x1000>;
  2568. interrupts = <0x00 0x1d 0x04>;
  2569. clocks = <0x3c 0x40 0x41 0x39 0x07 0x0d>;
  2570. hci_ctrl_no = <0x03>;
  2571. status = "okay";
  2572. };
  2573.  
  2574. ac200_codec {
  2575. compatible = "allwinner,ac200_codec";
  2576. status = "okay";
  2577. device_type = "ac200_codec";
  2578. gpio-spk = <0xdc 0x0b 0x06 0x01 0x01 0xffffffff 0xffffffff>;
  2579. };
  2580.  
  2581. daudio@0x05090000 {
  2582. compatible = "allwinner,sunxi-daudio";
  2583. reg = <0x00 0x5090000 0x00 0x74>;
  2584. clocks = <0x04 0x42>;
  2585. pinctrl-names = "default\0sleep";
  2586. pinctrl-0 = <0x43>;
  2587. pinctrl-1 = <0x44>;
  2588. pcm_lrck_period = <0x20>;
  2589. slot_width_select = <0x20>;
  2590. daudio_master = <0x04>;
  2591. audio_format = <0x01>;
  2592. signal_inversion = <0x01>;
  2593. tdm_config = <0x01>;
  2594. frametype = <0x00>;
  2595. tdm_num = <0x00>;
  2596. mclk_div = <0x00>;
  2597. status = "disabled";
  2598. linux,phandle = <0x59>;
  2599. phandle = <0x59>;
  2600. device_type = "daudio0";
  2601. };
  2602.  
  2603. daudio@0x05091000 {
  2604. compatible = "allwinner,sunxi-tdmhdmi";
  2605. reg = <0x00 0x5091000 0x00 0x74>;
  2606. clocks = <0x04 0x45>;
  2607. status = "okay";
  2608. linux,phandle = <0x5b>;
  2609. phandle = <0x5b>;
  2610. device_type = "audiohdmi";
  2611. };
  2612.  
  2613. daudio@0x05092000 {
  2614. compatible = "allwinner,sunxi-daudio";
  2615. reg = <0x00 0x5092000 0x00 0x74>;
  2616. clocks = <0x04 0x46>;
  2617. pinctrl-names = "default\0sleep";
  2618. pinctrl-0 = <0x47>;
  2619. pinctrl-1 = <0x48>;
  2620. pcm_lrck_period = <0x40>;
  2621. slot_width_select = <0x20>;
  2622. daudio_master = <0x04>;
  2623. audio_format = <0x04>;
  2624. signal_inversion = <0x03>;
  2625. tdm_config = <0x01>;
  2626. frametype = <0x00>;
  2627. tdm_num = <0x02>;
  2628. mclk_div = <0x01>;
  2629. status = "okay";
  2630. linux,phandle = <0x5d>;
  2631. phandle = <0x5d>;
  2632. device_type = "daudio2";
  2633. };
  2634.  
  2635. daudio@0x0508f000 {
  2636. compatible = "allwinner,sunxi-daudio";
  2637. reg = <0x00 0x508f000 0x00 0x74>;
  2638. clocks = <0x04 0x49>;
  2639. pinctrl-names = "default\0sleep";
  2640. pinctrl-0 = <0x4a>;
  2641. pinctrl-1 = <0x4b>;
  2642. pcm_lrck_period = <0x20>;
  2643. slot_width_select = <0x20>;
  2644. daudio_master = <0x04>;
  2645. audio_format = <0x01>;
  2646. signal_inversion = <0x01>;
  2647. tdm_config = <0x01>;
  2648. frametype = <0x00>;
  2649. tdm_num = <0x03>;
  2650. mclk_div = <0x01>;
  2651. status = "okay";
  2652. linux,phandle = <0x5f>;
  2653. phandle = <0x5f>;
  2654. device_type = "daudio3";
  2655. };
  2656.  
  2657. spdif-controller@0x05093000 {
  2658. compatible = "allwinner,sunxi-spdif";
  2659. reg = <0x00 0x5093000 0x00 0x40>;
  2660. clocks = <0x04 0x4c>;
  2661. pinctrl-names = "default\0sleep";
  2662. pinctrl-0 = <0x4d>;
  2663. pinctrl-1 = <0x4e>;
  2664. status = "okay";
  2665. linux,phandle = <0x61>;
  2666. phandle = <0x61>;
  2667. device_type = "spdif";
  2668. };
  2669.  
  2670. dmic-controller@0x05095000 {
  2671. compatible = "allwinner,sunxi-dmic";
  2672. reg = <0x00 0x5095000 0x00 0x50>;
  2673. clocks = <0x04 0x4f>;
  2674. pinctrl-names = "default\0sleep";
  2675. pinctrl-0 = <0x50>;
  2676. pinctrl-1 = <0x51>;
  2677. status = "disabled";
  2678. linux,phandle = <0x62>;
  2679. phandle = <0x62>;
  2680. device_type = "dmic";
  2681. };
  2682.  
  2683. cpudai0-controller@0x05097000 {
  2684. compatible = "allwinner,sunxi-ahub-cpudai";
  2685. reg = <0x00 0x5097000 0x00 0xadf>;
  2686. id = <0x00>;
  2687. status = "okay";
  2688. linux,phandle = <0x63>;
  2689. phandle = <0x63>;
  2690. };
  2691.  
  2692. cpudai1-controller@0x05097000 {
  2693. compatible = "allwinner,sunxi-ahub-cpudai";
  2694. reg = <0x00 0x5097000 0x00 0xadf>;
  2695. id = <0x01>;
  2696. status = "okay";
  2697. linux,phandle = <0x64>;
  2698. phandle = <0x64>;
  2699. };
  2700.  
  2701. cpudai2-controller@0x05097000 {
  2702. compatible = "allwinner,sunxi-ahub-cpudai";
  2703. reg = <0x00 0x5097000 0x00 0xadf>;
  2704. id = <0x02>;
  2705. status = "okay";
  2706. linux,phandle = <0x65>;
  2707. phandle = <0x65>;
  2708. };
  2709.  
  2710. ahub_codec@0x05097000 {
  2711. compatible = "allwinner,sunxi-ahub";
  2712. reg = <0x00 0x5097000 0x00 0xadf>;
  2713. clocks = <0x04 0x52>;
  2714. status = "okay";
  2715. linux,phandle = <0x66>;
  2716. phandle = <0x66>;
  2717. };
  2718.  
  2719. ahub_daudio0@0x05097000 {
  2720. compatible = "allwinner,sunxi-ahub-daudio";
  2721. reg = <0x00 0x5097000 0x00 0xadf>;
  2722. clocks = <0x04 0x52>;
  2723. pinctrl-names = "default\0sleep";
  2724. pinctrl-0 = <0x53>;
  2725. pinctrl-1 = <0x54>;
  2726. pinconfig = <0x01>;
  2727. frametype = <0x00>;
  2728. pcm_lrck_period = <0x20>;
  2729. slot_width_select = <0x20>;
  2730. daudio_master = <0x04>;
  2731. audio_format = <0x01>;
  2732. signal_inversion = <0x01>;
  2733. tdm_config = <0x01>;
  2734. tdm_num = <0x00>;
  2735. mclk_div = <0x00>;
  2736. status = "disabled";
  2737. linux,phandle = <0x5a>;
  2738. phandle = <0x5a>;
  2739. device_type = "ahub_daudio0";
  2740. };
  2741.  
  2742. ahub_daudio1@0x05097000 {
  2743. compatible = "allwinner,sunxi-ahub-daudio";
  2744. reg = <0x00 0x5097000 0x00 0xadf>;
  2745. clocks = <0x04 0x52>;
  2746. pinconfig = <0x00>;
  2747. frametype = <0x00>;
  2748. pcm_lrck_period = <0x20>;
  2749. slot_width_select = <0x20>;
  2750. daudio_master = <0x04>;
  2751. audio_format = <0x01>;
  2752. signal_inversion = <0x01>;
  2753. tdm_config = <0x01>;
  2754. tdm_num = <0x01>;
  2755. mclk_div = <0x01>;
  2756. status = "okay";
  2757. linux,phandle = <0x5c>;
  2758. phandle = <0x5c>;
  2759. device_type = "ahub_daudio1";
  2760. };
  2761.  
  2762. ahub_daudio2@0x05097000 {
  2763. compatible = "allwinner,sunxi-ahub-daudio";
  2764. reg = <0x00 0x5097000 0x00 0xadf>;
  2765. clocks = <0x04 0x52>;
  2766. pinctrl-names = "default\0sleep";
  2767. pinctrl-0 = <0x55>;
  2768. pinctrl-1 = <0x56>;
  2769. pinconfig = <0x01>;
  2770. frametype = <0x00>;
  2771. pcm_lrck_period = <0x20>;
  2772. slot_width_select = <0x20>;
  2773. daudio_master = <0x04>;
  2774. audio_format = <0x01>;
  2775. signal_inversion = <0x01>;
  2776. tdm_config = <0x01>;
  2777. tdm_num = <0x02>;
  2778. mclk_div = <0x01>;
  2779. status = "okay";
  2780. linux,phandle = <0x5e>;
  2781. phandle = <0x5e>;
  2782. device_type = "ahub_daudio2";
  2783. };
  2784.  
  2785. ahub_daudio3@0x05097000 {
  2786. compatible = "allwinner,sunxi-ahub-daudio";
  2787. reg = <0x00 0x5097000 0x00 0xadf>;
  2788. clocks = <0x04 0x52>;
  2789. pinctrl-names = "default\0sleep";
  2790. pinctrl-0 = <0x57>;
  2791. pinctrl-1 = <0x58>;
  2792. pinconfig = <0x01>;
  2793. frametype = <0x00>;
  2794. pcm_lrck_period = <0x20>;
  2795. slot_width_select = <0x20>;
  2796. daudio_master = <0x04>;
  2797. audio_format = <0x01>;
  2798. signal_inversion = <0x01>;
  2799. tdm_config = <0x01>;
  2800. tdm_num = <0x03>;
  2801. mclk_div = <0x04>;
  2802. status = "okay";
  2803. linux,phandle = <0x60>;
  2804. phandle = <0x60>;
  2805. device_type = "ahub_daudio3";
  2806. };
  2807.  
  2808. sound@0 {
  2809. compatible = "allwinner,sunxi-daudio0-machine";
  2810. sunxi,daudio-controller = <0x59>;
  2811. sunxi,cpudai-controller = <0x5a>;
  2812. status = "disabled";
  2813. device_type = "snddaudio0";
  2814. };
  2815.  
  2816. sound@1 {
  2817. compatible = "allwinner,sunxi-hdmi-machine";
  2818. sunxi,hdmi-controller = <0x5b>;
  2819. sunxi,cpudai-controller = <0x5c>;
  2820. status = "okay";
  2821. device_type = "sndhdmi";
  2822. };
  2823.  
  2824. sound@2 {
  2825. compatible = "allwinner,sunxi-daudio2-machine";
  2826. sunxi,daudio-controller = <0x5d>;
  2827. sunxi,cpudai-controller = <0x5e>;
  2828. status = "okay";
  2829. device_type = "snddaudio2";
  2830. };
  2831.  
  2832. sound@3 {
  2833. compatible = "allwinner,sunxi-daudio3-machine";
  2834. sunxi,daudio-controller = <0x5f>;
  2835. sunxi,cpudai-controller = <0x60>;
  2836. sunxi,snddaudio-codec = "acx00-codec";
  2837. sunxi,snddaudio-codec-dai = "acx00-dai";
  2838. status = "okay";
  2839. device_type = "snddaudio3";
  2840. };
  2841.  
  2842. sound@4 {
  2843. compatible = "allwinner,sunxi-spdif-machine";
  2844. sunxi,spdif-controller = <0x61>;
  2845. status = "okay";
  2846. device_type = "sndspdif";
  2847. };
  2848.  
  2849. sound@5 {
  2850. compatible = "allwinner,sunxi-dmic-machine";
  2851. sunxi,dmic-controller = <0x62>;
  2852. status = "disabled";
  2853. device_type = "snddmic";
  2854. };
  2855.  
  2856. sound@6 {
  2857. compatible = "allwinner,sunxi-ahub-machine";
  2858. sunxi,cpudai-controller0 = <0x63>;
  2859. sunxi,cpudai-controller1 = <0x64>;
  2860. sunxi,cpudai-controller2 = <0x65>;
  2861. sunxi,audio-codec = <0x66>;
  2862. status = "okay";
  2863. device_type = "sndahub";
  2864. };
  2865.  
  2866. spi@05010000 {
  2867. #address-cells = <0x01>;
  2868. #size-cells = <0x00>;
  2869. compatible = "allwinner,sun50i-spi";
  2870. device_type = "spi0";
  2871. reg = <0x00 0x5010000 0x00 0x1000>;
  2872. interrupts = <0x00 0x0a 0x04>;
  2873. clocks = <0x02 0x67>;
  2874. clock-frequency = <0x5f5e100>;
  2875. pinctrl-names = "default\0sleep";
  2876. spi0_cs_number = <0x01>;
  2877. spi0_cs_bitmap = <0x01>;
  2878. status = "disabled";
  2879. pinctrl-0 = <0xf2 0xf3>;
  2880. pinctrl-1 = <0xf4 0xf5>;
  2881. };
  2882.  
  2883. spi@05011000 {
  2884. #address-cells = <0x01>;
  2885. #size-cells = <0x00>;
  2886. compatible = "allwinner,sun50i-spi";
  2887. device_type = "spi1";
  2888. reg = <0x00 0x5011000 0x00 0x1000>;
  2889. interrupts = <0x00 0x0b 0x04>;
  2890. clocks = <0x02 0x6b>;
  2891. clock-frequency = <0x5f5e100>;
  2892. pinctrl-names = "default\0sleep";
  2893. spi1_cs_number = <0x01>;
  2894. spi1_cs_bitmap = <0x01>;
  2895. status = "disabled";
  2896. pinctrl-0 = <0xf6 0xf7>;
  2897. pinctrl-1 = <0xf8 0xf9>;
  2898. };
  2899.  
  2900. pcie@0x05400000 {
  2901. #address-cells = <0x03>;
  2902. #size-cells = <0x02>;
  2903. compatible = "allwinner,sun50i-pcie";
  2904. reg = <0x00 0x5400000 0x00 0x2000 0x00 0x5410000 0x00 0x10000>;
  2905. reg-names = "dbi\0config";
  2906. device_type = "pci";
  2907. ranges = <0x800 0x00 0x5410000 0x00 0x5410000 0x00 0x10000 0x81000000 0x00 0x00 0x00 0x5e00000 0x00 0x10000 0x82000000 0x00 0x5500000 0x00 0x5500000 0x00 0x800000>;
  2908. num-lanes = <0x01>;
  2909. interrupts = <0x00 0x7f 0x04 0x00 0x7e 0x04>;
  2910. interrupt-names = "msi";
  2911. clocks = <0x6f 0x70 0x71 0x72 0x73 0x74>;
  2912. #interrupt-cells = <0x01>;
  2913. interrupt-map-mask = <0x00 0x00 0x00 0x00>;
  2914. interrupt-map = <0x00 0x00 0x00 0x01 0x01 0x00 0x7f 0x04>;
  2915. status = "disabled";
  2916. pcie_rest = <0x81 0x07 0x03 0x01 0xffffffff 0xffffffff 0xffffffff>;
  2917. pcie_power = <0xdc 0x0b 0x08 0x01 0xffffffff 0xffffffff 0xffffffff>;
  2918. pcie_reg = <0xdc 0x0c 0x03 0x01 0xffffffff 0xffffffff 0xffffffff>;
  2919. pcie_iodvdd = <0x708>;
  2920. pcie_speed_gen = <0x02>;
  2921. pcie_vdd = "vdd-pcie";
  2922. pcie_vdd_vol = <0xdbba0>;
  2923. pcie_vcc = "vcc-pcie";
  2924. pcie_vcc_vol = <0x1b7740>;
  2925. pcie_vcc_slot = "vcc-pcie-slot";
  2926. pcie_vcc_slot_vol = <0x325aa0>;
  2927. };
  2928.  
  2929. sdmmc@04022000 {
  2930. compatible = "allwinner,sunxi-mmc-v4p6x";
  2931. device_type = "sdc2";
  2932. reg = <0x00 0x4022000 0x00 0x1000>;
  2933. interrupts = <0x00 0x25 0x104>;
  2934. clocks = <0x07 0x75 0x76 0x77 0x78>;
  2935. clock-names = "osc24m\0pll_periph\0mmc\0ahb\0rst";
  2936. pinctrl-names = "default\0sleep";
  2937. pinctrl-1 = <0x7a>;
  2938. bus-width = <0x08>;
  2939. max-frequency = <0x8f0d180>;
  2940. sdc_tm4_sm0_freq0 = <0x00>;
  2941. sdc_tm4_sm0_freq1 = <0x00>;
  2942. sdc_tm4_sm1_freq0 = <0x00>;
  2943. sdc_tm4_sm1_freq1 = <0x00>;
  2944. sdc_tm4_sm2_freq0 = <0x00>;
  2945. sdc_tm4_sm2_freq1 = <0x00>;
  2946. sdc_tm4_sm3_freq0 = <0x5000000>;
  2947. sdc_tm4_sm3_freq1 = <0x405>;
  2948. sdc_tm4_sm4_freq0 = <0x50000>;
  2949. sdc_tm4_sm4_freq1 = <0x408>;
  2950. status = "okay";
  2951. non-removable;
  2952. pinctrl-0 = <0x10c>;
  2953. cd-gpios;
  2954. sunxi-power-save-mode;
  2955. sunxi-dis-signal-vol-sw;
  2956. mmc-ddr-1_8v;
  2957. mmc-hs200-1_8v;
  2958. mmc-hs400-1_8v;
  2959. vmmc = "vcc-emmcv";
  2960. vqmmc = "vcc-emmcvq18";
  2961. vdmmc = "none";
  2962. };
  2963.  
  2964. sdmmc@04020000 {
  2965. compatible = "allwinner,sunxi-mmc-v4p1x";
  2966. device_type = "sdc0";
  2967. reg = <0x00 0x4020000 0x00 0x1000>;
  2968. interrupts = <0x00 0x23 0x104>;
  2969. clocks = <0x07 0x75 0x7b 0x7c 0x7d>;
  2970. clock-names = "osc24m\0pll_periph\0mmc\0ahb\0rst";
  2971. pinctrl-names = "default\0sleep\0uart0";
  2972. pinctrl-1 = <0x7f>;
  2973. pinctrl-2 = <0x80>;
  2974. max-frequency = <0x2faf080>;
  2975. bus-width = <0x04>;
  2976. status = "okay";
  2977. pinctrl-0 = <0x10a>;
  2978. cd-gpios = <0x81 0x05 0x06 0x00 0x01 0x02 0xffffffff>;
  2979. sunxi-power-save-mode;
  2980. sunxi-dis-signal-vol-sw;
  2981. vmmc = "vcc-sdcv";
  2982. vqmmc = "vcc-sdcvq33";
  2983. vdmmc = "vcc-sdcvd";
  2984. ctl-spec-caps = <0x80>;
  2985. };
  2986.  
  2987. sdmmc@04021000 {
  2988. compatible = "allwinner,sunxi-mmc-v4p1x";
  2989. device_type = "sdc1";
  2990. reg = <0x00 0x4021000 0x00 0x1000>;
  2991. interrupts = <0x00 0x24 0x104>;
  2992. clocks = <0x07 0x75 0x82 0x83 0x84>;
  2993. clock-names = "osc24m\0pll_periph\0mmc\0ahb\0rst";
  2994. pinctrl-names = "default\0sleep";
  2995. pinctrl-1 = <0x86>;
  2996. max-frequency = <0x8f0d180>;
  2997. bus-width = <0x04>;
  2998. sunxi-dly-52M-ddr4 = <0x01 0x00 0x00 0x00 0x02>;
  2999. sunxi-dly-104M = <0x01 0x00 0x00 0x00 0x01>;
  3000. sunxi-dly-208M = <0x01 0x00 0x00 0x00 0x01>;
  3001. status = "okay";
  3002. pinctrl-0 = <0x10b>;
  3003. sd-uhs-sdr50;
  3004. sd-uhs-ddr50;
  3005. sd-uhs-sdr104;
  3006. cap-sdio-irq;
  3007. keep-power-in-suspend;
  3008. ignore-pm-notify;
  3009. };
  3010.  
  3011. disp@01000000 {
  3012. compatible = "allwinner,sunxi-disp";
  3013. reg = <0x00 0x1000000 0x00 0x1400000 0x00 0x6510000 0x00 0x100 0x00 0x6511000 0x00 0x800 0x00 0x6515000 0x00 0x800>;
  3014. interrupts = <0x00 0x41 0x104 0x00 0x42 0x104>;
  3015. clocks = <0x87 0x88 0x89 0x8a>;
  3016. boot_disp = <0x00>;
  3017. fb_base = <0x00>;
  3018. iommus = <0x19 0x00 0x00>;
  3019. status = "okay";
  3020. device_type = "disp";
  3021. disp_init_enable = <0x01>;
  3022. disp_mode = <0x00>;
  3023. screen0_output_type = <0x03>;
  3024. screen0_output_mode = <0x0a>;
  3025. screen0_output_format = <0x01>;
  3026. screen0_output_bits = <0x00>;
  3027. screen0_output_eotf = <0x04>;
  3028. screen0_output_cs = <0x101>;
  3029. screen0_output_dvi_hdmi = <0x02>;
  3030. screen0_output_range = <0x02>;
  3031. screen0_output_scan = <0x00>;
  3032. screen0_output_aspect_ratio = <0x08>;
  3033. screen1_output_type = <0x03>;
  3034. screen1_output_mode = <0x02>;
  3035. screen1_output_format = <0x01>;
  3036. screen1_output_bits = <0x00>;
  3037. screen1_output_eotf = <0x04>;
  3038. screen1_output_cs = <0x104>;
  3039. screen1_output_dvi_hdmi = <0x02>;
  3040. screen1_output_range = <0x02>;
  3041. screen1_output_scan = <0x00>;
  3042. screen1_output_aspect_ratio = <0x08>;
  3043. dev0_output_type = <0x04>;
  3044. dev0_output_mode = <0x0a>;
  3045. dev0_screen_id = <0x00>;
  3046. dev0_do_hpd = <0x01>;
  3047. dev1_output_type = <0x02>;
  3048. dev1_output_mode = <0x0b>;
  3049. dev1_screen_id = <0x01>;
  3050. dev1_do_hpd = <0x01>;
  3051. dev2_output_type = <0x00>;
  3052. def_output_dev = <0x00>;
  3053. hdmi_mode_check = <0x01>;
  3054. fb0_format = <0x00>;
  3055. fb0_width = <0x500>;
  3056. fb0_height = <0x2d0>;
  3057. fb1_format = <0x00>;
  3058. fb1_width = <0x00>;
  3059. fb1_height = <0x00>;
  3060. disp_para_zone = <0x01>;
  3061. };
  3062.  
  3063. lcd0@01c0c000 {
  3064. compatible = "allwinner,sunxi-lcd0";
  3065. pinctrl-names = "active\0sleep";
  3066. status = "okay";
  3067. device_type = "lcd0";
  3068. lcd_used = <0x00>;
  3069. lcd_driver_name = "default_lcd";
  3070. lcd_backlight = <0x32>;
  3071. lcd_if = <0x00>;
  3072. lcd_x = <0x320>;
  3073. lcd_y = <0x258>;
  3074. lcd_width = <0x96>;
  3075. lcd_height = <0x5e>;
  3076. lcd_dclk_freq = <0x28>;
  3077. lcd_pwm_used = <0x00>;
  3078. lcd_pwm_ch = <0x00>;
  3079. lcd_pwm_freq = <0xc350>;
  3080. lcd_pwm_pol = <0x01>;
  3081. lcd_pwm_max_limit = <0xff>;
  3082. lcd_hbp = <0xd8>;
  3083. lcd_ht = <0x420>;
  3084. lcd_hspw = <0x80>;
  3085. lcd_vbp = <0x1b>;
  3086. lcd_vt = <0x274>;
  3087. lcd_vspw = <0x04>;
  3088. lcd_lvds_if = <0x00>;
  3089. lcd_lvds_colordepth = <0x01>;
  3090. lcd_lvds_mode = <0x00>;
  3091. lcd_frm = <0x01>;
  3092. lcd_hv_clk_phase = <0x00>;
  3093. lcd_hv_sync_polarity = <0x00>;
  3094. lcd_gamma_en = <0x00>;
  3095. lcd_bright_curve_en = <0x00>;
  3096. lcd_cmap_en = <0x00>;
  3097. lcd_bl_en;
  3098. lcd_bl_en_power = "none";
  3099. lcd_power = "vcc-lcd-0";
  3100. lcd_fix_power = "vcc-dsi-33";
  3101. pinctrl-0 = <0xfd>;
  3102. lcd_pin_power = "vcc-pd";
  3103. pinctrl-1 = <0xfe>;
  3104. };
  3105.  
  3106. lcd1@01c0c001 {
  3107. compatible = "allwinner,sunxi-lcd1";
  3108. pinctrl-names = "active\0sleep";
  3109. status = "okay";
  3110. };
  3111.  
  3112. hdmi@06000000 {
  3113. compatible = "allwinner,sunxi-hdmi";
  3114. reg = <0x00 0x6000000 0x00 0x100000>;
  3115. interrupts = <0x00 0x40 0x00>;
  3116. clocks = <0x8b 0x8c 0x8d 0x8e>;
  3117. pinctrl-names = "ddc_active\0ddc_sleep\0cec_active\0cec_sleep";
  3118. pinctrl-1 = <0x90>;
  3119. pinctrl-2 = <0x91>;
  3120. pinctrl-3 = <0x92>;
  3121. status = "okay";
  3122. device_type = "hdmi";
  3123. hdmi_hdcp_enable = <0x00>;
  3124. hdmi_hdcp22_enable = <0x00>;
  3125. hdmi_cts_compatibility = <0x00>;
  3126. hdmi_cec_support = <0x00>;
  3127. hdmi_skip_bootedid = <0x01>;
  3128. pinctrl-0 = <0xff>;
  3129. ddc_en_io_ctrl = <0x01>;
  3130. ddc_io_ctrl = <0x81 0x07 0x02 0x01 0xffffffff 0xffffffff 0x00>;
  3131. };
  3132.  
  3133. tv0@01c94000 {
  3134. compatible = "allwinner,sunxi-tv";
  3135. reg = <0x00 0x1e40000 0x00 0x1000>;
  3136. status = "disabled";
  3137. device_type = "tv0";
  3138. dac_src0 = <0x00>;
  3139. dac_type0 = <0x00>;
  3140. interface = <0x01>;
  3141. };
  3142.  
  3143. tr@01000000 {
  3144. compatible = "allwinner,sun50i-tr";
  3145. reg = <0x00 0x1000000 0x00 0x200bc>;
  3146. interrupts = <0x00 0x60 0x104>;
  3147. clocks = <0x87>;
  3148. status = "okay";
  3149. };
  3150.  
  3151. pwm@0300a000 {
  3152. compatible = "allwinner,sunxi-pwm";
  3153. reg = <0x00 0x300a000 0x00 0x3c>;
  3154. clocks = <0x93>;
  3155. pwm-number = <0x02>;
  3156. pwm-base = <0x00>;
  3157. pwms = <0x94 0x95>;
  3158. };
  3159.  
  3160. pwm0@0300a000 {
  3161. compatible = "allwinner,sunxi-pwm0";
  3162. pinctrl-names = "active\0sleep";
  3163. reg_base = <0x300a000>;
  3164. reg_busy_offset = <0x00>;
  3165. reg_busy_shift = <0x1c>;
  3166. reg_enable_offset = <0x00>;
  3167. reg_enable_shift = <0x04>;
  3168. reg_clk_gating_offset = <0x00>;
  3169. reg_clk_gating_shift = <0x06>;
  3170. reg_bypass_offset = <0x00>;
  3171. reg_bypass_shift = <0x09>;
  3172. reg_pulse_start_offset = <0x00>;
  3173. reg_pulse_start_shift = <0x08>;
  3174. reg_mode_offset = <0x00>;
  3175. reg_mode_shift = <0x07>;
  3176. reg_polarity_offset = <0x00>;
  3177. reg_polarity_shift = <0x05>;
  3178. reg_period_offset = <0x04>;
  3179. reg_period_shift = <0x10>;
  3180. reg_period_width = <0x10>;
  3181. reg_active_offset = <0x04>;
  3182. reg_active_shift = <0x00>;
  3183. reg_active_width = <0x10>;
  3184. reg_prescal_offset = <0x00>;
  3185. reg_prescal_shift = <0x00>;
  3186. reg_prescal_width = <0x04>;
  3187. linux,phandle = <0x94>;
  3188. phandle = <0x94>;
  3189. device_type = "pwm0";
  3190. pwm_used = <0x01>;
  3191. pinctrl-0 = <0x102>;
  3192. pinctrl-1 = <0x103>;
  3193. };
  3194.  
  3195. pwm1@0300a000 {
  3196. compatible = "allwinner,sunxi-pwm1";
  3197. pinctrl-names = "active\0sleep";
  3198. reg_base = <0x300a000>;
  3199. reg_busy_offset = <0x00>;
  3200. reg_busy_shift = <0x1d>;
  3201. reg_enable_offset = <0x00>;
  3202. reg_enable_shift = <0x13>;
  3203. reg_clk_gating_offset = <0x00>;
  3204. reg_clk_gating_shift = <0x15>;
  3205. reg_bypass_offset = <0x00>;
  3206. reg_bypass_shift = <0x18>;
  3207. reg_pulse_start_offset = <0x00>;
  3208. reg_pulse_start_shift = <0x17>;
  3209. reg_mode_offset = <0x00>;
  3210. reg_mode_shift = <0x16>;
  3211. reg_polarity_offset = <0x00>;
  3212. reg_polarity_shift = <0x14>;
  3213. reg_period_offset = <0x08>;
  3214. reg_period_shift = <0x10>;
  3215. reg_period_width = <0x10>;
  3216. reg_active_offset = <0x08>;
  3217. reg_active_shift = <0x00>;
  3218. reg_active_width = <0x10>;
  3219. reg_prescal_offset = <0x00>;
  3220. reg_prescal_shift = <0x0f>;
  3221. reg_prescal_width = <0x04>;
  3222. linux,phandle = <0x95>;
  3223. phandle = <0x95>;
  3224. device_type = "pwm1";
  3225. pwm_used = <0x01>;
  3226. pinctrl-0 = <0x104>;
  3227. pinctrl-1 = <0x105>;
  3228. };
  3229.  
  3230. s_pwm@07020c00 {
  3231. compatible = "allwinner,sunxi-s_pwm";
  3232. reg = <0x00 0x7020c00 0x00 0x3c>;
  3233. clocks = <0x96>;
  3234. pwm-number = <0x01>;
  3235. pwm-base = <0x10>;
  3236. pwms = <0x97>;
  3237. };
  3238.  
  3239. spwm0@07020c00 {
  3240. compatible = "allwinner,sunxi-pwm16";
  3241. pinctrl-names = "active\0sleep";
  3242. reg_base = <0x7020c00>;
  3243. reg_busy_offset = <0x00>;
  3244. reg_busy_shift = <0x1c>;
  3245. reg_enable_offset = <0x00>;
  3246. reg_enable_shift = <0x04>;
  3247. reg_clk_gating_offset = <0x00>;
  3248. reg_clk_gating_shift = <0x06>;
  3249. reg_bypass_offset = <0x00>;
  3250. reg_bypass_shift = <0x09>;
  3251. reg_pulse_start_offset = <0x00>;
  3252. reg_pulse_start_shift = <0x08>;
  3253. reg_mode_offset = <0x00>;
  3254. reg_mode_shift = <0x07>;
  3255. reg_polarity_offset = <0x00>;
  3256. reg_polarity_shift = <0x05>;
  3257. reg_period_offset = <0x04>;
  3258. reg_period_shift = <0x10>;
  3259. reg_period_width = <0x10>;
  3260. reg_active_offset = <0x04>;
  3261. reg_active_shift = <0x00>;
  3262. reg_active_width = <0x10>;
  3263. reg_prescal_offset = <0x00>;
  3264. reg_prescal_shift = <0x00>;
  3265. reg_prescal_width = <0x04>;
  3266. linux,phandle = <0x97>;
  3267. phandle = <0x97>;
  3268. };
  3269.  
  3270. boot_disp {
  3271. compatible = "allwinner,boot_disp";
  3272. device_type = "boot_disp";
  3273. auto_hpd = <0x01>;
  3274. output_disp = <0x00>;
  3275. output_type = <0x03>;
  3276. output_mode = <0x0b>;
  3277. hdmi_channel = <0x00>;
  3278. hdmi_mode = <0x04>;
  3279. };
  3280.  
  3281. ac200 {
  3282. compatible = "allwinner,sunxi-ac200";
  3283. clocks = <0x89>;
  3284. pinctrl-names = "active\0sleep\0ccir_clk_active\0ccir_clk_sleep";
  3285. pinctrl-2 = <0x98>;
  3286. pinctrl-3 = <0x99>;
  3287. status = "okay";
  3288. device_type = "ac200";
  3289. tv_used = <0x01>;
  3290. tv_module_name = "tv_ac200";
  3291. tv_twi_used = <0x01>;
  3292. tv_twi_id = <0x03>;
  3293. tv_twi_addr = <0x10>;
  3294. tv_pwm_ch = <0x01>;
  3295. tv_clk_div = <0x05>;
  3296. tv_regulator_name = "vcc-audio-33";
  3297. pinctrl-0 = <0x100>;
  3298. pinctrl-1 = <0x101>;
  3299. };
  3300.  
  3301. vind@0 {
  3302. compatible = "allwinner,sunxi-vin-media\0simple-bus";
  3303. #address-cells = <0x02>;
  3304. #size-cells = <0x02>;
  3305. ranges;
  3306. device_id = <0x00>;
  3307. reg = <0x00 0x6620000 0x00 0x1000>;
  3308. clocks = <0x9a 0x02 0x9b 0x07 0x02>;
  3309. pinctrl-names = "mclk0-default\0mclk0-sleep";
  3310. pinctrl-0 = <0x9c>;
  3311. pinctrl-1 = <0x9d>;
  3312. status = "okay";
  3313.  
  3314. cci@0x0662e000 {
  3315. compatible = "allwinner,sunxi-csi_cci";
  3316. reg = <0x00 0x662e000 0x00 0x1000>;
  3317. interrupts = <0x00 0x48 0x04>;
  3318. clocks = <0x9e>;
  3319. pinctrl-names = "default\0sleep";
  3320. pinctrl-0 = <0x9f>;
  3321. pinctrl-1 = <0xa0>;
  3322. device_id = <0x00>;
  3323. status = "okay";
  3324. };
  3325.  
  3326. csi@0x06621000 {
  3327. device_type = "csi0";
  3328. compatible = "allwinner,sunxi-csi";
  3329. reg = <0x00 0x6621000 0x00 0x1000>;
  3330. interrupts = <0x00 0x46 0x04>;
  3331. pinctrl-names = "default\0sleep";
  3332. pinctrl-1 = <0xa2>;
  3333. device_id = <0x00>;
  3334. iommus = <0x19 0x04 0x01>;
  3335. status = "disabled";
  3336. csi0_sensor_list = <0x00>;
  3337. pinctrl-0 = <0x108 0x109>;
  3338.  
  3339. csi0_dev0 {
  3340. device_type = "csi0_dev0";
  3341. status = "disabled";
  3342. csi0_dev0_mname = "ov5640";
  3343. csi0_dev0_twi_addr = <0x78>;
  3344. csi0_dev0_pos = "rear";
  3345. csi0_dev0_isp_used = <0x01>;
  3346. csi0_dev0_fmt = <0x00>;
  3347. csi0_dev0_stby_mode = <0x00>;
  3348. csi0_dev0_vflip = <0x00>;
  3349. csi0_dev0_hflip = <0x00>;
  3350. csi0_dev0_iovdd = "iovdd-csi";
  3351. csi0_dev0_iovdd_vol = <0x2ab980>;
  3352. csi0_dev0_avdd = "avdd-csi";
  3353. csi0_dev0_avdd_vol = <0x2ab980>;
  3354. csi0_dev0_dvdd = "dvdd-csi-18";
  3355. csi0_dev0_dvdd_vol = <0x16e360>;
  3356. csi0_dev0_afvdd = "afvcc-csi";
  3357. csi0_dev0_afvdd_vol = <0x2ab980>;
  3358. csi0_dev0_power_en;
  3359. csi0_dev0_reset = <0x81 0x04 0x0e 0x01 0x00 0x01 0x00>;
  3360. csi0_dev0_pwdn = <0x81 0x04 0x0f 0x01 0x00 0x01 0x00>;
  3361. csi0_dev0_flash_used = <0x00>;
  3362. csi0_dev0_flash_type = <0x02>;
  3363. csi0_dev0_flash_en;
  3364. csi0_dev0_flash_mode;
  3365. csi0_dev0_flvdd;
  3366. csi0_dev0_flvdd_vol;
  3367. csi0_dev0_af_pwdn;
  3368. csi0_dev0_act_used = <0x00>;
  3369. csi0_dev0_act_name = "ad5820_act";
  3370. csi0_dev0_act_slave = <0x18>;
  3371. };
  3372.  
  3373. csi0_dev1 {
  3374. device_type = "csi0_dev1";
  3375. status = "disabled";
  3376. csi0_dev1_mname;
  3377. csi0_dev1_twi_addr = <0x78>;
  3378. csi0_dev1_pos = "rear";
  3379. csi0_dev1_isp_used = <0x01>;
  3380. csi0_dev1_fmt = <0x00>;
  3381. csi0_dev1_stby_mode = <0x00>;
  3382. csi0_dev1_vflip = <0x00>;
  3383. csi0_dev1_hflip = <0x00>;
  3384. csi0_dev1_iovdd = "iovdd-csi";
  3385. csi0_dev1_iovdd_vol = <0x2ab980>;
  3386. csi0_dev1_avdd = "avdd-csi";
  3387. csi0_dev1_avdd_vol = <0x2ab980>;
  3388. csi0_dev1_dvdd = "dvdd-csi-18";
  3389. csi0_dev1_dvdd_vol = <0x16e360>;
  3390. csi0_dev1_afvdd = "afvcc-csi";
  3391. csi0_dev1_afvdd_vol = <0x2ab980>;
  3392. csi0_dev1_power_en;
  3393. csi0_dev1_reset;
  3394. csi0_dev1_pwdn;
  3395. csi0_dev1_flash_used = <0x00>;
  3396. csi0_dev1_flash_type = <0x02>;
  3397. csi0_dev1_flash_en;
  3398. csi0_dev1_flash_mode;
  3399. csi0_dev1_flvdd;
  3400. csi0_dev1_flvdd_vol;
  3401. csi0_dev1_af_pwdn;
  3402. csi0_dev1_act_used = <0x00>;
  3403. csi0_dev1_act_name = "ad5820_act";
  3404. csi0_dev1_act_slave = <0x18>;
  3405. };
  3406. };
  3407.  
  3408. csi@1 {
  3409. device_type = "csi1";
  3410. compatible = "allwinner,sunxi-csi";
  3411. device_id = <0x01>;
  3412. iommus = <0x19 0x04 0x01>;
  3413. status = "disabled";
  3414. };
  3415.  
  3416. mipi@0 {
  3417. compatible = "allwinner,sunxi-mipi";
  3418. device_id = <0x00>;
  3419. status = "disabled";
  3420. };
  3421.  
  3422. mipi@1 {
  3423. compatible = "allwinner,sunxi-mipi";
  3424. device_id = <0x01>;
  3425. status = "disabled";
  3426. };
  3427.  
  3428. isp@0 {
  3429. compatible = "allwinner,sunxi-isp";
  3430. reg = <0x00 0x2100000 0x00 0x800>;
  3431. interrupts = <0x00 0x56 0x04>;
  3432. device_id = <0x00>;
  3433. iommus = <0x19 0x04 0x01>;
  3434. status = "okay";
  3435. linux,phandle = <0xa5>;
  3436. phandle = <0xa5>;
  3437. };
  3438.  
  3439. isp@1 {
  3440. compatible = "allwinner,sunxi-isp";
  3441. reg = <0x00 0x2100800 0x00 0x800>;
  3442. device_id = <0x01>;
  3443. iommus = <0x19 0x04 0x01>;
  3444. status = "disabled";
  3445. linux,phandle = <0xa6>;
  3446. phandle = <0xa6>;
  3447. };
  3448.  
  3449. scaler@0x02101000 {
  3450. compatible = "allwinner,sunxi-scaler";
  3451. reg = <0x00 0x2101000 0x00 0x400>;
  3452. device_id = <0x00>;
  3453. iommus = <0x19 0x04 0x01>;
  3454. status = "okay";
  3455. };
  3456.  
  3457. scaler@0x02101400 {
  3458. compatible = "allwinner,sunxi-scaler";
  3459. reg = <0x00 0x2101400 0x00 0x400>;
  3460. device_id = <0x01>;
  3461. iommus = <0x19 0x04 0x01>;
  3462. status = "okay";
  3463. };
  3464.  
  3465. scaler@2 {
  3466. compatible = "allwinner,sunxi-scaler";
  3467. device_id = <0x02>;
  3468. iommus = <0x19 0x04 0x01>;
  3469. status = "disabled";
  3470. };
  3471.  
  3472. scaler@3 {
  3473. compatible = "allwinner,sunxi-scaler";
  3474. device_id = <0x03>;
  3475. iommus = <0x19 0x04 0x01>;
  3476. status = "disabled";
  3477. };
  3478.  
  3479. actuator@0 {
  3480. device_type = "actuator0";
  3481. compatible = "allwinner,sunxi-actuator";
  3482. actuator0_name = "ad5820_act";
  3483. actuator0_slave = <0x18>;
  3484. actuator0_af_pwdn;
  3485. actuator0_afvdd = "afvcc-csi";
  3486. actuator0_afvdd_vol = <0x2ab980>;
  3487. status = "disabled";
  3488. linux,phandle = <0xa4>;
  3489. phandle = <0xa4>;
  3490. };
  3491.  
  3492. flash@0 {
  3493. device_type = "flash0";
  3494. compatible = "allwinner,sunxi-flash";
  3495. flash0_type = <0x02>;
  3496. flash0_en;
  3497. flash0_mode;
  3498. flash0_flvdd = [00];
  3499. flash0_flvdd_vol;
  3500. device_id = <0x00>;
  3501. status = "disabled";
  3502. linux,phandle = <0xa3>;
  3503. phandle = <0xa3>;
  3504. };
  3505.  
  3506. sensor@0 {
  3507. device_type = "sensor0";
  3508. sensor0_mname = "ov5640";
  3509. sensor0_twi_cci_id = <0x00>;
  3510. sensor0_twi_addr = <0x78>;
  3511. sensor0_pos = "rear";
  3512. sensor0_isp_used = <0x00>;
  3513. sensor0_fmt = <0x00>;
  3514. sensor0_stby_mode = <0x00>;
  3515. sensor0_vflip = <0x00>;
  3516. sensor0_hflip = <0x00>;
  3517. sensor0_iovdd = "iovdd-csi";
  3518. sensor0_iovdd_vol = <0x2ab980>;
  3519. sensor0_avdd = "avdd-csi";
  3520. sensor0_avdd_vol = <0x2ab980>;
  3521. sensor0_dvdd = "dvdd-csi-18";
  3522. sensor0_dvdd_vol = <0x16e360>;
  3523. sensor0_power_en;
  3524. sensor0_reset = <0x81 0x04 0x0e 0x01 0x00 0x01 0x00>;
  3525. sensor0_pwdn = <0x81 0x04 0x10 0x01 0x00 0x01 0x00>;
  3526. flash_handle = <0xa3>;
  3527. act_handle = <0xa4>;
  3528. status = "okay";
  3529. linux,phandle = <0xa7>;
  3530. phandle = <0xa7>;
  3531. };
  3532.  
  3533. sensor@1 {
  3534. device_type = "sensor1";
  3535. sensor1_mname = "ov5647";
  3536. sensor1_twi_cci_id = <0x00>;
  3537. sensor1_twi_addr = <0x6c>;
  3538. sensor1_pos = "front";
  3539. sensor1_isp_used = <0x00>;
  3540. sensor1_fmt = <0x00>;
  3541. sensor1_stby_mode = <0x00>;
  3542. sensor1_vflip = <0x00>;
  3543. sensor1_hflip = <0x00>;
  3544. sensor1_iovdd = "iovdd-csi";
  3545. sensor1_iovdd_vol = <0x2ab980>;
  3546. sensor1_avdd = "avdd-csi";
  3547. sensor1_avdd_vol = <0x2ab980>;
  3548. sensor1_dvdd = "dvdd-csi-18";
  3549. sensor1_dvdd_vol = <0x16e360>;
  3550. sensor1_power_en;
  3551. sensor1_reset = <0x81 0x04 0x0e 0x01 0x00 0x01 0x00>;
  3552. sensor1_pwdn = <0x81 0x04 0x0f 0x01 0x00 0x01 0x00>;
  3553. flash_handle;
  3554. act_handle;
  3555. status = "okay";
  3556. linux,phandle = <0xa8>;
  3557. phandle = <0xa8>;
  3558. };
  3559.  
  3560. vinc@0x06623000 {
  3561. device_type = "vinc0";
  3562. compatible = "allwinner,sunxi-vin-core";
  3563. reg = <0x00 0x6623000 0x00 0x100>;
  3564. interrupts = <0x00 0x43 0x04>;
  3565. vinc0_csi_sel = <0x00>;
  3566. vinc0_mipi_sel = <0xff>;
  3567. vinc0_isp_sel = <0x00>;
  3568. vinc0_sensor_sel = <0x00>;
  3569. vinc0_sensor_list = <0x00>;
  3570. isp_handle = <0xa5 0xa6>;
  3571. sensor_handle = <0xa7 0xa8>;
  3572. device_id = <0x00>;
  3573. iommus = <0x19 0x04 0x01>;
  3574. status = "okay";
  3575. };
  3576.  
  3577. vinc@0x06623100 {
  3578. device_type = "vinc1";
  3579. compatible = "allwinner,sunxi-vin-core";
  3580. reg = <0x00 0x6623100 0x00 0x100>;
  3581. interrupts = <0x00 0x44 0x04>;
  3582. vinc1_csi_sel = <0x00>;
  3583. vinc1_mipi_sel = <0xff>;
  3584. vinc1_isp_sel = <0x00>;
  3585. vinc1_sensor_sel = <0x01>;
  3586. vinc1_sensor_list = <0x00>;
  3587. isp_handle = <0xa5 0xa6>;
  3588. sensor_handle = <0xa7 0xa8>;
  3589. device_id = <0x01>;
  3590. iommus = <0x19 0x04 0x01>;
  3591. status = "okay";
  3592. };
  3593. };
  3594.  
  3595. vdevice@0 {
  3596. compatible = "allwinner,sun50i-vdevice";
  3597. device_type = "Vdevice";
  3598. pinctrl-names = "default";
  3599. test-gpios = <0x81 0x01 0x00 0x01 0x02 0x02 0x01>;
  3600. status = "disabled";
  3601. pinctrl-0 = <0x110>;
  3602. };
  3603.  
  3604. emce@01905000 {
  3605. compatible = "allwinner,sunxi-emce";
  3606. device_name = "emce";
  3607. reg = <0x00 0x1905000 0x00 0x100>;
  3608. clock-frequency = <0x11e1a300>;
  3609. clocks = <0xaa 0x1b>;
  3610. };
  3611.  
  3612. ce@1904000 {
  3613. compatible = "allwinner,sunxi-ce";
  3614. device_name = "ce";
  3615. reg = <0x00 0x1904000 0x00 0xa0 0x00 0x1904800 0x00 0xa0>;
  3616. interrupts = <0x00 0x57 0xff01 0x00 0x58 0xff01>;
  3617. clock-frequency = <0x11e1a300>;
  3618. clocks = <0xab 0x1b>;
  3619. };
  3620.  
  3621. deinterlace@0x01420000 {
  3622. #address-cells = <0x01>;
  3623. #size-cells = <0x00>;
  3624. compatible = "allwinner,sunxi-deinterlace";
  3625. reg = <0x00 0x1420000 0x00 0x20c>;
  3626. interrupts = <0x00 0x4f 0x04>;
  3627. clocks = <0xac 0x02>;
  3628. iommus = <0x19 0x02 0x01>;
  3629. status = "okay";
  3630. device_type = "di";
  3631. };
  3632.  
  3633. smartcard@0x05005000 {
  3634. #address-cells = <0x01>;
  3635. #size-cells = <0x00>;
  3636. compatible = "allwinner,sunxi-scr";
  3637. device_type = "scr0";
  3638. reg = <0x00 0x5005000 0x00 0x400>;
  3639. interrupts = <0x00 0x08 0x04>;
  3640. clocks = <0xad 0xae>;
  3641. clock-frequency = <0x16e3600>;
  3642. pinctrl-names = "default\0sleep";
  3643. pinctrl-0 = <0xaf 0xb0>;
  3644. pinctrl-1 = <0xb1>;
  3645. status = "disabled";
  3646. };
  3647.  
  3648. smartcard@0x05005400 {
  3649. #address-cells = <0x01>;
  3650. #size-cells = <0x00>;
  3651. compatible = "allwinner,sunxi-scr";
  3652. device_type = "scr1";
  3653. reg = <0x00 0x5005400 0x00 0x400>;
  3654. interrupts = <0x00 0x09 0x04>;
  3655. clocks = <0xb2 0xae>;
  3656. clock-frequency = <0x16e3600>;
  3657. pinctrl-names = "default\0sleep";
  3658. pinctrl-0 = <0xb3 0xb4>;
  3659. pinctrl-1 = <0xb5>;
  3660. status = "disabled";
  3661. };
  3662.  
  3663. pmu@0 {
  3664. interrupts = <0x00 0x60 0x04>;
  3665. status = "okay";
  3666. device_type = "pmu0";
  3667. compatible = "axpdummy";
  3668. pmu_id = <0x83>;
  3669.  
  3670. powerkey@0 {
  3671. status = "disabled";
  3672. device_type = "powerkey0";
  3673. compatible = "axp806-powerkey";
  3674. pmu_powkey_off_time = <0x1770>;
  3675. pmu_powkey_off_func = <0x00>;
  3676. pmu_powkey_off_en = <0x01>;
  3677. pmu_powkey_long_time = <0x5dc>;
  3678. pmu_powkey_on_time = <0x3e8>;
  3679. };
  3680.  
  3681. regulator@0 {
  3682. status = "okay";
  3683. device_type = "regulator0";
  3684. compatible = "axpdummy-regulator";
  3685. regulator_count = <0x07>;
  3686. regulator1 = "axpdummy_ldo1 none vdd-cpua";
  3687. regulator2 = "axpdummy_ldo2 none vdd-gpu vdd-sys vdd-hdmi vdd-usb vdd-pcie";
  3688. regulator3 = "axpdummy_ldo3 none vcc-dram";
  3689. regulator4 = "axpdummy_ldo4 none vcc-pl vcc-led vcc-ir vcc-io vcc-audio-33 vcc-pg vcc-pm ac-ldoin vcc-wifi1 vcc-wifi2 vcc-wifi-io vcc-tv vcc-emmc-33 vcc-emmcv vcc-emmcvq18 vcc-sdcv vcc-sdcvq33 vcc-sdcvd";
  3690. regulator5 = "axpdummy_ldo5 none vcc-5v";
  3691. regulator6 = "axpdummy_ldo6 none vcc-rtc vdd18-lpddr vcc-usb usb-dvdd vcc-ts vcc-ephy vcc-pcie-slot vdd-dram-18 vdd-bias vcc-emmc-18 vcc-card vcc-pd vcc-uart vcc-camera-33";
  3692. regulator7 = "axpdummy_ldo7 none vdd18-dram vcc18-bias vcc-pll vcc-hdmi vcc-pc vdd-efuse vccio-dcxo";
  3693. };
  3694.  
  3695. axp_gpio@0 {
  3696. gpio-controller;
  3697. #size-cells = <0x00>;
  3698. #gpio-cells = <0x06>;
  3699. status = "okay";
  3700. device_type = "axp_pio";
  3701. linux,phandle = <0xfa>;
  3702. phandle = <0xfa>;
  3703. };
  3704.  
  3705. charger@0 {
  3706. status = "okay";
  3707. device_type = "charger0";
  3708. pmu_bat_unused = <0x01>;
  3709. pmu_pwroff_vol = <0xce4>;
  3710. power_start = <0x00>;
  3711. };
  3712. };
  3713.  
  3714. nmi@0x01f00c00 {
  3715. #address-cells = <0x01>;
  3716. #size-cells = <0x00>;
  3717. compatible = "allwinner,sunxi-nmi";
  3718. reg = <0x00 0x1f00c00 0x00 0x50>;
  3719. nmi_irq_ctrl = <0x0c>;
  3720. nmi_irq_en = <0x40>;
  3721. nmi_irq_status = <0x10>;
  3722. nmi_irq_mask = <0x50>;
  3723. status = "okay";
  3724. };
  3725.  
  3726. nand0@04011000 {
  3727. compatible = "allwinner,sun50iw6-nand";
  3728. device_type = "nand0";
  3729. reg = <0x00 0x4011000 0x00 0x1000>;
  3730. interrupts = <0x00 0x22 0x04>;
  3731. clocks = <0x1b 0xb6 0xb7>;
  3732. pinctrl-names = "default\0sleep";
  3733. pinctrl-1 = <0xba>;
  3734. nand0_regulator1 = "vcc-nand";
  3735. nand0_regulator2 = "none";
  3736. nand0_cache_level = <0x55aaaa55>;
  3737. nand0_flush_cache_num = <0x55aaaa55>;
  3738. nand0_capacity_level = <0x55aaaa55>;
  3739. nand0_id_number_ctl = <0x55aaaa55>;
  3740. nand0_print_level = <0x55aaaa55>;
  3741. nand0_p0 = <0x55aaaa55>;
  3742. nand0_p1 = <0x55aaaa55>;
  3743. nand0_p2 = <0x55aaaa55>;
  3744. nand0_p3 = <0x55aaaa55>;
  3745. status = "okay";
  3746. nand0_support_2ch = <0x00>;
  3747. pinctrl-0 = <0xfb 0xfc>;
  3748. };
  3749.  
  3750. ts0@05060000 {
  3751. compatible = "allwinner,sun50i-tsc";
  3752. device_type = "ts0";
  3753. reg = <0x00 0x5060000 0x00 0x1000>;
  3754. interrupts = <0x00 0x0e 0x04>;
  3755. clocks = <0x02 0xbb>;
  3756. clock-frequency = <0x7270e00>;
  3757. pinctrl-names = "ts0-default\0ts1-default\0ts2-default\0ts3-default\0ts0-sleep\0ts1-sleep\0ts2-sleep\0ts3-sleep";
  3758. pinctrl-0 = <0xbc>;
  3759. pinctrl-1 = <0xbd>;
  3760. pinctrl-2 = <0xbe>;
  3761. pinctrl-3 = <0xbf>;
  3762. pinctrl-4 = <0xc0>;
  3763. pinctrl-5 = <0xc1>;
  3764. pinctrl-6 = <0xc2>;
  3765. pinctrl-7 = <0xc3>;
  3766. ts0config = <0x01>;
  3767. ts1config = <0x00>;
  3768. ts2config = <0x00>;
  3769. ts3config = <0x00>;
  3770. status = "okay";
  3771. };
  3772.  
  3773. thermal_sensor {
  3774. compatible = "allwinner,thermal_sensor";
  3775. reg = <0x00 0x5070400 0x00 0x400>;
  3776. interrupts = <0x00 0x0f 0x00>;
  3777. clocks = <0x07 0xc4>;
  3778. sensor_num = <0x02>;
  3779. combine_num = <0x02>;
  3780. alarm_low_temp = <0x69>;
  3781. alarm_high_temp = <0x6e>;
  3782. alarm_temp_hysteresis = <0x0f>;
  3783. shut_temp = <0x73>;
  3784. status = "okay";
  3785.  
  3786. ths_combine0 {
  3787. compatible = "allwinner,ths_combine0";
  3788. #thermal-sensor-cells = <0x01>;
  3789. combine_sensor_num = <0x01>;
  3790. combine_sensor_type = "cpu";
  3791. combine_sensor_temp_type = "max";
  3792. combine_sensor_id = <0x00>;
  3793. linux,phandle = <0xc5>;
  3794. phandle = <0xc5>;
  3795. };
  3796.  
  3797. ths_combine1 {
  3798. compatible = "allwinner,ths_combine1";
  3799. #thermal-sensor-cells = <0x01>;
  3800. combine_sensor_num = <0x01>;
  3801. combine_sensor_type = "gpu";
  3802. combine_sensor_temp_type = "max";
  3803. combine_sensor_id = <0x01>;
  3804. linux,phandle = <0xcd>;
  3805. phandle = <0xcd>;
  3806. };
  3807. };
  3808.  
  3809. cpu_budget_cool {
  3810. device_type = "cpu_budget_cool";
  3811. compatible = "allwinner,budget_cooling";
  3812. #cooling-cells = <0x02>;
  3813. status = "okay";
  3814. state_cnt = <0x07>;
  3815. cluster_num = <0x01>;
  3816. state0 = <0x1b7740 0x04>;
  3817. state1 = <0x16b480 0x04>;
  3818. state2 = <0x142440 0x03>;
  3819. state3 = <0x107ac0 0x02>;
  3820. state4 = <0xd8cc0 0x01>;
  3821. state5 = <0xafc80 0x01>;
  3822. state6 = <0x75300 0x01>;
  3823. linux,phandle = <0xc7>;
  3824. phandle = <0xc7>;
  3825. };
  3826.  
  3827. gpu_cooling {
  3828. compatible = "allwinner,gpu_cooling";
  3829. reg = <0x00 0x00 0x00 0x00>;
  3830. #cooling-cells = <0x02>;
  3831. status = "okay";
  3832. state_cnt = <0x04>;
  3833. state0 = <0x00>;
  3834. state1 = <0x01>;
  3835. state2 = <0x02>;
  3836. state3 = <0x03>;
  3837. linux,phandle = <0xcf>;
  3838. phandle = <0xcf>;
  3839. };
  3840.  
  3841. thermal-zones {
  3842.  
  3843. cpu_thermal_zone {
  3844. polling-delay-passive = <0x3e8>;
  3845. polling-delay = <0x3e8>;
  3846. thermal-sensors = <0xc5 0x00>;
  3847.  
  3848. trips {
  3849.  
  3850. t0 {
  3851. temperature = <0x3c>;
  3852. type = "passive";
  3853. hysteresis = <0x00>;
  3854. linux,phandle = <0xc6>;
  3855. phandle = <0xc6>;
  3856. };
  3857.  
  3858. t1 {
  3859. temperature = <0x5a>;
  3860. type = "passive";
  3861. hysteresis = <0x00>;
  3862. linux,phandle = <0xc8>;
  3863. phandle = <0xc8>;
  3864. };
  3865.  
  3866. t2 {
  3867. temperature = <0x5f>;
  3868. type = "passive";
  3869. hysteresis = <0x00>;
  3870. linux,phandle = <0xc9>;
  3871. phandle = <0xc9>;
  3872. };
  3873.  
  3874. t3 {
  3875. temperature = <0x64>;
  3876. type = "passive";
  3877. hysteresis = <0x00>;
  3878. linux,phandle = <0xca>;
  3879. phandle = <0xca>;
  3880. };
  3881.  
  3882. t4 {
  3883. temperature = <0x69>;
  3884. type = "passive";
  3885. hysteresis = <0x00>;
  3886. linux,phandle = <0xcb>;
  3887. phandle = <0xcb>;
  3888. };
  3889.  
  3890. t5 {
  3891. temperature = <0x6e>;
  3892. type = "passive";
  3893. hysteresis = <0x00>;
  3894. linux,phandle = <0xcc>;
  3895. phandle = <0xcc>;
  3896. };
  3897.  
  3898. t6 {
  3899. temperature = <0x73>;
  3900. type = "critical";
  3901. hysteresis = <0x00>;
  3902. };
  3903. };
  3904.  
  3905. cooling-maps {
  3906.  
  3907. bind0 {
  3908. contribution = <0x00>;
  3909. trip = <0xc6>;
  3910. cooling-device = <0xc7 0x01 0x01>;
  3911. };
  3912.  
  3913. bind1 {
  3914. contribution = <0x00>;
  3915. trip = <0xc8>;
  3916. cooling-device = <0xc7 0x02 0x02>;
  3917. };
  3918.  
  3919. bind2 {
  3920. contribution = <0x00>;
  3921. trip = <0xc9>;
  3922. cooling-device = <0xc7 0x03 0x03>;
  3923. };
  3924.  
  3925. bind3 {
  3926. contribution = <0x00>;
  3927. trip = <0xca>;
  3928. cooling-device = <0xc7 0x04 0x04>;
  3929. };
  3930.  
  3931. bind4 {
  3932. contribution = <0x00>;
  3933. trip = <0xcb>;
  3934. cooling-device = <0xc7 0x05 0x05>;
  3935. };
  3936.  
  3937. bind5 {
  3938. contribution = <0x00>;
  3939. trip = <0xcc>;
  3940. cooling-device = <0xc7 0x06 0x06>;
  3941. };
  3942. };
  3943. };
  3944.  
  3945. gpu_thermal_zone {
  3946. polling-delay-passive = <0x3e8>;
  3947. polling-delay = <0x7d0>;
  3948. thermal-sensors = <0xcd 0x01>;
  3949.  
  3950. trips {
  3951.  
  3952. t0 {
  3953. temperature = <0x5f>;
  3954. type = "passive";
  3955. hysteresis = <0x00>;
  3956. linux,phandle = <0xce>;
  3957. phandle = <0xce>;
  3958. };
  3959.  
  3960. t1 {
  3961. temperature = <0x64>;
  3962. type = "passive";
  3963. hysteresis = <0x00>;
  3964. linux,phandle = <0xd0>;
  3965. phandle = <0xd0>;
  3966. };
  3967.  
  3968. t2 {
  3969. temperature = <0x69>;
  3970. type = "passive";
  3971. hysteresis = <0x00>;
  3972. linux,phandle = <0xd1>;
  3973. phandle = <0xd1>;
  3974. };
  3975.  
  3976. t3 {
  3977. temperature = <0x73>;
  3978. type = "critical";
  3979. hysteresis = <0x00>;
  3980. };
  3981. };
  3982.  
  3983. cooling-maps {
  3984.  
  3985. bind0 {
  3986. contribution = <0x00>;
  3987. trip = <0xce>;
  3988. cooling-device = <0xcf 0x01 0x01>;
  3989. };
  3990.  
  3991. bind1 {
  3992. contribution = <0x00>;
  3993. trip = <0xd0>;
  3994. cooling-device = <0xcf 0x02 0x02>;
  3995. };
  3996.  
  3997. bind2 {
  3998. contribution = <0x00>;
  3999. trip = <0xd1>;
  4000. cooling-device = <0xcf 0x03 0x03>;
  4001. };
  4002. };
  4003. };
  4004. };
  4005.  
  4006. keyboard {
  4007. compatible = "allwinner,keyboard_1200mv";
  4008. reg = <0x00 0x5070800 0x00 0x400>;
  4009. interrupts = <0x00 0x10 0x00>;
  4010. status = "okay";
  4011. key_cnt = <0x05>;
  4012. key0 = <0x73 0x73>;
  4013. key1 = <0xeb 0x72>;
  4014. key2 = <0x14a 0x8b>;
  4015. key3 = <0x1a4 0x1c>;
  4016. key4 = <0x208 0x66>;
  4017. };
  4018.  
  4019. eth@05020000 {
  4020. compatible = "allwinner,sunxi-gmac";
  4021. reg = <0x00 0x5020000 0x00 0x10000 0x00 0x3000030 0x00 0x04>;
  4022. interrupts = <0x00 0x0c 0x04>;
  4023. interrupt-names = "gmacirq";
  4024. clocks = <0xd2>;
  4025. clock-names = "gmac";
  4026. pinctrl-names = "default";
  4027. phy-mode = "rmii";
  4028. tx-delay = <0x00>;
  4029. rx-delay = <0x00>;
  4030. phy-rst;
  4031. gmac-power0 = "vcc-ephy";
  4032. status = "okay";
  4033. device_type = "gmac0";
  4034. pinctrl-0 = <0xe2>;
  4035. gmac-power1;
  4036. gmac-power2;
  4037. };
  4038.  
  4039. product {
  4040. device_type = "product";
  4041. version = "100";
  4042. machine = "petrel-p1";
  4043. };
  4044.  
  4045. platform {
  4046. device_type = "platform";
  4047. eraseflag = <0x01>;
  4048. };
  4049.  
  4050. target {
  4051. device_type = "target";
  4052. boot_clock = <0x528>;
  4053. storage_type = <0xffffffff>;
  4054. burn_key = <0x01>;
  4055. dragonboard_test = <0x00>;
  4056. power_mode = <0x01>;
  4057. advert_enable = <0x00>;
  4058. };
  4059.  
  4060. secure {
  4061. device_type = "secure";
  4062. dram_region_mbytes = <0x50>;
  4063. drm_region_mbytes = <0x00>;
  4064. drm_region_start_mbytes = <0x00>;
  4065. };
  4066.  
  4067. power_sply {
  4068. device_type = "power_sply";
  4069. dcdca_vol = <0xf4628>;
  4070. aldo2_vol = <0xf4f24>;
  4071. cldo2_vol = <0xce4>;
  4072. cldo3_vol = <0xce4>;
  4073. bldo3_vol = <0x708>;
  4074. bldo4_vol = <0xf4948>;
  4075. };
  4076.  
  4077. gpio_bias {
  4078. device_type = "gpio_bias";
  4079. pc_bias = "axp806:bldo2:1800";
  4080. pg_bias = "axp806:bldo3:1800";
  4081. };
  4082.  
  4083. ir_boot_recovery {
  4084. device_type = "ir_boot_recovery";
  4085. status = "disabled";
  4086. ir_work_mode = <0x02>;
  4087. ir_press_times = <0x02>;
  4088. ir_detect_time = <0x7d0>;
  4089. ir_key_no_duplicate = <0x00>;
  4090. ir_recovery_key_code0 = <0x04>;
  4091. ir_addr_code0 = <0xff00>;
  4092. ir_recovery_key_code1 = <0x10>;
  4093. ir_addr_code1 = <0xff00>;
  4094. };
  4095.  
  4096. card_boot {
  4097. device_type = "card_boot";
  4098. logical_start = <0xa000>;
  4099. sprite_gpio0 = <0xdc 0x0b 0x04 0x01 0xffffffff 0xffffffff 0x01>;
  4100. next_work = <0x03>;
  4101. };
  4102.  
  4103. key_boot_recovery {
  4104. device_type = "key_boot_recovery";
  4105. status = "okay";
  4106. press_mode_enable = <0x00>;
  4107. key_work_mode = <0x01>;
  4108. short_press_mode = <0x00>;
  4109. long_press_mode = <0x01>;
  4110. key_press_time = <0x7d0>;
  4111. recovery_key = <0xdc 0x0b 0x02 0x00 0xffffffff 0xffffffff 0xffffffff>;
  4112. };
  4113.  
  4114. boot_init_gpio {
  4115. device_type = "boot_init_gpio";
  4116. status = "okay";
  4117. gpio0 = <0xdc 0x0b 0x07 0x01 0xffffffff 0xffffffff 0x01>;
  4118. gpio1 = <0xdc 0x0b 0x04 0x01 0xffffffff 0xffffffff 0x00>;
  4119. gpio2 = <0x81 0x07 0x02 0x01 0xffffffff 0xffffffff 0x01>;
  4120. };
  4121.  
  4122. pm_para {
  4123. device_type = "pm_para";
  4124. standby_mode = <0x01>;
  4125. standby_stay_cpu = <0x01>;
  4126. };
  4127.  
  4128. card0_boot_para {
  4129. device_type = "card0_boot_para";
  4130. card_ctrl = <0x00>;
  4131. card_high_speed = <0x01>;
  4132. card_line = <0x04>;
  4133. pinctrl-0 = <0xdd>;
  4134. };
  4135.  
  4136. card2_boot_para {
  4137. device_type = "card2_boot_para";
  4138. card_ctrl = <0x02>;
  4139. card_high_speed = <0x01>;
  4140. card_line = <0x08>;
  4141. pinctrl-0 = <0xde>;
  4142. sdc_ex_dly_used = <0x02>;
  4143. sdc_io_1v8 = <0x01>;
  4144. sdc_tm4_hs400_max_freq = <0x64>;
  4145. sdc_tm4_hs200_max_freq = <0x96>;
  4146. };
  4147.  
  4148. twi_para {
  4149. device_type = "twi_para";
  4150. twi_port = <0x00>;
  4151. pinctrl-0 = <0xdf>;
  4152. };
  4153.  
  4154. uart_para {
  4155. device_type = "uart_para";
  4156. uart_debug_port = <0x00>;
  4157. pinctrl-0 = <0xe0>;
  4158. };
  4159.  
  4160. jtag_para {
  4161. device_type = "jtag_para";
  4162. jtag_enable = <0x01>;
  4163. pinctrl-0 = <0xe1>;
  4164. };
  4165.  
  4166. clock {
  4167. device_type = "clock";
  4168. pll4 = <0x12c>;
  4169. pll6 = <0x258>;
  4170. pll8 = <0x168>;
  4171. pll9 = <0x129>;
  4172. pll10 = <0x108>;
  4173. };
  4174.  
  4175. rtp_para {
  4176. device_type = "rtp_para";
  4177. rtp_used = <0x00>;
  4178. rtp_screen_size = <0x05>;
  4179. rtp_regidity_level = <0x05>;
  4180. rtp_press_threshold_enable = <0x00>;
  4181. rtp_press_threshold = <0x1f40>;
  4182. rtp_sensitive_level = <0x0f>;
  4183. rtp_exchange_x_y_flag = <0x00>;
  4184. };
  4185.  
  4186. ctp {
  4187. device_type = "ctp";
  4188. compatible = "allwinner,sun50i-ctp-para";
  4189. status = "disabled";
  4190. ctp_twi_id = <0x00>;
  4191. ctp_twi_addr = <0x5d>;
  4192. ctp_screen_max_x = <0x500>;
  4193. ctp_screen_max_y = <0x320>;
  4194. ctp_revert_x_flag = <0x01>;
  4195. ctp_revert_y_flag = <0x01>;
  4196. ctp_exchange_x_y_flag = <0x01>;
  4197. ctp_int_port = <0x81 0x07 0x04 0x06 0xffffffff 0xffffffff 0xffffffff>;
  4198. ctp_wakeup = <0x81 0x07 0x08 0x01 0xffffffff 0xffffffff 0x01>;
  4199. ctp_power_ldo = "vcc-ctp";
  4200. ctp_power_ldo_vol = <0xce4>;
  4201. ctp_power_io;
  4202. };
  4203.  
  4204. ctp_list {
  4205. device_type = "ctp_list";
  4206. compatible = "allwinner,sun50i-ctp-list";
  4207. ctp_det_used = <0x00>;
  4208. ft5x_ts = <0x01>;
  4209. gt82x = <0x01>;
  4210. gslX680 = <0x01>;
  4211. gt9xx_ts = <0x00>;
  4212. gt9xxnew_ts = <0x01>;
  4213. gt811 = <0x01>;
  4214. zet622x = <0x01>;
  4215. aw5306_ts = <0x01>;
  4216. };
  4217.  
  4218. tkey_para {
  4219. device_type = "tkey_para";
  4220. tkey_used = <0x00>;
  4221. tkey_twi_id;
  4222. tkey_twi_addr;
  4223. tkey_int;
  4224. };
  4225.  
  4226. motor_para {
  4227. device_type = "motor_para";
  4228. motor_used = <0x01>;
  4229. motor_shake = <0xfa 0xfffe 0x03 0x01 0xffffffff 0xffffffff 0x01>;
  4230. };
  4231.  
  4232. esm {
  4233. device_type = "esm";
  4234. esm_img_size_addr = <0x00>;
  4235. esm_img_buff_addr = <0x00>;
  4236. };
  4237.  
  4238. pwm16 {
  4239. device_type = "pwm16";
  4240. status = "disabled";
  4241. pinctrl-0 = <0x106>;
  4242. pinctrl-1 = <0x107>;
  4243. };
  4244.  
  4245. tvout_para {
  4246. device_type = "tvout_para";
  4247. tvout_used;
  4248. tvout_channel_num;
  4249. tv_en;
  4250. };
  4251.  
  4252. tvin_para {
  4253. device_type = "tvin_para";
  4254. tvin_used;
  4255. tvin_channel_num;
  4256. };
  4257.  
  4258. smc {
  4259. device_type = "smc";
  4260. smc_used;
  4261. smc_rst;
  4262. smc_vppen;
  4263. smc_vppp;
  4264. smc_det;
  4265. smc_vccen;
  4266. smc_sck;
  4267. smc_sda;
  4268. };
  4269.  
  4270. gpio_para {
  4271. device_type = "gpio_para";
  4272. compatible = "allwinner,sunxi-init-gpio";
  4273. status = "okay";
  4274. gpio_num = <0x03>;
  4275. gpio_pin_1 = <0xdc 0x0b 0x07 0x01 0xffffffff 0xffffffff 0x01>;
  4276. gpio_pin_2 = <0xdc 0x0b 0x03 0x01 0xffffffff 0xffffffff 0x00>;
  4277. gpio_pin_3 = <0xdc 0x0b 0x04 0x01 0xffffffff 0xffffffff 0x00>;
  4278. normal_led = "gpio_pin_1";
  4279. standby_led = "gpio_pin_3";
  4280. easy_light_used = <0x01>;
  4281. normal_led_light = <0x01>;
  4282. standby_led_light = <0x01>;
  4283. };
  4284.  
  4285. usbc3 {
  4286. device_type = "usbc3";
  4287. status = "disabled";
  4288. usb_drv_vbus_gpio;
  4289. usb_host_init_state = <0x01>;
  4290. usb_regulator_io = "nocare";
  4291. usb_wakeup_suspend = <0x01>;
  4292. };
  4293.  
  4294. serial_feature {
  4295. device_type = "serial_feature";
  4296. sn_filename = "sn.txt";
  4297. };
  4298.  
  4299. gsensor {
  4300. device_type = "gsensor";
  4301. compatible = "allwinner,sun50i-gsensor-para";
  4302. status = "disabled";
  4303. gsensor_twi_id = <0x01>;
  4304. gsensor_twi_addr = <0x18>;
  4305. gsensor_int1 = <0x81 0x00 0x09 0x06 0x01 0xffffffff 0xffffffff>;
  4306. gsensor_int2;
  4307. gsensor_vcc_io = "vcc-deviceio";
  4308. gsensor_vcc_io_val = <0xc1c>;
  4309. };
  4310.  
  4311. gsensor_list_para {
  4312. device_type = "gsensor_list_para";
  4313. compatible = "allwinner,sun50i-gsensor-list-para";
  4314. gsensor_det_used = <0x00>;
  4315. lsm9ds0_acc_mag = <0x01>;
  4316. bma250 = <0x01>;
  4317. mma8452 = <0x01>;
  4318. mma7660 = <0x01>;
  4319. mma865x = <0x01>;
  4320. afa750 = <0x01>;
  4321. lis3de_acc = <0x01>;
  4322. lis3dh_acc = <0x01>;
  4323. kxtik = <0x01>;
  4324. dmard10 = <0x00>;
  4325. dmard06 = <0x01>;
  4326. mxc622x = <0x01>;
  4327. fxos8700 = <0x01>;
  4328. lsm303d = <0x00>;
  4329. };
  4330.  
  4331. 3g_para {
  4332. device_type = "3g_para";
  4333. status = "disabled";
  4334. 3g_usbc_num = <0x02>;
  4335. 3g_uart_num = <0x00>;
  4336. bb_vbat = <0xdc 0x0b 0x03 0x01 0xffffffff 0xffffffff 0x00>;
  4337. bb_host_wake = <0xdc 0x0c 0x00 0x01 0xffffffff 0xffffffff 0x00>;
  4338. bb_on = <0xdc 0x0c 0x01 0x01 0xffffffff 0xffffffff 0x00>;
  4339. bb_pwr_on = <0xdc 0x0c 0x03 0x01 0xffffffff 0xffffffff 0x00>;
  4340. bb_wake = <0xdc 0x0c 0x04 0x01 0xffffffff 0xffffffff 0x00>;
  4341. bb_rf_dis = <0xdc 0x0c 0x05 0x01 0xffffffff 0xffffffff 0x00>;
  4342. bb_rst = <0xdc 0x0c 0x06 0x01 0xffffffff 0xffffffff 0x00>;
  4343. 3g_int;
  4344. };
  4345.  
  4346. gy_para {
  4347. device_type = "gy_para";
  4348. compatible = "allwinner,sun50i-gyr_sensors-para";
  4349. gy_used = <0x00>;
  4350. gy_twi_id = <0x02>;
  4351. gy_twi_addr = <0x6a>;
  4352. gy_int1 = <0x81 0x00 0x0a 0x06 0x01 0xffffffff 0xffffffff>;
  4353. gy_int2;
  4354. };
  4355.  
  4356. gy_list_para {
  4357. device_type = "gy_list_para";
  4358. compatible = "allwinner,sun50i-gyr_sensors-list-para";
  4359. gy_det_used = <0x01>;
  4360. lsm9ds0_gyr = <0x01>;
  4361. l3gd20_gyr = <0x00>;
  4362. bmg160_gyr = <0x01>;
  4363. };
  4364.  
  4365. ls_para {
  4366. device_type = "ls_para";
  4367. compatible = "allwinner,sun50i-lsensors-para";
  4368. ls_used = <0x00>;
  4369. ls_twi_id = <0x02>;
  4370. ls_twi_addr = <0x23>;
  4371. ls_int = <0x81 0x00 0x0c 0x06 0x01 0xffffffff 0xffffffff>;
  4372. };
  4373.  
  4374. ls_list_para {
  4375. device_type = "ls_list_para";
  4376. compatible = "allwinner,sun50i-lsensors-list-para";
  4377. ls_det_used = <0x01>;
  4378. ltr_501als = <0x01>;
  4379. jsa1212 = <0x00>;
  4380. jsa1127 = <0x01>;
  4381. };
  4382.  
  4383. compass_para {
  4384. device_type = "compass_para";
  4385. compatible = "allwinner,sun50i-compass-para";
  4386. compass_used = <0x00>;
  4387. compass_twi_id = <0x02>;
  4388. compass_twi_addr = <0x0d>;
  4389. compass_int = <0x81 0x00 0x0b 0x06 0x01 0xffffffff 0xffffffff>;
  4390. };
  4391.  
  4392. compass_list_para {
  4393. device_type = "compass_list_para";
  4394. compatible = "allwinner,sun50i-compass-list-para";
  4395. compass_det_used = <0x01>;
  4396. lsm9ds0 = <0x01>;
  4397. lsm303d = <0x00>;
  4398. akm8963 = <0x01>;
  4399. };
  4400.  
  4401. s_rsb0 {
  4402. device_type = "s_rsb0";
  4403. status = "disabled";
  4404. pinctrl-0 = <0x10e>;
  4405. };
  4406.  
  4407. box_standby_led {
  4408. device_type = "box_standby_led";
  4409. gpio0 = <0xdc 0x0b 0x07 0x01 0xffffffff 0xffffffff 0x00>;
  4410. gpio1 = <0xdc 0x0b 0x03 0x01 0xffffffff 0xffffffff 0x01>;
  4411. gpio2 = <0xdc 0x0b 0x04 0x01 0xffffffff 0xffffffff 0x01>;
  4412. };
  4413.  
  4414. gpio_power_key {
  4415. device_type = "gpio_power_key";
  4416. compatible = "allwinner,sunxi-gpio-power-key";
  4417. status = "disabled";
  4418. key_io = <0xdc 0x0b 0x05 0x00 0xffffffff 0xffffffff 0x00>;
  4419. trigger_mode = <0x01>;
  4420. };
  4421.  
  4422. fd655_key {
  4423. device_type = "fd655_key";
  4424. compatible = "rockchip,fd655_dev";
  4425. clk_pin = <0x81 0x07 0x03 0x00 0xffffffff 0xffffffff 0x00>;
  4426. dat_pin = <0x81 0x03 0x1a 0x00 0xffffffff 0xffffffff 0x00>;
  4427. };
  4428.  
  4429. auto_print {
  4430. device_type = "auto_print";
  4431. status = "disabled";
  4432. };
  4433. };
  4434.  
  4435. aliases {
  4436. serial0 = "/soc@03000000/uart@05000000\0/soc@03000000/uart@05000000";
  4437. serial1 = "/soc@03000000/uart@05000400\0/soc@03000000/uart@05000400";
  4438. serial2 = "/soc@03000000/uart@05000800\0/soc@03000000/uart@05000800";
  4439. serial3 = "/soc@03000000/uart@05000c00\0/soc@03000000/uart@05000c00";
  4440. twi0 = "/soc@03000000/twi@0x05002000\0/soc@03000000/twi@0x05002000";
  4441. twi1 = "/soc@03000000/twi@0x05002400\0/soc@03000000/twi@0x05002400";
  4442. twi2 = "/soc@03000000/twi@0x05002800\0/soc@03000000/twi@0x05002800";
  4443. twi3 = "/soc@03000000/twi@0x05002c00\0/soc@03000000/twi@0x05002c00";
  4444. spi0 = "/soc@03000000/spi@05010000\0/soc@03000000/spi@05010000";
  4445. spi1 = "/soc@03000000/spi@05011000\0/soc@03000000/spi@05011000";
  4446. pcie = "/soc@03000000/pcie@0x05400000\0/soc@03000000/pcie@0x05400000";
  4447. scr0 = "/soc@03000000/smartcard@0x05005000\0/soc@03000000/smartcard@0x05005000";
  4448. scr1 = "/soc@03000000/smartcard@0x05005400\0/soc@03000000/smartcard@0x05005400";
  4449. gmac0 = "/soc@03000000/eth@05020000\0/soc@03000000/eth@05020000";
  4450. global_timer0 = "/soc@03000000/timer@03009000\0/soc@03000000/timer@03009000";
  4451. mmc0 = "/soc@03000000/sdmmc@04020000\0/soc@03000000/sdmmc@04020000";
  4452. mmc2 = "/soc@03000000/sdmmc@04022000\0/soc@03000000/sdmmc@04022000";
  4453. nand0 = "/soc@03000000/nand0@04011000\0/soc@03000000/nand0@04011000";
  4454. disp = "/soc@03000000/disp@01000000\0/soc@03000000/disp@01000000";
  4455. lcd0 = "/soc@03000000/lcd0@01c0c000\0/soc@03000000/lcd0@01c0c000";
  4456. lcd1 = "/soc@03000000/lcd1@01c0c001\0/soc@03000000/lcd1@01c0c001";
  4457. hdmi = "/soc@03000000/hdmi@06000000\0/soc@03000000/hdmi@06000000";
  4458. pwm = "/soc@03000000/pwm@0300a000\0/soc@03000000/pwm@0300a000";
  4459. pwm0 = "/soc@03000000/pwm0@0300a000\0/soc@03000000/pwm0@0300a000";
  4460. pwm1 = "/soc@03000000/pwm1@0300a000\0/soc@03000000/pwm1@0300a000";
  4461. tv0 = "/soc@03000000/tv0@01c94000\0/soc@03000000/tv0@01c94000";
  4462. s_pwm = "/soc@03000000/s_pwm@07020c00\0/soc@03000000/s_pwm@07020c00";
  4463. spwm0 = "/soc@03000000/spwm0@07020c00\0/soc@03000000/spwm0@07020c00";
  4464. boot_disp = "/soc@03000000/boot_disp\0/soc@03000000/boot_disp";
  4465. charger0 = "/soc@03000000/pmu@0/charger@0\0/soc@03000000/pmu@0/charger@0";
  4466. regulator0 = "/soc@03000000/pmu@0/regulator@0\0/soc@03000000/pmu@0/regulator@0";
  4467. };
  4468.  
  4469. chosen {
  4470. bootargs = "earlyprintk=sunxi-uart,0x05000000 loglevel=8 initcall_debug=1 console=ttyS0 init=/init";
  4471. linux,initrd-start = <0x00 0x00>;
  4472. linux,initrd-end = <0x00 0x00>;
  4473. };
  4474.  
  4475. cpus {
  4476. #address-cells = <0x02>;
  4477. #size-cells = <0x00>;
  4478.  
  4479. cpu@0 {
  4480. device_type = "cpu";
  4481. compatible = "arm,cortex-a53\0arm,armv8";
  4482. reg = <0x00 0x00>;
  4483. enable-method = "psci";
  4484. cpufreq_tbl = <0x75300 0x9e340 0xc7380 0xd8cc0 0x107ac0 0x142440 0x16b480 0x1b7740>;
  4485. clock-latency = <0x1e8480>;
  4486. clock-frequency = <0x4ead9a00>;
  4487. cpu-idle-states = <0xd4 0xd5 0xd6>;
  4488. };
  4489.  
  4490. cpu@1 {
  4491. device_type = "cpu";
  4492. compatible = "arm,cortex-a53\0arm,armv8";
  4493. reg = <0x00 0x01>;
  4494. enable-method = "psci";
  4495. clock-frequency = <0x4ead9a00>;
  4496. cpu-idle-states = <0xd4 0xd5 0xd6>;
  4497. };
  4498.  
  4499. cpu@2 {
  4500. device_type = "cpu";
  4501. compatible = "arm,cortex-a53\0arm,armv8";
  4502. reg = <0x00 0x02>;
  4503. enable-method = "psci";
  4504. clock-frequency = <0x4ead9a00>;
  4505. cpu-idle-states = <0xd4 0xd5 0xd6>;
  4506. };
  4507.  
  4508. cpu@3 {
  4509. device_type = "cpu";
  4510. compatible = "arm,cortex-a53\0arm,armv8";
  4511. reg = <0x00 0x03>;
  4512. enable-method = "psci";
  4513. clock-frequency = <0x4ead9a00>;
  4514. cpu-idle-states = <0xd4 0xd5 0xd6>;
  4515. };
  4516.  
  4517. idle-states {
  4518. entry-method = "arm,psci";
  4519.  
  4520. cpu-sleep-0 {
  4521. compatible = "arm,idle-state";
  4522. arm,psci-suspend-param = <0x10000>;
  4523. entry-latency-us = <0xfa0>;
  4524. exit-latency-us = <0x2710>;
  4525. min-residency-us = <0x3a98>;
  4526. linux,phandle = <0xd4>;
  4527. phandle = <0xd4>;
  4528. };
  4529.  
  4530. cluster-sleep-0 {
  4531. compatible = "arm,idle-state";
  4532. arm,psci-suspend-param = <0x1010000>;
  4533. entry-latency-us = <0xc350>;
  4534. exit-latency-us = <0x186a0>;
  4535. min-residency-us = <0x3d090>;
  4536. linux,phandle = <0xd5>;
  4537. phandle = <0xd5>;
  4538. };
  4539.  
  4540. sys-sleep-0 {
  4541. compatible = "arm,idle-state";
  4542. arm,psci-suspend-param = <0x2010000>;
  4543. entry-latency-us = <0x186a0>;
  4544. exit-latency-us = <0x1e8480>;
  4545. min-residency-us = <0x44aa20>;
  4546. linux,phandle = <0xd6>;
  4547. phandle = <0xd6>;
  4548. };
  4549. };
  4550. };
  4551.  
  4552. psci {
  4553. compatible = "arm,psci-0.2";
  4554. method = "smc";
  4555. psci_version = <0x84000000>;
  4556. cpu_suspend = <0xc4000001>;
  4557. cpu_off = <0x84000002>;
  4558. cpu_on = <0xc4000003>;
  4559. affinity_info = <0xc4000004>;
  4560. migrate = <0xc4000005>;
  4561. migrate_info_type = <0x84000006>;
  4562. migrate_info_up_cpu = <0xc4000007>;
  4563. system_off = <0x84000008>;
  4564. system_reset = <0x84000009>;
  4565. };
  4566.  
  4567. n_brom {
  4568. compatible = "allwinner,n-brom";
  4569. reg = <0x00 0x00 0x00 0xa000>;
  4570. };
  4571.  
  4572. s_brom {
  4573. compatible = "allwinner,s-brom";
  4574. reg = <0x00 0x00 0x00 0x10000>;
  4575. };
  4576.  
  4577. sram_ctrl {
  4578. device_type = "sram_ctrl";
  4579. compatible = "allwinner,sram_ctrl";
  4580. reg = <0x00 0x3000000 0x00 0x100>;
  4581. };
  4582.  
  4583. sram_a1 {
  4584. compatible = "allwinner,sram_a1";
  4585. reg = <0x00 0x20000 0x00 0x8000>;
  4586. };
  4587.  
  4588. sram_a2 {
  4589. compatible = "allwinner,sram_a2";
  4590. reg = <0x00 0x100000 0x00 0x14000>;
  4591. };
  4592.  
  4593. prcm {
  4594. compatible = "allwinner,prcm";
  4595. reg = <0x00 0x1f01400 0x00 0x400>;
  4596. };
  4597.  
  4598. cpuscfg {
  4599. compatible = "allwinner,cpuscfg";
  4600. reg = <0x00 0x1f01c00 0x00 0x400>;
  4601. };
  4602.  
  4603. ion {
  4604. compatible = "allwinner,sunxi-ion";
  4605.  
  4606. system {
  4607. type = <0x00>;
  4608. };
  4609.  
  4610. system_contig {
  4611. type = <0x01>;
  4612. };
  4613.  
  4614. cma {
  4615. type = <0x04>;
  4616. };
  4617.  
  4618. secure {
  4619. type = <0x06>;
  4620. };
  4621. };
  4622.  
  4623. dram {
  4624. compatible = "allwinner,dram";
  4625. clocks = <0xd7>;
  4626. clock-names = "pll_ddr";
  4627. dram_clk = <0x2a0>;
  4628. dram_type = <0x03>;
  4629. dram_zq = <0x3b3bfb>;
  4630. dram_odt_en = <0x01>;
  4631. dram_para1 = <0x30fb>;
  4632. dram_para2 = <0x00>;
  4633. dram_mr0 = <0x1c70>;
  4634. dram_mr1 = <0x40>;
  4635. dram_mr2 = <0x18>;
  4636. dram_mr3 = <0x00>;
  4637. dram_tpr0 = <0x48a192>;
  4638. dram_tpr1 = <0x1b1a94b>;
  4639. dram_tpr2 = <0x61043>;
  4640. dram_tpr3 = <0x78787896>;
  4641. dram_tpr4 = <0x00>;
  4642. dram_tpr5 = <0x00>;
  4643. dram_tpr6 = "\t\t\t";
  4644. dram_tpr7 = <0x1e08a1e0>;
  4645. dram_tpr8 = <0x00>;
  4646. dram_tpr9 = <0x00>;
  4647. dram_tpr10 = <0x00>;
  4648. dram_tpr11 = <0x00>;
  4649. dram_tpr12 = <0x1212>;
  4650. dram_tpr13 = <0x2001>;
  4651. device_type = "dram";
  4652. clk = <0x348>;
  4653. dram_mr4 = <0x00>;
  4654. dram_mr5 = <0x400>;
  4655. dram_mr6 = <0x848>;
  4656. };
  4657.  
  4658. memory@40000000 {
  4659. device_type = "memory";
  4660. reg = <0x00 0x40000000 0x00 0x20000000>;
  4661. };
  4662.  
  4663. interrupt-controller@03020000 {
  4664. compatible = "arm,cortex-a15-gic\0arm,cortex-a9-gic";
  4665. #interrupt-cells = <0x03>;
  4666. #address-cells = <0x00>;
  4667. device_type = "gic";
  4668. interrupt-controller;
  4669. reg = <0x00 0x3021000 0x00 0x1000 0x00 0x3022000 0x00 0x2000 0x00 0x3024000 0x00 0x2000 0x00 0x3026000 0x00 0x2000>;
  4670. interrupts = <0x01 0x09 0xf04>;
  4671. linux,phandle = <0x01>;
  4672. phandle = <0x01>;
  4673. };
  4674.  
  4675. sunxi-sid@03006000 {
  4676. compatible = "allwinner,sunxi-sid";
  4677. device_type = "sid";
  4678. reg = <0x00 0x3006000 0x00 0x1000>;
  4679. };
  4680.  
  4681. sunxi-chipid@03006200 {
  4682. compatible = "allwinner,sunxi-chipid";
  4683. device_type = "chipid";
  4684. reg = <0x00 0x3006200 0x00 0x200>;
  4685. };
  4686.  
  4687. timer {
  4688. compatible = "arm,armv8-timer";
  4689. interrupts = <0x01 0x0d 0xff01 0x01 0x0e 0xff01 0x01 0x0b 0xff01 0x01 0x0a 0xff01>;
  4690. clock-frequency = <0x16e3600>;
  4691. };
  4692.  
  4693. pmu {
  4694. compatible = "arm,armv8-pmuv3";
  4695. interrupts = <0x00 0x8c 0x04 0x00 0x8d 0x04 0x00 0x8e 0x04 0x00 0x8f 0x04>;
  4696. };
  4697.  
  4698. dvfs_table {
  4699. compatible = "allwinner,dvfs_table";
  4700. multi-vf-table;
  4701.  
  4702. dvfs_table_0 {
  4703. max_freq = <0x6b49d200>;
  4704. min_freq = <0x1c9c3800>;
  4705. lv_count = <0x08>;
  4706. lv1_freq = <0x6b49d200>;
  4707. lv1_volt = <0x488>;
  4708. lv1_pval = <0x514>;
  4709. lv2_freq = <0x58b11400>;
  4710. lv2_volt = <0x424>;
  4711. lv2_pval = <0x514>;
  4712. lv3_freq = <0x4ead9a00>;
  4713. lv3_volt = <0x3e8>;
  4714. lv3_pval = <0x514>;
  4715. lv4_freq = "@_~";
  4716. lv4_volt = <0x3ac>;
  4717. lv4_pval = <0x514>;
  4718. lv5_freq = <0x34edce00>;
  4719. lv5_volt = <0x370>;
  4720. lv5_pval = <0x514>;
  4721. lv6_freq = <0x00>;
  4722. lv6_volt = <0x370>;
  4723. lv6_pval = <0x514>;
  4724. lv7_freq = <0x00>;
  4725. lv7_volt = <0x370>;
  4726. lv7_pval = <0x514>;
  4727. lv8_freq = <0x00>;
  4728. lv8_volt = <0x370>;
  4729. lv8_pval = <0x514>;
  4730. device_type = "dvfs_table_0";
  4731. };
  4732.  
  4733. dvfs_table_1 {
  4734. max_freq = <0x6b49d200>;
  4735. min_freq = <0x1c9c3800>;
  4736. lv_count = <0x08>;
  4737. lv1_freq = <0x6b49d200>;
  4738. lv1_volt = <0x44c>;
  4739. lv1_pval = <0x514>;
  4740. lv2_freq = <0x58b11400>;
  4741. lv2_volt = <0x3e8>;
  4742. lv2_pval = <0x514>;
  4743. lv3_freq = <0x4ead9a00>;
  4744. lv3_volt = <0x3ac>;
  4745. lv3_pval = <0x514>;
  4746. lv4_freq = "@_~";
  4747. lv4_volt = <0x370>;
  4748. lv4_pval = <0x514>;
  4749. lv5_freq = <0x34edce00>;
  4750. lv5_volt = <0x334>;
  4751. lv5_pval = <0x514>;
  4752. lv6_freq = <0x00>;
  4753. lv6_volt = <0x334>;
  4754. lv6_pval = <0x514>;
  4755. lv7_freq = <0x00>;
  4756. lv7_volt = <0x334>;
  4757. lv7_pval = <0x514>;
  4758. lv8_freq = <0x00>;
  4759. lv8_volt = <0x334>;
  4760. lv8_pval = <0x514>;
  4761. device_type = "dvfs_table_1";
  4762. };
  4763.  
  4764. dvfs_table_2 {
  4765. max_freq = <0x6b49d200>;
  4766. min_freq = <0x1c9c3800>;
  4767. lv_count = <0x08>;
  4768. lv1_freq = <0x6b49d200>;
  4769. lv1_volt = <0x424>;
  4770. lv1_pval = <0x514>;
  4771. lv2_freq = <0x58b11400>;
  4772. lv2_volt = <0x3c0>;
  4773. lv2_pval = <0x514>;
  4774. lv3_freq = <0x4ead9a00>;
  4775. lv3_volt = <0x384>;
  4776. lv3_pval = <0x514>;
  4777. lv4_freq = "@_~";
  4778. lv4_volt = <0x348>;
  4779. lv4_pval = <0x514>;
  4780. lv5_freq = <0x34edce00>;
  4781. lv5_volt = <0x320>;
  4782. lv5_pval = <0x514>;
  4783. lv6_freq = <0x00>;
  4784. lv6_volt = <0x320>;
  4785. lv6_pval = <0x514>;
  4786. lv7_freq = <0x00>;
  4787. lv7_volt = <0x320>;
  4788. lv7_pval = <0x514>;
  4789. lv8_freq = <0x00>;
  4790. lv8_volt = <0x320>;
  4791. lv8_pval = <0x514>;
  4792. device_type = "dvfs_table_2";
  4793. };
  4794. };
  4795.  
  4796. dramfreq {
  4797. compatible = "allwinner,sunxi-dramfreq";
  4798. reg = <0x00 0x4002000 0x00 0x1000 0x00 0x4003000 0x00 0x3000 0x00 0x3001000 0x00 0x1000>;
  4799. interrupts = <0x00 0x21 0x04>;
  4800. clocks = <0xd7>;
  4801. status = "okay";
  4802. };
  4803.  
  4804. uboot {
  4805. };
  4806.  
  4807. iommu@030f0000 {
  4808. compatible = "allwinner,sunxi-iommu";
  4809. reg = <0x00 0x30f0000 0x00 0x1000>;
  4810. interrupts = <0x00 0x39 0x04>;
  4811. interrupt-names = "iommu-irq";
  4812. clocks = <0xd8>;
  4813. clock-names = "iommu";
  4814. #iommu-cells = <0x02>;
  4815. status = "okay";
  4816. linux,phandle = <0x19>;
  4817. phandle = <0x19>;
  4818. };
  4819.  
  4820. gpu@0x01800000 {
  4821. device_type = "gpu";
  4822. compatible = "arm,mali-t720\0arm,mali-midgard";
  4823. reg = <0x00 0x1800000 0x00 0x4000>;
  4824. interrupts = <0x00 0x53 0x04 0x00 0x54 0x04 0x00 0x55 0x04>;
  4825. interrupt-names = "GPU\0JOB\0MMU";
  4826. clocks = <0xd9 0xda>;
  4827. clock-names = "clk_parent\0clk_mali";
  4828. operating-points = <0xb8920 0xfde80 0x98580 0xe7ef0 0x8ca00 0xe30d0 0x83d60 0xde2b0 0x7b0c0 0xd9490 0x6f540 0xd4670 0x69780 0xd1f60 0x668a0 0xcf850 0x639c0 0xcd140 0x5dc00 0xcaa30 0x57e40 0xc8320 0x52080 0xc5c10 0x4c2c0 0xc5c10 0x40740 0xc5c10 0x34bc0 0xc5c10>;
  4829. independent_power = <0x00>;
  4830. gpu_idle = <0x00>;
  4831. dvfs_status = <0x01>;
  4832. temp_ctrl_status = <0x01>;
  4833. scene_ctrl_status = <0x01>;
  4834. max_normal_level = <0x0d>;
  4835. };
  4836.  
  4837. wlan {
  4838. compatible = "allwinner,sunxi-wlan";
  4839. wlan_busnum = <0x01>;
  4840. wlan_usbnum = <0x03>;
  4841. wlan_power;
  4842. wlan_io_regulator = "vcc-wifi-io";
  4843. status = "okay";
  4844. device_type = "wlan";
  4845. wlan_power1 = "vcc-wifi1";
  4846. wlan_power2 = "vcc-wifi2";
  4847. wlan_en;
  4848. wlan_regon = <0xdc 0x0c 0x03 0x01 0xffffffff 0xffffffff 0x00>;
  4849. wlan_hostwake = <0xdc 0x0c 0x00 0x00 0xffffffff 0xffffffff 0x00>;
  4850. };
  4851.  
  4852. bt {
  4853. compatible = "allwinner,sunxi-bt";
  4854. clocks = <0xdb>;
  4855. bt_power = "vcc-wifi";
  4856. bt_io_regulator = "vcc-wifi-io";
  4857. status = "okay";
  4858. device_type = "bt";
  4859. bt_rst_n = <0xdc 0x0c 0x04 0x01 0xffffffff 0xffffffff 0x00>;
  4860. };
  4861.  
  4862. btlpm {
  4863. compatible = "allwinner,sunxi-btlpm";
  4864. uart_index = <0x01>;
  4865. status = "okay";
  4866. device_type = "btlpm";
  4867. bt_hostwake_enable = <0x00>;
  4868. bt_wake = <0xdc 0x0c 0x02 0x01 0xffffffff 0xffffffff 0x01>;
  4869. bt_hostwake = <0xdc 0x0c 0x01 0x06 0xffffffff 0xffffffff 0x00>;
  4870. };
  4871. };
  4872.  
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