mega_sim

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-- Company:
-- Engineer:
--
-- Create Date: 11/20/2019 04:51:33 PM
-- Design Name:
-- Module Name: ent - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
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-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY mealy IS
PORT (
i: IN BIT;
reset, clock:IN BIT;
O: OUT std_logic);
END  mealy;


ARCHITECTURE arc_mealy OF mealy IS

    TYPE state IS (s0, s1, s2, s3, s4, s5, s6);
    SIGNAL pr_state, nx_state: state;

    BEGIN

        PROCESS (reset, clock)
        BEGIN
        IF (reset='1') THEN
        pr_state <= s0;
        ELSIF (clock'EVENT AND clock='1') THEN
        pr_state <= nx_state;
        END IF;
        END PROCESS;

        PROCESS (I, pr_state)
        BEGIN
            CASE pr_state IS

                WHEN s0 => IF (i = '0') THEN
                        O <= '1';
                        nx_state <= s1;
                    else
                        O <= '0';
                        nx_state <= s2;
                    END IF;

                WHEN s1 => IF (i = '0') THEN
                        O <= '1';
                        nx_state <= s3;
                    ELSE
                        O <= '0';
                        nx_state <= s4;
                    END IF;

                WHEN s2 => IF (i= '0') THEN
                        O <= '0';
                        nx_state <= s4;
                    ELSE
                        O <= '1';
                        nx_state <= s4;
                    END IF;

                WHEN s3 => IF (i = '0') THEN
                        O <= '0';
                        nx_state <= s5;
                    else
                        O <= '0';
                        nx_state <= s5;
                    END IF;

                WHEN s4 => IF (i = '0') THEN
                        O <= '1';
                        nx_state <= s5;
                    else
                        O <= '0';
                        nx_state <= s6;
                    END IF;

                WHEN s5 => IF (i = '0') THEN
                        O <= '0';
                        nx_state <= s0;
                    else
                        O <= '1';
                        nx_state <= s0;
                    END IF;


                WHEN s6 => IF ( i = '0') THEN
                            O <= '1';
                            nx_state <= s0;
                        END IF;

            END CASE;
        END PROCESS;
END arc_mealy;



library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;



entity tb_mealy is
end tb_mealy;


architecture arc_tb_mealy of tb_mealy is

component mealy is
PORT (
i: IN BIT;
reset, clock:IN BIT;
O: OUT std_logic);
end component;

signal tb_input : bit;
signal tb_rst : bit;
signal tb_clk : bit;
signal tb_output : std_logic;

begin
moor : mealy port map(tb_input,tb_rst,tb_clk,tb_output);
tb_rst <='1' after 25 ns,'0' after 30 ns,'1' after 65 ns,'0' after 70 ns;
tb_input <= '0' after 0 ns,'1' after  44ns,'0' after 54 ns,'1' after 60 ns,'0' after 115 ns;-- s0-s1-3 2ns
tb_clk <= '0','1' after 5 ns, '0' after 10 ns, '1' after 15ns, '0' after 20 ns, '1' after 25 ns,'0' after 30 ns,'1' after 35ns, '0' after 40 ns, '1' after 45 ns, '0' after 50 ns, '1' after 55 ns, '0' after 60 ns,'1' after 65 ns, '0' after 70 ns,'1' after 75 ns, '0' after 80 ns, '1' after 85 ns, '0' after 90 ns,'1' after 95 ns, '0' after 100 ns,'1' after 105 ns, '0' after 110 ns,'1' after 115 ns, '0' after 120 ns;--3ns -> s0 +1n
--tb_rst <= ;
--tb_input <= ;--s4
--tb_input <= ;--s5
--tb_rst <= ;
--tb_rst <= ;
--tb_input <=;--s1-s2-s4-s6
--tb_rst <= ;

end arc_tb_mealy;