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linux-5.6.0-0-manjaro-pinebookpro.patch

xmixahlx
Mar 30th, 2020
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  1. diff -uNr '--exclude=.git' linux-5.6-rc7/arch/arm64/boot/dts/rockchip/Makefile linux-pinebook-pro_v5.6/arch/arm64/boot/dts/rockchip/Makefile
  2. --- linux-5.6-rc7/arch/arm64/boot/dts/rockchip/Makefile 2020-03-22 18:31:56.000000000 -0700
  3. +++ linux-pinebook-pro_v5.6/arch/arm64/boot/dts/rockchip/Makefile 2020-03-23 07:26:33.000000000 -0700
  4. @@ -28,6 +28,7 @@
  5. dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-m4.dtb
  6. dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-neo4.dtb
  7. dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-orangepi.dtb
  8. +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-pinebook-pro.dtb
  9. dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb
  10. dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc.dtb
  11. dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-mezzanine.dtb
  12. diff -uNr '--exclude=.git' linux-5.6-rc7/arch/arm64/boot/dts/rockchip/rk3399.dtsi linux-pinebook-pro_v5.6/arch/arm64/boot/dts/rockchip/rk3399.dtsi
  13. --- linux-5.6-rc7/arch/arm64/boot/dts/rockchip/rk3399.dtsi 2020-03-22 18:31:56.000000000 -0700
  14. +++ linux-pinebook-pro_v5.6/arch/arm64/boot/dts/rockchip/rk3399.dtsi 2020-03-23 07:26:33.000000000 -0700
  15. @@ -9,6 +9,7 @@
  16. #include <dt-bindings/interrupt-controller/irq.h>
  17. #include <dt-bindings/pinctrl/rockchip.h>
  18. #include <dt-bindings/power/rk3399-power.h>
  19. +#include <dt-bindings/suspend/rockchip-rk3399.h>
  20. #include <dt-bindings/thermal/thermal.h>
  21.  
  22. / {
  23. @@ -2661,4 +2662,27 @@
  24. };
  25.  
  26. };
  27. +
  28. + rockchip_suspend: rockchip-suspend {
  29. + compatible = "rockchip,pm-rk3399";
  30. + status = "disabled";
  31. + rockchip,sleep-debug-en = <0>;
  32. + rockchip,virtual-poweroff = <0>;
  33. + rockchip,sleep-mode-config = <
  34. + (0
  35. + | RKPM_SLP_ARMPD
  36. + | RKPM_SLP_PERILPPD
  37. + | RKPM_SLP_DDR_RET
  38. + | RKPM_SLP_PLLPD
  39. + | RKPM_SLP_OSC_DIS
  40. + | RKPM_SLP_CENTER_PD
  41. + | RKPM_SLP_AP_PWROFF
  42. + )
  43. + >;
  44. + rockchip,wakeup-config = <
  45. + (0
  46. + | RKPM_GPIO_WKUP_EN
  47. + )
  48. + >;
  49. + };
  50. };
  51. diff -uNr '--exclude=.git' linux-5.6-rc7/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts linux-pinebook-pro_v5.6/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
  52. --- linux-5.6-rc7/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts 1969-12-31 16:00:00.000000000 -0800
  53. +++ linux-pinebook-pro_v5.6/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts 2020-03-23 07:26:33.000000000 -0700
  54. @@ -0,0 +1,1172 @@
  55. +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  56. +/*
  57. + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
  58. + * Copyright (c) 2018 Akash Gajjar <Akash_Gajjar@mentor.com>
  59. + * Copyright (c) 2020 Tobias Schramm <t.schramm@manjaro.org>
  60. + */
  61. +
  62. +/dts-v1/;
  63. +#include <dt-bindings/input/gpio-keys.h>
  64. +#include <dt-bindings/input/linux-event-codes.h>
  65. +#include <dt-bindings/pwm/pwm.h>
  66. +#include <dt-bindings/usb/pd.h>
  67. +#include <dt-bindings/leds/common.h>
  68. +#include "rk3399.dtsi"
  69. +#include "rk3399-opp.dtsi"
  70. +
  71. +/ {
  72. + model = "Pine64 Pinebook Pro";
  73. + compatible = "pine64,pinebook-pro", "rockchip,rk3399";
  74. +
  75. + chosen {
  76. + bootargs = "earlycon=uart8250,mmio32,0xff1a0000";
  77. + stdout-path = "serial2:1500000n8";
  78. + };
  79. +
  80. + memory {
  81. + device_type = "memory";
  82. + reg = <0x0 0x00200000 0x0 0xf7e00000>;
  83. + };
  84. +
  85. + backlight: edp-backlight {
  86. + compatible = "pwm-backlight";
  87. + power-supply = <&vcc_12v>;
  88. + pwms = <&pwm0 0 740740 0>;
  89. + };
  90. +
  91. + bat: battery {
  92. + compatible = "simple-battery";
  93. + charge-full-design-microamp-hours = <9800000>;
  94. + voltage-max-design-microvolt = <4350000>;
  95. + voltage-min-design-microvolt = <3000000>;
  96. + };
  97. +
  98. + edp_panel: edp-panel {
  99. + compatible = "boe,nv140fhmn49";
  100. + backlight = <&backlight>;
  101. + enable-gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
  102. + pinctrl-names = "default";
  103. + pinctrl-0 = <&panel_en_gpio>;
  104. + power-supply = <&vcc3v3_panel>;
  105. +
  106. + ports {
  107. + #address-cells = <1>;
  108. + #size-cells = <0>;
  109. +
  110. + port@0 {
  111. + reg = <0>;
  112. + #address-cells = <1>;
  113. + #size-cells = <0>;
  114. +
  115. + panel_in_edp: endpoint@0 {
  116. + reg = <0>;
  117. + remote-endpoint = <&edp_out_panel>;
  118. + };
  119. + };
  120. + };
  121. + };
  122. +
  123. + /*
  124. + * Use separate nodes for gpio-keys to allow for selective deactivation
  125. + * of wakeup sources via sysfs without disabling the whole key
  126. + */
  127. + gpio-key-lid {
  128. + compatible = "gpio-keys";
  129. + pinctrl-names = "default";
  130. + pinctrl-0 = <&lidbtn_gpio>;
  131. +
  132. + lid {
  133. + debounce-interval = <20>;
  134. + gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_LOW>;
  135. + label = "Lid";
  136. + linux,code = <SW_LID>;
  137. + linux,input-type = <EV_SW>;
  138. + wakeup-event-action = <EV_ACT_DEASSERTED>;
  139. + wakeup-source;
  140. + };
  141. + };
  142. +
  143. + gpio-key-power {
  144. + compatible = "gpio-keys";
  145. + pinctrl-names = "default";
  146. + pinctrl-0 = <&pwrbtn_gpio>;
  147. +
  148. + power {
  149. + debounce-interval = <20>;
  150. + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
  151. + label = "Power";
  152. + linux,code = <KEY_POWER>;
  153. + wakeup-source;
  154. + };
  155. + };
  156. +
  157. +
  158. + leds {
  159. + compatible = "gpio-leds";
  160. + pinctrl-names = "default";
  161. + pinctrl-0 = <&pwrled_gpio &slpled_gpio>;
  162. +
  163. + green-led {
  164. + color = <LED_COLOR_ID_GREEN>;
  165. + default-state = "on";
  166. + function = LED_FUNCTION_POWER;
  167. + gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
  168. + label = "green:disk-activity";
  169. + linux,default-trigger = "mmc2-inverted";
  170. + };
  171. +
  172. + red-led {
  173. + color = <LED_COLOR_ID_RED>;
  174. + default-state = "off";
  175. + function = LED_FUNCTION_STANDBY;
  176. + gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
  177. + label = "red:standby";
  178. + panic-indicator;
  179. + retain-state-suspended;
  180. + };
  181. + };
  182. +
  183. + /* Power sequence for SDIO WiFi module */
  184. + sdio_pwrseq: sdio-pwrseq {
  185. + compatible = "mmc-pwrseq-simple";
  186. + clocks = <&rk808 1>;
  187. + clock-names = "ext_clock";
  188. + pinctrl-names = "default";
  189. + pinctrl-0 = <&wifi_enable_h_gpio>;
  190. + post-power-on-delay-ms = <100>;
  191. + power-off-delay-us = <500000>;
  192. +
  193. + /* WL_REG_ON on module */
  194. + reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
  195. + };
  196. +
  197. + /* first 128k(0xff8d0000~0xff8f0000) for ddr and ATF */
  198. + sram@ff8d0000 {
  199. + compatible = "mmio-sram";
  200. + reg = <0x0 0xff8d0000 0x0 0x20000>; /* 128k */
  201. + };
  202. +
  203. + /* Audio components */
  204. + es8316-sound {
  205. + compatible = "simple-audio-card";
  206. + pinctrl-names = "default";
  207. + pinctrl-0 = <&hp_det_gpio>;
  208. + simple-audio-card,name = "rockchip,es8316-codec";
  209. + simple-audio-card,format = "i2s";
  210. + simple-audio-card,mclk-fs = <256>;
  211. +
  212. + simple-audio-card,widgets =
  213. + "Microphone", "Mic Jack",
  214. + "Headphone", "Headphones",
  215. + "Speaker", "Speaker";
  216. + simple-audio-card,routing =
  217. + "MIC1", "Mic Jack",
  218. + "Headphones", "HPOL",
  219. + "Headphones", "HPOR",
  220. + "Speaker Amplifier INL", "HPOL",
  221. + "Speaker Amplifier INR", "HPOR",
  222. + "Speaker", "Speaker Amplifier OUTL",
  223. + "Speaker", "Speaker Amplifier OUTR";
  224. +
  225. + simple-audio-card,hp-det-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
  226. + simple-audio-card,aux-devs = <&speaker_amp>;
  227. + simple-audio-card,pin-switches = "Speaker";
  228. +
  229. + simple-audio-card,cpu {
  230. + sound-dai = <&i2s1>;
  231. + };
  232. +
  233. + simple-audio-card,codec {
  234. + sound-dai = <&es8316>;
  235. + };
  236. + };
  237. +
  238. + speaker_amp: speaker-amplifier {
  239. + compatible = "simple-audio-amplifier";
  240. + enable-gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>;
  241. + sound-name-prefix = "Speaker Amplifier";
  242. + VCC-supply = <&pa_5v>;
  243. + };
  244. +
  245. + /* Power tree */
  246. + /* Root power source */
  247. + vcc_sysin: vcc-sysin {
  248. + compatible = "regulator-fixed";
  249. + regulator-always-on;
  250. + regulator-boot-on;
  251. + regulator-name = "vcc_sysin";
  252. + };
  253. +
  254. + /* Regulators supplied by vcc_sysin */
  255. + /* LCD backlight supply */
  256. + vcc_12v: vcc-12v {
  257. + compatible = "regulator-fixed";
  258. + regulator-always-on;
  259. + regulator-boot-on;
  260. + regulator-min-microvolt = <12000000>;
  261. + regulator-max-microvolt = <12000000>;
  262. + regulator-name = "vcc_12v";
  263. + vin-supply = <&vcc_sysin>;
  264. +
  265. + regulator-state-mem {
  266. + regulator-off-in-suspend;
  267. + };
  268. + };
  269. +
  270. + /* Main 3.3 V supply */
  271. + vcc3v3_sys: wifi_bat: vcc3v3-sys {
  272. + compatible = "regulator-fixed";
  273. + regulator-always-on;
  274. + regulator-boot-on;
  275. + regulator-min-microvolt = <3300000>;
  276. + regulator-max-microvolt = <3300000>;
  277. + regulator-name = "vcc3v3_sys";
  278. + vin-supply = <&vcc_sysin>;
  279. +
  280. + regulator-state-mem {
  281. + regulator-on-in-suspend;
  282. + };
  283. + };
  284. +
  285. + /* 5 V USB power supply */
  286. + vcc5v0_usb: pa_5v: vcc5v0-usb-regulator {
  287. + compatible = "regulator-fixed";
  288. + enable-active-high;
  289. + gpio = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
  290. + pinctrl-names = "default";
  291. + pinctrl-0 = <&pwr_5v_gpio>;
  292. + regulator-always-on;
  293. + regulator-min-microvolt = <5000000>;
  294. + regulator-max-microvolt = <5000000>;
  295. + regulator-name = "vcc5v0_usb";
  296. + vin-supply = <&vcc_sysin>;
  297. +
  298. + regulator-state-mem {
  299. + regulator-off-in-suspend;
  300. + };
  301. + };
  302. +
  303. + /* RK3399 logic supply */
  304. + vdd_log: vdd-log {
  305. + compatible = "pwm-regulator";
  306. + pwms = <&pwm2 0 25000 1>;
  307. + regulator-always-on;
  308. + regulator-boot-on;
  309. + regulator-min-microvolt = <800000>;
  310. + regulator-max-microvolt = <1400000>;
  311. + regulator-name = "vdd_log";
  312. + vin-supply = <&vcc_sysin>;
  313. +
  314. + regulator-state-mem {
  315. + regulator-on-in-suspend;
  316. + };
  317. + };
  318. +
  319. + /* Regulators supplied by vcc3v3_sys */
  320. + /* 0.9 V supply, always on */
  321. + vcc_0v9: vcc-0v9 {
  322. + compatible = "regulator-fixed";
  323. + regulator-always-on;
  324. + regulator-boot-on;
  325. + regulator-min-microvolt = <900000>;
  326. + regulator-max-microvolt = <900000>;
  327. + regulator-name = "vcc_0v9";
  328. + vin-supply = <&vcc3v3_sys>;
  329. + };
  330. +
  331. + /* S3 1.8 V supply, switched by vcc1v8_s3 */
  332. + vcca1v8_s3: vcc1v8-s3 {
  333. + compatible = "regulator-fixed";
  334. + regulator-always-on;
  335. + regulator-boot-on;
  336. + regulator-min-microvolt = <1800000>;
  337. + regulator-max-microvolt = <1800000>;
  338. + regulator-name = "vcca1v8_s3";
  339. + vin-supply = <&vcc3v3_sys>;
  340. + };
  341. +
  342. + /* micro SD card power */
  343. + vcc3v0_sd: vcc3v0-sd {
  344. + compatible = "regulator-fixed";
  345. + enable-active-high;
  346. + gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
  347. + pinctrl-names = "default";
  348. + pinctrl-0 = <&sdmmc0_pwr_h_gpio>;
  349. + regulator-always-on;
  350. + regulator-min-microvolt = <3000000>;
  351. + regulator-max-microvolt = <3000000>;
  352. + regulator-name = "vcc3v0_sd";
  353. + vin-supply = <&vcc3v3_sys>;
  354. +
  355. + regulator-state-mem {
  356. + regulator-off-in-suspend;
  357. + };
  358. + };
  359. +
  360. + /* LCD panel power, called VCC3V3_S0 in schematic */
  361. + vcc3v3_panel: vcc3v3-panel {
  362. + compatible = "regulator-fixed";
  363. + enable-active-high;
  364. + gpio = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>;
  365. + pinctrl-names = "default";
  366. + pinctrl-0 = <&lcdvcc_en_gpio>;
  367. + regulator-always-on;
  368. + regulator-enable-ramp-delay = <100000>;
  369. + regulator-min-microvolt = <3300000>;
  370. + regulator-max-microvolt = <3300000>;
  371. + regulator-name = "vcc3v3_panel";
  372. + vin-supply = <&vcc3v3_sys>;
  373. +
  374. + regulator-state-mem {
  375. + regulator-off-in-suspend;
  376. + };
  377. + };
  378. +
  379. + /* M.2 adapter power, switched by vcc1v8_s3 */
  380. + vcc3v3_ssd: vcc3v3-ssd {
  381. + compatible = "regulator-fixed";
  382. + regulator-min-microvolt = <3300000>;
  383. + regulator-max-microvolt = <3300000>;
  384. + regulator-name = "vcc3v3_ssd";
  385. + vin-supply = <&vcc3v3_sys>;
  386. + };
  387. +
  388. + /* Regulators supplied by vcc5v0_usb */
  389. + /* USB 3 port power supply regulator */
  390. + vcc5v0_otg: vcc5v0-otg {
  391. + compatible = "regulator-fixed";
  392. + enable-active-high;
  393. + gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
  394. + pinctrl-names = "default";
  395. + pinctrl-0 = <&vcc5v0_host_en_gpio>;
  396. + regulator-always-on;
  397. + regulator-min-microvolt = <5000000>;
  398. + regulator-max-microvolt = <5000000>;
  399. + regulator-name = "vcc5v0_otg";
  400. + vin-supply = <&vcc5v0_usb>;
  401. +
  402. + regulator-state-mem {
  403. + regulator-off-in-suspend;
  404. + };
  405. + };
  406. +
  407. + /* Regulators supplied by vcc5v0_usb */
  408. + /* Type C port power supply regulator */
  409. + vbus_5vout: vbus_typec: vbus-5vout {
  410. + compatible = "regulator-fixed";
  411. + enable-active-high;
  412. + gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
  413. + pinctrl-names = "default";
  414. + pinctrl-0 = <&vcc5v0_typec0_en_gpio>;
  415. + regulator-min-microvolt = <5000000>;
  416. + regulator-max-microvolt = <5000000>;
  417. + regulator-name = "vbus_5vout";
  418. + vin-supply = <&vcc5v0_usb>;
  419. +
  420. + regulator-state-mem {
  421. + regulator-off-in-suspend;
  422. + };
  423. + };
  424. +
  425. + /* Regulators supplied by vcc_1v8 */
  426. + /* Primary 0.9 V LDO */
  427. + vcca0v9_s3: vcca0v9-s3 {
  428. + compatible = "regulator-fixed";
  429. + regulator-min-microvolt = <5000000>;
  430. + regulator-max-microvolt = <5000000>;
  431. + regulator-name = "vcc0v9_s3";
  432. + vin-supply = <&vcc_1v8>;
  433. +
  434. + regulator-state-mem {
  435. + regulator-on-in-suspend;
  436. + };
  437. + };
  438. +
  439. + mains_charger: dc-charger {
  440. + compatible = "gpio-charger";
  441. + charger-type = "mains";
  442. + gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_LOW>;
  443. +
  444. + /* Also triggered by USB charger */
  445. + pinctrl-names = "default";
  446. + pinctrl-0 = <&dc_det_gpio>;
  447. + };
  448. +};
  449. +
  450. +&cluster1_opp {
  451. + opp08 {
  452. + opp-hz = /bits/ 64 <2000000000>;
  453. + opp-microvolt = <1300000>;
  454. + };
  455. +};
  456. +
  457. +&cdn_dp {
  458. + status = "okay";
  459. + extcon = <&fusb0>;
  460. +};
  461. +
  462. +&cpu_b0 {
  463. + cpu-supply = <&vdd_cpu_b>;
  464. +};
  465. +
  466. +&cpu_b1 {
  467. + cpu-supply = <&vdd_cpu_b>;
  468. +};
  469. +
  470. +&cpu_l0 {
  471. + cpu-supply = <&vdd_cpu_l>;
  472. +};
  473. +
  474. +&cpu_l1 {
  475. + cpu-supply = <&vdd_cpu_l>;
  476. +};
  477. +
  478. +&cpu_l2 {
  479. + cpu-supply = <&vdd_cpu_l>;
  480. +};
  481. +
  482. +&cpu_l3 {
  483. + cpu-supply = <&vdd_cpu_l>;
  484. +};
  485. +
  486. +&edp {
  487. + force-hpd;
  488. + pinctrl-names = "default";
  489. + pinctrl-0 = <&edp_hpd>;
  490. + status = "okay";
  491. +
  492. + ports {
  493. + edp_out: port@1 {
  494. + reg = <1>;
  495. + #address-cells = <1>;
  496. + #size-cells = <0>;
  497. +
  498. + edp_out_panel: endpoint@0 {
  499. + reg = <0>;
  500. + remote-endpoint = <&panel_in_edp>;
  501. + };
  502. + };
  503. + };
  504. +};
  505. +
  506. +&emmc_phy {
  507. + status = "okay";
  508. +};
  509. +
  510. +&gpu {
  511. + mali-supply = <&vdd_gpu>;
  512. + status = "okay";
  513. +};
  514. +
  515. +&hdmi_sound {
  516. + status = "okay";
  517. +};
  518. +
  519. +&i2c0 {
  520. + clock-frequency = <400000>;
  521. + i2c-scl-falling-time-ns = <4>;
  522. + i2c-scl-rising-time-ns = <168>;
  523. + status = "okay";
  524. +
  525. + rk808: pmic@1b {
  526. + compatible = "rockchip,rk808";
  527. + reg = <0x1b>;
  528. + #clock-cells = <1>;
  529. + clock-output-names = "xin32k", "rk808-clkout2";
  530. + interrupt-parent = <&gpio3>;
  531. + interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
  532. + pinctrl-names = "default";
  533. + pinctrl-0 = <&pmic_int_l_gpio>;
  534. + rockchip,system-power-controller;
  535. + wakeup-source;
  536. +
  537. + vcc1-supply = <&vcc_sysin>;
  538. + vcc2-supply = <&vcc_sysin>;
  539. + vcc3-supply = <&vcc_sysin>;
  540. + vcc4-supply = <&vcc_sysin>;
  541. + vcc6-supply = <&vcc_sysin>;
  542. + vcc7-supply = <&vcc_sysin>;
  543. + vcc8-supply = <&vcc3v3_sys>;
  544. + vcc9-supply = <&vcc_sysin>;
  545. + vcc10-supply = <&vcc_sysin>;
  546. + vcc11-supply = <&vcc_sysin>;
  547. + vcc12-supply = <&vcc3v3_sys>;
  548. + vcc13-supply = <&vcc_sysin>;
  549. + vcc14-supply = <&vcc_sysin>;
  550. +
  551. + regulators {
  552. + /* rk3399 center logic supply */
  553. + vdd_center: DCDC_REG1 {
  554. + regulator-always-on;
  555. + regulator-boot-on;
  556. + regulator-min-microvolt = <750000>;
  557. + regulator-max-microvolt = <1350000>;
  558. + regulator-name = "vdd_center";
  559. + regulator-ramp-delay = <6001>;
  560. +
  561. + regulator-state-mem {
  562. + regulator-off-in-suspend;
  563. + };
  564. + };
  565. +
  566. + vdd_cpu_l: DCDC_REG2 {
  567. + regulator-always-on;
  568. + regulator-boot-on;
  569. + regulator-min-microvolt = <750000>;
  570. + regulator-max-microvolt = <1350000>;
  571. + regulator-name = "vdd_cpu_l";
  572. + regulator-ramp-delay = <6001>;
  573. +
  574. + regulator-state-mem {
  575. + regulator-off-in-suspend;
  576. + };
  577. + };
  578. +
  579. + vcc_ddr: DCDC_REG3 {
  580. + regulator-always-on;
  581. + regulator-boot-on;
  582. + regulator-name = "vcc_ddr";
  583. +
  584. + regulator-state-mem {
  585. + regulator-on-in-suspend;
  586. + };
  587. + };
  588. +
  589. + vcc_1v8: vcc_wl: DCDC_REG4 {
  590. + regulator-always-on;
  591. + regulator-boot-on;
  592. + regulator-min-microvolt = <1800000>;
  593. + regulator-max-microvolt = <1800000>;
  594. + regulator-name = "vcc_1v8";
  595. +
  596. + regulator-state-mem {
  597. + regulator-on-in-suspend;
  598. + regulator-suspend-microvolt = <1800000>;
  599. + };
  600. + };
  601. +
  602. + /* not used */
  603. + LDO_REG1 {
  604. + };
  605. +
  606. + /* not used */
  607. + LDO_REG2 {
  608. + };
  609. +
  610. + vcc1v8_pmupll: LDO_REG3 {
  611. + regulator-always-on;
  612. + regulator-boot-on;
  613. + regulator-min-microvolt = <1800000>;
  614. + regulator-max-microvolt = <1800000>;
  615. + regulator-name = "vcc1v8_pmupll";
  616. +
  617. + regulator-state-mem {
  618. + regulator-on-in-suspend;
  619. + regulator-suspend-microvolt = <1800000>;
  620. + };
  621. + };
  622. +
  623. + vcc_sdio: LDO_REG4 {
  624. + regulator-always-on;
  625. + regulator-boot-on;
  626. + regulator-min-microvolt = <1800000>;
  627. + regulator-max-microvolt = <3000000>;
  628. + regulator-name = "vcc_sdio";
  629. +
  630. + regulator-state-mem {
  631. + regulator-on-in-suspend;
  632. + regulator-suspend-microvolt = <3000000>;
  633. + };
  634. + };
  635. +
  636. + vcca3v0_codec: LDO_REG5 {
  637. + regulator-always-on;
  638. + regulator-boot-on;
  639. + regulator-min-microvolt = <3000000>;
  640. + regulator-max-microvolt = <3000000>;
  641. + regulator-name = "vcca3v0_codec";
  642. +
  643. + regulator-state-mem {
  644. + regulator-off-in-suspend;
  645. + };
  646. + };
  647. +
  648. + vcc_1v5: LDO_REG6 {
  649. + regulator-always-on;
  650. + regulator-boot-on;
  651. + regulator-min-microvolt = <1500000>;
  652. + regulator-max-microvolt = <1500000>;
  653. + regulator-name = "vcc_1v5";
  654. +
  655. + regulator-state-mem {
  656. + regulator-on-in-suspend;
  657. + regulator-suspend-microvolt = <1500000>;
  658. + };
  659. + };
  660. +
  661. + vcca1v8_codec: LDO_REG7 {
  662. + regulator-always-on;
  663. + regulator-boot-on;
  664. + regulator-min-microvolt = <1800000>;
  665. + regulator-max-microvolt = <1800000>;
  666. + regulator-name = "vcca1v8_codec";
  667. +
  668. + regulator-state-mem {
  669. + regulator-off-in-suspend;
  670. + };
  671. + };
  672. +
  673. + vcc_3v0: LDO_REG8 {
  674. + regulator-always-on;
  675. + regulator-boot-on;
  676. + regulator-min-microvolt = <3000000>;
  677. + regulator-max-microvolt = <3000000>;
  678. + regulator-name = "vcc_3v0";
  679. +
  680. + regulator-state-mem {
  681. + regulator-on-in-suspend;
  682. + regulator-suspend-microvolt = <3000000>;
  683. + };
  684. + };
  685. +
  686. + vcc3v3_s3: SWITCH_REG1 {
  687. + regulator-always-on;
  688. + regulator-boot-on;
  689. + regulator-name = "vcc3v3_s3";
  690. +
  691. + regulator-state-mem {
  692. + regulator-off-in-suspend;
  693. + };
  694. + };
  695. +
  696. + vcc3v3_s0: SWITCH_REG2 {
  697. + regulator-always-on;
  698. + regulator-boot-on;
  699. + regulator-name = "vcc3v3_s0";
  700. +
  701. + regulator-state-mem {
  702. + regulator-off-in-suspend;
  703. + };
  704. + };
  705. + };
  706. + };
  707. +
  708. + vdd_cpu_b: regulator@40 {
  709. + compatible = "silergy,syr827";
  710. + reg = <0x40>;
  711. + fcs,suspend-voltage-selector = <1>;
  712. + pinctrl-names = "default";
  713. + pinctrl-0 = <&vsel1_gpio>;
  714. + regulator-always-on;
  715. + regulator-boot-on;
  716. + regulator-compatible = "fan53555-reg";
  717. + regulator-min-microvolt = <712500>;
  718. + regulator-max-microvolt = <1500000>;
  719. + regulator-name = "vdd_cpu_b";
  720. + regulator-ramp-delay = <1000>;
  721. + vin-supply = <&vcc_1v8>;
  722. +
  723. + regulator-state-mem {
  724. + regulator-off-in-suspend;
  725. + };
  726. + };
  727. +
  728. + vdd_gpu: regulator@41 {
  729. + compatible = "silergy,syr828";
  730. + reg = <0x41>;
  731. + fcs,suspend-voltage-selector = <1>;
  732. + pinctrl-names = "default";
  733. + pinctrl-0 = <&vsel2_gpio>;
  734. + regulator-always-on;
  735. + regulator-boot-on;
  736. + regulator-compatible = "fan53555-reg";
  737. + regulator-min-microvolt = <712500>;
  738. + regulator-max-microvolt = <1500000>;
  739. + regulator-name = "vdd_gpu";
  740. + regulator-ramp-delay = <1000>;
  741. + vin-supply = <&vcc_1v8>;
  742. +
  743. + regulator-state-mem {
  744. + regulator-off-in-suspend;
  745. + };
  746. + };
  747. +};
  748. +
  749. +&i2c1 {
  750. + clock-frequency = <100000>;
  751. + i2c-scl-falling-time-ns = <4>;
  752. + i2c-scl-rising-time-ns = <168>;
  753. + status = "okay";
  754. +
  755. + es8316: es8316@11 {
  756. + compatible = "everest,es8316";
  757. + reg = <0x11>;
  758. + clocks = <&cru SCLK_I2S_8CH_OUT>;
  759. + clock-names = "mclk";
  760. + #sound-dai-cells = <0>;
  761. + };
  762. +};
  763. +
  764. +&i2c3 {
  765. + i2c-scl-falling-time-ns = <15>;
  766. + i2c-scl-rising-time-ns = <450>;
  767. + status = "okay";
  768. +};
  769. +
  770. +&i2c4 {
  771. + i2c-scl-falling-time-ns = <20>;
  772. + i2c-scl-rising-time-ns = <600>;
  773. + status = "okay";
  774. +
  775. + fusb0: fusb30x@22 {
  776. + compatible = "fcs,fusb302";
  777. + reg = <0x22>;
  778. + fcs,int_n = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
  779. + pinctrl-names = "default";
  780. + pinctrl-0 = <&fusb0_int_gpio>;
  781. + vbus-supply = <&vbus_typec>;
  782. +
  783. + connector {
  784. + compatible = "usb-c-connector";
  785. + data-role = "host";
  786. + label = "USB-C";
  787. + op-sink-microwatt = <1000000>;
  788. + power-role = "dual";
  789. + sink-pdos =
  790. + <PDO_FIXED(5000, 2500, PDO_FIXED_USB_COMM)>;
  791. + source-pdos =
  792. + <PDO_FIXED(5000, 1400, PDO_FIXED_USB_COMM)>;
  793. + try-power-role = "sink";
  794. +
  795. + extcon-cables = <1 2 5 6 9 10 12 44>;
  796. + typec-altmodes = <0xff01 1 0x001c0000 1>;
  797. +
  798. + ports {
  799. + #address-cells = <1>;
  800. + #size-cells = <0>;
  801. +
  802. + port@0 {
  803. + reg = <0>;
  804. +
  805. + usbc_hs: endpoint {
  806. + remote-endpoint =
  807. + <&u2phy0_typec_hs>;
  808. + };
  809. + };
  810. +
  811. + port@1 {
  812. + reg = <1>;
  813. +
  814. + usbc_ss: endpoint {
  815. + remote-endpoint =
  816. + <&tcphy0_typec_ss>;
  817. + };
  818. + };
  819. +
  820. + port@2 {
  821. + reg = <2>;
  822. +
  823. + usbc_dp: endpoint {
  824. + remote-endpoint =
  825. + <&tcphy0_typec_dp>;
  826. + };
  827. + };
  828. + };
  829. + };
  830. + };
  831. +
  832. + cw2015@62 {
  833. + compatible = "cellwise,cw2015";
  834. + reg = <0x62>;
  835. + cellwise,battery-profile = /bits/ 8 <
  836. + 0x17 0x67 0x80 0x73 0x6E 0x6C 0x6B 0x63
  837. + 0x77 0x51 0x5C 0x58 0x50 0x4C 0x48 0x36
  838. + 0x15 0x0C 0x0C 0x19 0x5B 0x7D 0x6F 0x69
  839. + 0x69 0x5B 0x0C 0x29 0x20 0x40 0x52 0x59
  840. + 0x57 0x56 0x54 0x4F 0x3B 0x1F 0x7F 0x17
  841. + 0x06 0x1A 0x30 0x5A 0x85 0x93 0x96 0x2D
  842. + 0x48 0x77 0x9C 0xB3 0x80 0x52 0x94 0xCB
  843. + 0x2F 0x00 0x64 0xA5 0xB5 0x11 0xF0 0x11
  844. + >;
  845. + cellwise,monitor-interval-ms = <5000>;
  846. + monitored-battery = <&bat>;
  847. + power-supplies = <&mains_charger>, <&fusb0>;
  848. + };
  849. +};
  850. +
  851. +&i2s1 {
  852. + #sound-dai-cells = <0>;
  853. + pinctrl-names = "default";
  854. + pinctrl-0 = <&i2s_8ch_mclk_gpio>, <&i2s1_2ch_bus>;
  855. + rockchip,capture-channels = <8>;
  856. + rockchip,playback-channels = <8>;
  857. + status = "okay";
  858. +};
  859. +
  860. +&io_domains {
  861. + audio-supply = <&vcc_3v0>;
  862. + gpio1830-supply = <&vcc_3v0>;
  863. + sdmmc-supply = <&vcc_sdio>;
  864. + status = "okay";
  865. +};
  866. +
  867. +&pcie_phy {
  868. + status = "okay";
  869. +};
  870. +
  871. +&pcie0 {
  872. + bus-scan-delay-ms = <1000>;
  873. + ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>;
  874. + max-link-speed = <2>;
  875. + num-lanes = <4>;
  876. + pinctrl-names = "default";
  877. + pinctrl-0 = <&pcie_clkreqn_cpm>;
  878. + vpcie0v9-supply = <&vcca0v9_s3>;
  879. + vpcie1v8-supply = <&vcca1v8_s3>;
  880. + vpcie3v3-supply = <&vcc3v3_ssd>;
  881. + status = "okay";
  882. +};
  883. +
  884. +&pinctrl {
  885. + buttons {
  886. + lidbtn_gpio: lidbtn-gpio {
  887. + rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
  888. + };
  889. +
  890. + pwrbtn_gpio: pwrbtn-gpio {
  891. + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
  892. + };
  893. + };
  894. +
  895. + dc-charger {
  896. + dc_det_gpio: dc-det-gpio {
  897. + rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
  898. + };
  899. + };
  900. +
  901. + es8316 {
  902. + hp_det_gpio: hp-det-gpio {
  903. + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
  904. + };
  905. + };
  906. +
  907. + fusb302x {
  908. + fusb0_int_gpio: fusb0-int-gpio {
  909. + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
  910. + };
  911. + };
  912. +
  913. + i2s1 {
  914. + i2s_8ch_mclk_gpio: i2s-8ch-mclk-gpio {
  915. + rockchip,pins = <4 RK_PA0 1 &pcfg_pull_none>;
  916. + };
  917. + };
  918. +
  919. + lcd-panel {
  920. + lcd_panel_reset_gpio: lcd-panel-reset-gpio {
  921. + rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>;
  922. + };
  923. +
  924. + lcdvcc_en_gpio: lcdvcc-en-gpio {
  925. + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
  926. + };
  927. +
  928. + panel_en_gpio: panel-en-gpio {
  929. + rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
  930. + };
  931. + };
  932. +
  933. + leds {
  934. + pwrled_gpio: pwrled_gpio {
  935. + rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
  936. + };
  937. +
  938. + slpled_gpio: slpled_gpio {
  939. + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
  940. + };
  941. + };
  942. +
  943. + pmic {
  944. + pmic_int_l_gpio: pmic-int-l-gpio {
  945. + rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
  946. + };
  947. +
  948. + vsel1_gpio: vsel1-gpio {
  949. + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
  950. + };
  951. +
  952. + vsel2_gpio: vsel2-gpio {
  953. + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
  954. + };
  955. + };
  956. +
  957. + sdcard {
  958. + sdmmc0_pwr_h_gpio: sdmmc0-pwr-h-gpio {
  959. + rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
  960. + };
  961. +
  962. + };
  963. +
  964. + sdio-pwrseq {
  965. + wifi_enable_h_gpio: wifi-enable-h-gpio {
  966. + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
  967. + };
  968. + };
  969. +
  970. + usb-typec {
  971. + vcc5v0_typec0_en_gpio: vcc5v0-typec0-en-gpio {
  972. + rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
  973. + };
  974. + };
  975. +
  976. + usb2 {
  977. + pwr_5v_gpio: pwr-5v-gpio {
  978. + rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
  979. + };
  980. +
  981. + vcc5v0_host_en_gpio: vcc5v0-host-en-gpio {
  982. + rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
  983. + };
  984. + };
  985. +
  986. + wireless-bluetooth {
  987. + bt_host_wake_gpio: bt-host-wake-gpio {
  988. + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
  989. + };
  990. +
  991. + bt_reset_gpio: bt-reset-gpio {
  992. + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
  993. + };
  994. +
  995. + bt_wake_gpio: bt-wake-gpio {
  996. + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
  997. + };
  998. + };
  999. +};
  1000. +
  1001. +&pmu_io_domains {
  1002. + pmu1830-supply = <&vcc_3v0>;
  1003. + status = "okay";
  1004. +};
  1005. +
  1006. +&pwm0 {
  1007. + status = "okay";
  1008. +};
  1009. +
  1010. +&pwm2 {
  1011. + status = "okay";
  1012. +};
  1013. +
  1014. +&rockchip_suspend {
  1015. + status = "okay";
  1016. + rockchip,sleep-debug-en = <1>;
  1017. + rockchip,sleep-mode-config = <
  1018. + (0
  1019. + | RKPM_SLP_ARMPD
  1020. + | RKPM_SLP_PERILPPD
  1021. + | RKPM_SLP_DDR_RET
  1022. + | RKPM_SLP_PLLPD
  1023. + | RKPM_SLP_CENTER_PD
  1024. + | RKPM_SLP_AP_PWROFF
  1025. + )
  1026. + >;
  1027. + rockchip,pwm-regulator-config = <
  1028. + (0
  1029. + | PWM2_REGULATOR_EN
  1030. + )
  1031. + >;
  1032. + rockchip,power-ctrl =
  1033. + <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>,
  1034. + <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>;
  1035. +};
  1036. +
  1037. +&saradc {
  1038. + vref-supply = <&vcca1v8_s3>;
  1039. + status = "okay";
  1040. +};
  1041. +
  1042. +&sdmmc {
  1043. + bus-width = <4>;
  1044. + cap-mmc-highspeed;
  1045. + cap-sd-highspeed;
  1046. + cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
  1047. + disable-wp;
  1048. + pinctrl-names = "default";
  1049. + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
  1050. + sd-uhs-sdr104;
  1051. + vmmc-supply = <&vcc3v0_sd>;
  1052. + vqmmc-supply = <&vcc_sdio>;
  1053. + status = "okay";
  1054. +};
  1055. +
  1056. +&sdio0 {
  1057. + bus-width = <4>;
  1058. + cap-sd-highspeed;
  1059. + cap-sdio-irq;
  1060. + keep-power-in-suspend;
  1061. + mmc-pwrseq = <&sdio_pwrseq>;
  1062. + non-removable;
  1063. + pinctrl-names = "default";
  1064. + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
  1065. + sd-uhs-sdr104;
  1066. + status = "okay";
  1067. +};
  1068. +
  1069. +&sdhci {
  1070. + bus-width = <8>;
  1071. + mmc-hs200-1_8v;
  1072. + non-removable;
  1073. + status = "okay";
  1074. +};
  1075. +
  1076. +&spi1 {
  1077. + max-freq = <10000000>;
  1078. + status = "okay";
  1079. +
  1080. + spiflash: flash@0 {
  1081. + compatible = "jedec,spi-nor";
  1082. + reg = <0>;
  1083. + m25p,fast-read;
  1084. + spi-max-frequency = <10000000>;
  1085. + };
  1086. +};
  1087. +
  1088. +&tcphy0 {
  1089. + extcon = <&fusb0>;
  1090. + status = "okay";
  1091. +};
  1092. +
  1093. +&tcphy0_dp {
  1094. + port {
  1095. + tcphy0_typec_dp: endpoint {
  1096. + remote-endpoint = <&usbc_dp>;
  1097. + };
  1098. + };
  1099. +};
  1100. +
  1101. +&tcphy0_usb3 {
  1102. + port {
  1103. + tcphy0_typec_ss: endpoint {
  1104. + remote-endpoint = <&usbc_ss>;
  1105. + };
  1106. + };
  1107. +};
  1108. +
  1109. +&tcphy1 {
  1110. + status = "okay";
  1111. +};
  1112. +
  1113. +&tsadc {
  1114. + /* tshut mode 0:CRU 1:GPIO */
  1115. + rockchip,hw-tshut-mode = <1>;
  1116. + /* tshut polarity 0:LOW 1:HIGH */
  1117. + rockchip,hw-tshut-polarity = <1>;
  1118. + status = "okay";
  1119. +};
  1120. +
  1121. +&u2phy0 {
  1122. + status = "okay";
  1123. +
  1124. + u2phy0_otg: otg-port {
  1125. + status = "okay";
  1126. + };
  1127. +
  1128. + u2phy0_host: host-port {
  1129. + phy-supply = <&vcc5v0_otg>;
  1130. + status = "okay";
  1131. + };
  1132. +
  1133. + port {
  1134. + u2phy0_typec_hs: endpoint {
  1135. + remote-endpoint = <&usbc_hs>;
  1136. + };
  1137. + };
  1138. +};
  1139. +
  1140. +&u2phy1 {
  1141. + status = "okay";
  1142. +
  1143. + u2phy1_otg: otg-port {
  1144. + status = "okay";
  1145. + };
  1146. +
  1147. + u2phy1_host: host-port {
  1148. + phy-supply = <&vcc5v0_otg>;
  1149. + status = "okay";
  1150. + };
  1151. +};
  1152. +
  1153. +&uart0 {
  1154. + pinctrl-names = "default";
  1155. + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
  1156. + uart-has-rtscts;
  1157. + status = "okay";
  1158. +
  1159. + bluetooth {
  1160. + compatible = "brcm,bcm4345c5";
  1161. + clocks = <&rk808 1>;
  1162. + clock-names = "lpo";
  1163. + device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
  1164. + host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
  1165. + max-speed = <1500000>;
  1166. + pinctrl-names = "default";
  1167. + pinctrl-0 = <&bt_host_wake_gpio &bt_wake_gpio &bt_reset_gpio>;
  1168. + shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
  1169. + vbat-supply = <&wifi_bat>;
  1170. + vddio-supply = <&vcc_wl>;
  1171. + };
  1172. +};
  1173. +
  1174. +&uart2 {
  1175. + status = "okay";
  1176. +};
  1177. +
  1178. +&usb_host0_ehci {
  1179. + status = "okay";
  1180. +};
  1181. +
  1182. +&usb_host0_ohci {
  1183. + status = "okay";
  1184. +};
  1185. +
  1186. +&usb_host1_ehci {
  1187. + status = "okay";
  1188. +};
  1189. +
  1190. +&usb_host1_ohci {
  1191. + status = "okay";
  1192. +};
  1193. +
  1194. +&usbdrd3_0 {
  1195. + status = "okay";
  1196. +};
  1197. +
  1198. +&usbdrd_dwc3_0 {
  1199. + dr_mode = "host";
  1200. + status = "okay";
  1201. +};
  1202. +
  1203. +&usbdrd3_1 {
  1204. + status = "okay";
  1205. +};
  1206. +
  1207. +&usbdrd_dwc3_1 {
  1208. + dr_mode = "host";
  1209. + status = "okay";
  1210. +};
  1211. +
  1212. +&vopb {
  1213. + status = "okay";
  1214. +};
  1215. +
  1216. +&vopb_mmu {
  1217. + status = "okay";
  1218. +};
  1219. +
  1220. +&vopl {
  1221. + status = "okay";
  1222. +};
  1223. +
  1224. +&vopl_mmu {
  1225. + status = "okay";
  1226. +};
  1227. diff -uNr '--exclude=.git' linux-5.6-rc7/arch/arm64/configs/pinebook_pro_defconfig linux-pinebook-pro_v5.6/arch/arm64/configs/pinebook_pro_defconfig
  1228. --- linux-5.6-rc7/arch/arm64/configs/pinebook_pro_defconfig 1969-12-31 16:00:00.000000000 -0800
  1229. +++ linux-pinebook-pro_v5.6/arch/arm64/configs/pinebook_pro_defconfig 2020-03-23 07:26:33.000000000 -0700
  1230. @@ -0,0 +1,3009 @@
  1231. +CONFIG_LOCALVERSION="-MANJARO-ARM"
  1232. +# CONFIG_LOCALVERSION_AUTO is not set
  1233. +CONFIG_SYSVIPC=y
  1234. +CONFIG_POSIX_MQUEUE=y
  1235. +CONFIG_GENERIC_IRQ_DEBUGFS=y
  1236. +CONFIG_NO_HZ=y
  1237. +CONFIG_HIGH_RES_TIMERS=y
  1238. +CONFIG_PREEMPT_VOLUNTARY=y
  1239. +CONFIG_IRQ_TIME_ACCOUNTING=y
  1240. +CONFIG_BSD_PROCESS_ACCT=y
  1241. +CONFIG_BSD_PROCESS_ACCT_V3=y
  1242. +CONFIG_TASK_XACCT=y
  1243. +CONFIG_TASK_IO_ACCOUNTING=y
  1244. +CONFIG_IKCONFIG=y
  1245. +CONFIG_IKCONFIG_PROC=y
  1246. +CONFIG_LOG_BUF_SHIFT=23
  1247. +CONFIG_LOG_CPU_MAX_BUF_SHIFT=14
  1248. +CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=15
  1249. +CONFIG_MEMCG=y
  1250. +CONFIG_MEMCG_SWAP=y
  1251. +CONFIG_BLK_CGROUP=y
  1252. +CONFIG_CFS_BANDWIDTH=y
  1253. +CONFIG_CGROUP_PIDS=y
  1254. +CONFIG_CGROUP_RDMA=y
  1255. +CONFIG_CGROUP_FREEZER=y
  1256. +CONFIG_CGROUP_HUGETLB=y
  1257. +CONFIG_CPUSETS=y
  1258. +CONFIG_CGROUP_DEVICE=y
  1259. +CONFIG_CGROUP_CPUACCT=y
  1260. +CONFIG_CGROUP_PERF=y
  1261. +CONFIG_CGROUP_BPF=y
  1262. +CONFIG_NAMESPACES=y
  1263. +CONFIG_USER_NS=y
  1264. +CONFIG_CHECKPOINT_RESTORE=y
  1265. +CONFIG_SCHED_AUTOGROUP=y
  1266. +CONFIG_BLK_DEV_INITRD=y
  1267. +CONFIG_EXPERT=y
  1268. +CONFIG_KALLSYMS_ALL=y
  1269. +CONFIG_BPF_SYSCALL=y
  1270. +# CONFIG_COMPAT_BRK is not set
  1271. +CONFIG_SLAB_FREELIST_RANDOM=y
  1272. +CONFIG_PROFILING=y
  1273. +CONFIG_ARCH_ROCKCHIP=y
  1274. +CONFIG_ARM64_VA_BITS_48=y
  1275. +CONFIG_SCHED_MC=y
  1276. +CONFIG_SCHED_SMT=y
  1277. +CONFIG_NR_CPUS=8
  1278. +CONFIG_HZ_100=y
  1279. +CONFIG_SECCOMP=y
  1280. +CONFIG_PARAVIRT_TIME_ACCOUNTING=y
  1281. +CONFIG_KEXEC=y
  1282. +CONFIG_KEXEC_FILE=y
  1283. +CONFIG_COMPAT=y
  1284. +CONFIG_ARM64_ACPI_PARKING_PROTOCOL=y
  1285. +CONFIG_CMDLINE="console=ttyAMA0"
  1286. +CONFIG_HIBERNATION=y
  1287. +CONFIG_PM_DEBUG=y
  1288. +CONFIG_PM_TEST_SUSPEND=y
  1289. +CONFIG_ENERGY_MODEL=y
  1290. +CONFIG_CPU_IDLE_GOV_LADDER=y
  1291. +CONFIG_ARM_CPUIDLE=y
  1292. +CONFIG_CPU_FREQ=y
  1293. +CONFIG_CPU_FREQ_STAT=y
  1294. +CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
  1295. +CONFIG_CPU_FREQ_GOV_POWERSAVE=y
  1296. +CONFIG_CPU_FREQ_GOV_USERSPACE=y
  1297. +CONFIG_CPU_FREQ_GOV_ONDEMAND=y
  1298. +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
  1299. +CONFIG_CPUFREQ_DT=y
  1300. +CONFIG_ACPI_CPPC_CPUFREQ=y
  1301. +CONFIG_ARM_SCPI_CPUFREQ=y
  1302. +CONFIG_ARM_SCPI_PROTOCOL=y
  1303. +CONFIG_DMI_SYSFS=y
  1304. +CONFIG_ROCKCHIP_SIP=y
  1305. +CONFIG_EFI_VARS=y
  1306. +CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE=y
  1307. +# CONFIG_EFI_ARMSTUB_DTB_LOADER is not set
  1308. +CONFIG_EFI_BOOTLOADER_CONTROL=y
  1309. +CONFIG_ACPI=y
  1310. +CONFIG_ACPI_EC_DEBUGFS=y
  1311. +CONFIG_ACPI_DOCK=y
  1312. +CONFIG_ACPI_IPMI=m
  1313. +CONFIG_ACPI_PCI_SLOT=y
  1314. +CONFIG_ACPI_HED=y
  1315. +CONFIG_ACPI_CUSTOM_METHOD=y
  1316. +CONFIG_PMIC_OPREGION=y
  1317. +CONFIG_ACPI_CONFIGFS=m
  1318. +CONFIG_VIRTUALIZATION=y
  1319. +CONFIG_KVM=y
  1320. +CONFIG_VHOST_NET=m
  1321. +CONFIG_VHOST_SCSI=m
  1322. +CONFIG_VHOST_VSOCK=m
  1323. +CONFIG_CRYPTO_SHA1_ARM64_CE=y
  1324. +CONFIG_CRYPTO_SHA2_ARM64_CE=y
  1325. +CONFIG_CRYPTO_SHA512_ARM64_CE=y
  1326. +CONFIG_CRYPTO_SHA3_ARM64=y
  1327. +CONFIG_CRYPTO_SM3_ARM64_CE=y
  1328. +CONFIG_CRYPTO_SM4_ARM64_CE=y
  1329. +CONFIG_CRYPTO_GHASH_ARM64_CE=y
  1330. +CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
  1331. +CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
  1332. +CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
  1333. +CONFIG_CRYPTO_CHACHA20_NEON=y
  1334. +CONFIG_CRYPTO_NHPOLY1305_NEON=y
  1335. +CONFIG_CRYPTO_AES_ARM64_BS=y
  1336. +CONFIG_JUMP_LABEL=y
  1337. +CONFIG_MODULES=y
  1338. +CONFIG_MODULE_UNLOAD=y
  1339. +CONFIG_MODULE_COMPRESS=y
  1340. +CONFIG_UNUSED_SYMBOLS=y
  1341. +CONFIG_BLK_DEV_ZONED=y
  1342. +CONFIG_BLK_DEV_THROTTLING=y
  1343. +CONFIG_BLK_CMDLINE_PARSER=y
  1344. +CONFIG_BLK_WBT=y
  1345. +CONFIG_BLK_SED_OPAL=y
  1346. +CONFIG_PARTITION_ADVANCED=y
  1347. +CONFIG_AIX_PARTITION=y
  1348. +CONFIG_OSF_PARTITION=y
  1349. +CONFIG_AMIGA_PARTITION=y
  1350. +CONFIG_MAC_PARTITION=y
  1351. +CONFIG_BSD_DISKLABEL=y
  1352. +CONFIG_MINIX_SUBPARTITION=y
  1353. +CONFIG_SOLARIS_X86_PARTITION=y
  1354. +CONFIG_UNIXWARE_DISKLABEL=y
  1355. +CONFIG_LDM_PARTITION=y
  1356. +CONFIG_SGI_PARTITION=y
  1357. +CONFIG_SUN_PARTITION=y
  1358. +CONFIG_KARMA_PARTITION=y
  1359. +CONFIG_IOSCHED_BFQ=y
  1360. +CONFIG_BFQ_GROUP_IOSCHED=y
  1361. +CONFIG_BINFMT_MISC=y
  1362. +CONFIG_KSM=y
  1363. +CONFIG_CLEANCACHE=y
  1364. +CONFIG_FRONTSWAP=y
  1365. +CONFIG_CMA=y
  1366. +CONFIG_CMA_DEBUGFS=y
  1367. +CONFIG_ZSWAP=y
  1368. +CONFIG_ZBUD=y
  1369. +CONFIG_Z3FOLD=y
  1370. +CONFIG_ZSMALLOC=y
  1371. +CONFIG_NET=y
  1372. +CONFIG_PACKET=y
  1373. +CONFIG_PACKET_DIAG=m
  1374. +CONFIG_UNIX=y
  1375. +CONFIG_UNIX_DIAG=m
  1376. +CONFIG_TLS=m
  1377. +CONFIG_XFRM_USER=y
  1378. +CONFIG_XFRM_SUB_POLICY=y
  1379. +CONFIG_XFRM_STATISTICS=y
  1380. +CONFIG_NET_KEY=m
  1381. +CONFIG_NET_KEY_MIGRATE=y
  1382. +CONFIG_INET=y
  1383. +CONFIG_IP_MULTICAST=y
  1384. +CONFIG_IP_ADVANCED_ROUTER=y
  1385. +CONFIG_IP_FIB_TRIE_STATS=y
  1386. +CONFIG_IP_MULTIPLE_TABLES=y
  1387. +CONFIG_IP_ROUTE_MULTIPATH=y
  1388. +CONFIG_IP_ROUTE_VERBOSE=y
  1389. +CONFIG_NET_IPIP=m
  1390. +CONFIG_NET_IPGRE_DEMUX=m
  1391. +CONFIG_NET_IPGRE=m
  1392. +CONFIG_NET_IPGRE_BROADCAST=y
  1393. +CONFIG_IP_MROUTE=y
  1394. +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
  1395. +CONFIG_IP_PIMSM_V1=y
  1396. +CONFIG_IP_PIMSM_V2=y
  1397. +CONFIG_NET_IPVTI=m
  1398. +CONFIG_NET_FOU_IP_TUNNELS=y
  1399. +CONFIG_INET_AH=m
  1400. +CONFIG_INET_ESP=m
  1401. +CONFIG_INET_IPCOMP=m
  1402. +CONFIG_INET_DIAG=m
  1403. +CONFIG_INET_UDP_DIAG=m
  1404. +CONFIG_INET_RAW_DIAG=m
  1405. +CONFIG_TCP_CONG_ADVANCED=y
  1406. +CONFIG_TCP_CONG_HSTCP=m
  1407. +CONFIG_TCP_CONG_HYBLA=m
  1408. +CONFIG_TCP_CONG_NV=m
  1409. +CONFIG_TCP_CONG_SCALABLE=m
  1410. +CONFIG_TCP_CONG_LP=m
  1411. +CONFIG_TCP_CONG_VENO=m
  1412. +CONFIG_TCP_CONG_YEAH=m
  1413. +CONFIG_TCP_CONG_ILLINOIS=m
  1414. +CONFIG_TCP_CONG_DCTCP=m
  1415. +CONFIG_TCP_CONG_CDG=m
  1416. +CONFIG_TCP_CONG_BBR=m
  1417. +CONFIG_TCP_MD5SIG=y
  1418. +CONFIG_IPV6_ROUTER_PREF=y
  1419. +CONFIG_IPV6_ROUTE_INFO=y
  1420. +CONFIG_IPV6_OPTIMISTIC_DAD=y
  1421. +CONFIG_INET6_AH=m
  1422. +CONFIG_INET6_ESP=m
  1423. +CONFIG_INET6_IPCOMP=m
  1424. +CONFIG_IPV6_MIP6=y
  1425. +CONFIG_IPV6_ILA=m
  1426. +CONFIG_IPV6_VTI=m
  1427. +CONFIG_IPV6_SIT=m
  1428. +CONFIG_IPV6_SIT_6RD=y
  1429. +CONFIG_IPV6_GRE=m
  1430. +CONFIG_IPV6_SUBTREES=y
  1431. +CONFIG_IPV6_MROUTE=y
  1432. +CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
  1433. +CONFIG_IPV6_PIMSM_V2=y
  1434. +CONFIG_IPV6_SEG6_LWTUNNEL=y
  1435. +CONFIG_IPV6_SEG6_HMAC=y
  1436. +CONFIG_NETLABEL=y
  1437. +CONFIG_NETFILTER=y
  1438. +CONFIG_NF_CONNTRACK=m
  1439. +CONFIG_NF_LOG_NETDEV=m
  1440. +CONFIG_NF_CONNTRACK_ZONES=y
  1441. +CONFIG_NF_CONNTRACK_EVENTS=y
  1442. +CONFIG_NF_CONNTRACK_TIMEOUT=y
  1443. +CONFIG_NF_CONNTRACK_TIMESTAMP=y
  1444. +CONFIG_NF_CONNTRACK_AMANDA=m
  1445. +CONFIG_NF_CONNTRACK_FTP=m
  1446. +CONFIG_NF_CONNTRACK_H323=m
  1447. +CONFIG_NF_CONNTRACK_IRC=m
  1448. +CONFIG_NF_CONNTRACK_NETBIOS_NS=m
  1449. +CONFIG_NF_CONNTRACK_SNMP=m
  1450. +CONFIG_NF_CONNTRACK_PPTP=m
  1451. +CONFIG_NF_CONNTRACK_SANE=m
  1452. +CONFIG_NF_CONNTRACK_SIP=m
  1453. +CONFIG_NF_CONNTRACK_TFTP=m
  1454. +CONFIG_NF_CT_NETLINK=m
  1455. +CONFIG_NF_CT_NETLINK_TIMEOUT=m
  1456. +CONFIG_NF_CT_NETLINK_HELPER=m
  1457. +CONFIG_NETFILTER_NETLINK_GLUE_CT=y
  1458. +CONFIG_NF_TABLES=m
  1459. +CONFIG_NF_TABLES_SET=m
  1460. +CONFIG_NF_TABLES_INET=y
  1461. +CONFIG_NF_TABLES_NETDEV=y
  1462. +CONFIG_NFT_NUMGEN=m
  1463. +CONFIG_NFT_CT=m
  1464. +CONFIG_NFT_FLOW_OFFLOAD=m
  1465. +CONFIG_NFT_COUNTER=m
  1466. +CONFIG_NFT_CONNLIMIT=m
  1467. +CONFIG_NFT_LOG=m
  1468. +CONFIG_NFT_LIMIT=m
  1469. +CONFIG_NFT_MASQ=m
  1470. +CONFIG_NFT_REDIR=m
  1471. +CONFIG_NFT_NAT=m
  1472. +CONFIG_NFT_TUNNEL=m
  1473. +CONFIG_NFT_OBJREF=m
  1474. +CONFIG_NFT_QUEUE=m
  1475. +CONFIG_NFT_QUOTA=m
  1476. +CONFIG_NFT_REJECT=m
  1477. +CONFIG_NFT_COMPAT=m
  1478. +CONFIG_NFT_HASH=m
  1479. +CONFIG_NFT_FIB_INET=m
  1480. +CONFIG_NFT_XFRM=m
  1481. +CONFIG_NFT_SOCKET=m
  1482. +CONFIG_NFT_OSF=m
  1483. +CONFIG_NFT_TPROXY=m
  1484. +CONFIG_NFT_DUP_NETDEV=m
  1485. +CONFIG_NFT_FWD_NETDEV=m
  1486. +CONFIG_NFT_FIB_NETDEV=m
  1487. +CONFIG_NF_FLOW_TABLE_INET=m
  1488. +CONFIG_NF_FLOW_TABLE=m
  1489. +CONFIG_NETFILTER_XT_SET=m
  1490. +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
  1491. +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
  1492. +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
  1493. +CONFIG_NETFILTER_XT_TARGET_CT=m
  1494. +CONFIG_NETFILTER_XT_TARGET_DSCP=m
  1495. +CONFIG_NETFILTER_XT_TARGET_HMARK=m
  1496. +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
  1497. +CONFIG_NETFILTER_XT_TARGET_LED=m
  1498. +CONFIG_NETFILTER_XT_TARGET_LOG=m
  1499. +CONFIG_NETFILTER_XT_TARGET_MARK=m
  1500. +CONFIG_NETFILTER_XT_TARGET_NFLOG=m
  1501. +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
  1502. +CONFIG_NETFILTER_XT_TARGET_TEE=m
  1503. +CONFIG_NETFILTER_XT_TARGET_TPROXY=m
  1504. +CONFIG_NETFILTER_XT_TARGET_TRACE=m
  1505. +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
  1506. +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
  1507. +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
  1508. +CONFIG_NETFILTER_XT_MATCH_BPF=m
  1509. +CONFIG_NETFILTER_XT_MATCH_CGROUP=m
  1510. +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
  1511. +CONFIG_NETFILTER_XT_MATCH_COMMENT=m
  1512. +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
  1513. +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
  1514. +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
  1515. +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
  1516. +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
  1517. +CONFIG_NETFILTER_XT_MATCH_CPU=m
  1518. +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
  1519. +CONFIG_NETFILTER_XT_MATCH_DSCP=m
  1520. +CONFIG_NETFILTER_XT_MATCH_ESP=m
  1521. +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
  1522. +CONFIG_NETFILTER_XT_MATCH_HELPER=m
  1523. +CONFIG_NETFILTER_XT_MATCH_IPCOMP=m
  1524. +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
  1525. +CONFIG_NETFILTER_XT_MATCH_IPVS=m
  1526. +CONFIG_NETFILTER_XT_MATCH_LENGTH=m
  1527. +CONFIG_NETFILTER_XT_MATCH_LIMIT=m
  1528. +CONFIG_NETFILTER_XT_MATCH_MAC=m
  1529. +CONFIG_NETFILTER_XT_MATCH_MARK=m
  1530. +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
  1531. +CONFIG_NETFILTER_XT_MATCH_NFACCT=m
  1532. +CONFIG_NETFILTER_XT_MATCH_OSF=m
  1533. +CONFIG_NETFILTER_XT_MATCH_OWNER=m
  1534. +CONFIG_NETFILTER_XT_MATCH_POLICY=m
  1535. +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
  1536. +CONFIG_NETFILTER_XT_MATCH_QUOTA=m
  1537. +CONFIG_NETFILTER_XT_MATCH_RATEEST=m
  1538. +CONFIG_NETFILTER_XT_MATCH_REALM=m
  1539. +CONFIG_NETFILTER_XT_MATCH_RECENT=m
  1540. +CONFIG_NETFILTER_XT_MATCH_SOCKET=m
  1541. +CONFIG_NETFILTER_XT_MATCH_STATE=m
  1542. +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
  1543. +CONFIG_NETFILTER_XT_MATCH_STRING=m
  1544. +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
  1545. +CONFIG_NETFILTER_XT_MATCH_TIME=m
  1546. +CONFIG_NETFILTER_XT_MATCH_U32=m
  1547. +CONFIG_IP_SET=m
  1548. +CONFIG_IP_SET_BITMAP_IP=m
  1549. +CONFIG_IP_SET_BITMAP_IPMAC=m
  1550. +CONFIG_IP_SET_BITMAP_PORT=m
  1551. +CONFIG_IP_SET_HASH_IP=m
  1552. +CONFIG_IP_SET_HASH_IPMARK=m
  1553. +CONFIG_IP_SET_HASH_IPPORT=m
  1554. +CONFIG_IP_SET_HASH_IPPORTIP=m
  1555. +CONFIG_IP_SET_HASH_IPPORTNET=m
  1556. +CONFIG_IP_SET_HASH_IPMAC=m
  1557. +CONFIG_IP_SET_HASH_MAC=m
  1558. +CONFIG_IP_SET_HASH_NETPORTNET=m
  1559. +CONFIG_IP_SET_HASH_NET=m
  1560. +CONFIG_IP_SET_HASH_NETNET=m
  1561. +CONFIG_IP_SET_HASH_NETPORT=m
  1562. +CONFIG_IP_SET_HASH_NETIFACE=m
  1563. +CONFIG_IP_SET_LIST_SET=m
  1564. +CONFIG_IP_VS=m
  1565. +CONFIG_IP_VS_IPV6=y
  1566. +CONFIG_IP_VS_PROTO_TCP=y
  1567. +CONFIG_IP_VS_PROTO_UDP=y
  1568. +CONFIG_IP_VS_PROTO_ESP=y
  1569. +CONFIG_IP_VS_PROTO_AH=y
  1570. +CONFIG_IP_VS_PROTO_SCTP=y
  1571. +CONFIG_IP_VS_RR=m
  1572. +CONFIG_IP_VS_WRR=m
  1573. +CONFIG_IP_VS_LC=m
  1574. +CONFIG_IP_VS_WLC=m
  1575. +CONFIG_IP_VS_FO=m
  1576. +CONFIG_IP_VS_OVF=m
  1577. +CONFIG_IP_VS_LBLC=m
  1578. +CONFIG_IP_VS_LBLCR=m
  1579. +CONFIG_IP_VS_DH=m
  1580. +CONFIG_IP_VS_SH=m
  1581. +CONFIG_IP_VS_MH=m
  1582. +CONFIG_IP_VS_SED=m
  1583. +CONFIG_IP_VS_NQ=m
  1584. +CONFIG_IP_VS_FTP=m
  1585. +CONFIG_IP_VS_PE_SIP=m
  1586. +CONFIG_NFT_DUP_IPV4=m
  1587. +CONFIG_NFT_FIB_IPV4=m
  1588. +CONFIG_NF_TABLES_ARP=y
  1589. +CONFIG_NF_FLOW_TABLE_IPV4=m
  1590. +CONFIG_NF_LOG_ARP=m
  1591. +CONFIG_NF_REJECT_IPV4=y
  1592. +CONFIG_IP_NF_IPTABLES=y
  1593. +CONFIG_IP_NF_MATCH_AH=m
  1594. +CONFIG_IP_NF_MATCH_ECN=m
  1595. +CONFIG_IP_NF_MATCH_RPFILTER=m
  1596. +CONFIG_IP_NF_MATCH_TTL=m
  1597. +CONFIG_IP_NF_FILTER=m
  1598. +CONFIG_IP_NF_TARGET_REJECT=m
  1599. +CONFIG_IP_NF_TARGET_SYNPROXY=m
  1600. +CONFIG_IP_NF_NAT=m
  1601. +CONFIG_IP_NF_TARGET_MASQUERADE=m
  1602. +CONFIG_IP_NF_TARGET_NETMAP=m
  1603. +CONFIG_IP_NF_TARGET_REDIRECT=m
  1604. +CONFIG_IP_NF_MANGLE=m
  1605. +CONFIG_IP_NF_TARGET_CLUSTERIP=m
  1606. +CONFIG_IP_NF_TARGET_ECN=m
  1607. +CONFIG_IP_NF_TARGET_TTL=m
  1608. +CONFIG_IP_NF_RAW=m
  1609. +CONFIG_IP_NF_SECURITY=m
  1610. +CONFIG_IP_NF_ARPTABLES=m
  1611. +CONFIG_IP_NF_ARPFILTER=m
  1612. +CONFIG_IP_NF_ARP_MANGLE=m
  1613. +CONFIG_NFT_DUP_IPV6=m
  1614. +CONFIG_NFT_FIB_IPV6=m
  1615. +CONFIG_NF_FLOW_TABLE_IPV6=m
  1616. +CONFIG_IP6_NF_MATCH_AH=m
  1617. +CONFIG_IP6_NF_MATCH_EUI64=m
  1618. +CONFIG_IP6_NF_MATCH_FRAG=m
  1619. +CONFIG_IP6_NF_MATCH_OPTS=m
  1620. +CONFIG_IP6_NF_MATCH_HL=m
  1621. +CONFIG_IP6_NF_MATCH_IPV6HEADER=m
  1622. +CONFIG_IP6_NF_MATCH_MH=m
  1623. +CONFIG_IP6_NF_MATCH_RPFILTER=m
  1624. +CONFIG_IP6_NF_MATCH_RT=m
  1625. +CONFIG_IP6_NF_MATCH_SRH=m
  1626. +CONFIG_IP6_NF_TARGET_HL=m
  1627. +CONFIG_IP6_NF_FILTER=m
  1628. +CONFIG_IP6_NF_TARGET_REJECT=m
  1629. +CONFIG_IP6_NF_TARGET_SYNPROXY=m
  1630. +CONFIG_IP6_NF_MANGLE=m
  1631. +CONFIG_IP6_NF_RAW=m
  1632. +CONFIG_IP6_NF_SECURITY=m
  1633. +CONFIG_IP6_NF_NAT=m
  1634. +CONFIG_IP6_NF_TARGET_MASQUERADE=m
  1635. +CONFIG_IP6_NF_TARGET_NPT=m
  1636. +CONFIG_NF_TABLES_BRIDGE=m
  1637. +CONFIG_NFT_BRIDGE_REJECT=m
  1638. +CONFIG_NF_LOG_BRIDGE=m
  1639. +CONFIG_BRIDGE_NF_EBTABLES=m
  1640. +CONFIG_BRIDGE_EBT_BROUTE=m
  1641. +CONFIG_BRIDGE_EBT_T_FILTER=m
  1642. +CONFIG_BRIDGE_EBT_T_NAT=m
  1643. +CONFIG_BRIDGE_EBT_802_3=m
  1644. +CONFIG_BRIDGE_EBT_AMONG=m
  1645. +CONFIG_BRIDGE_EBT_ARP=m
  1646. +CONFIG_BRIDGE_EBT_IP=m
  1647. +CONFIG_BRIDGE_EBT_IP6=m
  1648. +CONFIG_BRIDGE_EBT_LIMIT=m
  1649. +CONFIG_BRIDGE_EBT_MARK=m
  1650. +CONFIG_BRIDGE_EBT_PKTTYPE=m
  1651. +CONFIG_BRIDGE_EBT_STP=m
  1652. +CONFIG_BRIDGE_EBT_VLAN=m
  1653. +CONFIG_BRIDGE_EBT_ARPREPLY=m
  1654. +CONFIG_BRIDGE_EBT_DNAT=m
  1655. +CONFIG_BRIDGE_EBT_MARK_T=m
  1656. +CONFIG_BRIDGE_EBT_REDIRECT=m
  1657. +CONFIG_BRIDGE_EBT_SNAT=m
  1658. +CONFIG_BRIDGE_EBT_LOG=m
  1659. +CONFIG_BRIDGE_EBT_NFLOG=m
  1660. +CONFIG_BPFILTER=y
  1661. +CONFIG_IP_DCCP=m
  1662. +CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1=y
  1663. +CONFIG_SCTP_COOKIE_HMAC_MD5=y
  1664. +CONFIG_RDS=m
  1665. +CONFIG_RDS_TCP=m
  1666. +CONFIG_TIPC=m
  1667. +CONFIG_ATM=m
  1668. +CONFIG_ATM_CLIP=m
  1669. +CONFIG_ATM_LANE=m
  1670. +CONFIG_ATM_BR2684=m
  1671. +CONFIG_L2TP=m
  1672. +CONFIG_L2TP_DEBUGFS=m
  1673. +CONFIG_L2TP_V3=y
  1674. +CONFIG_L2TP_IP=m
  1675. +CONFIG_L2TP_ETH=m
  1676. +CONFIG_BRIDGE=m
  1677. +CONFIG_BRIDGE_VLAN_FILTERING=y
  1678. +CONFIG_NET_DSA=m
  1679. +CONFIG_VLAN_8021Q=m
  1680. +CONFIG_VLAN_8021Q_GVRP=y
  1681. +CONFIG_VLAN_8021Q_MVRP=y
  1682. +CONFIG_ATALK=m
  1683. +CONFIG_DEV_APPLETALK=m
  1684. +CONFIG_IPDDP=m
  1685. +CONFIG_IPDDP_ENCAP=y
  1686. +CONFIG_6LOWPAN=m
  1687. +CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m
  1688. +CONFIG_6LOWPAN_GHC_UDP=m
  1689. +CONFIG_6LOWPAN_GHC_ICMPV6=m
  1690. +CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m
  1691. +CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m
  1692. +CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m
  1693. +CONFIG_IEEE802154=m
  1694. +CONFIG_IEEE802154_6LOWPAN=m
  1695. +CONFIG_MAC802154=m
  1696. +CONFIG_NET_SCHED=y
  1697. +CONFIG_NET_SCH_CBQ=m
  1698. +CONFIG_NET_SCH_HTB=m
  1699. +CONFIG_NET_SCH_HFSC=m
  1700. +CONFIG_NET_SCH_ATM=m
  1701. +CONFIG_NET_SCH_PRIO=m
  1702. +CONFIG_NET_SCH_MULTIQ=m
  1703. +CONFIG_NET_SCH_RED=m
  1704. +CONFIG_NET_SCH_SFB=m
  1705. +CONFIG_NET_SCH_SFQ=m
  1706. +CONFIG_NET_SCH_TEQL=m
  1707. +CONFIG_NET_SCH_TBF=m
  1708. +CONFIG_NET_SCH_CBS=m
  1709. +CONFIG_NET_SCH_GRED=m
  1710. +CONFIG_NET_SCH_DSMARK=m
  1711. +CONFIG_NET_SCH_NETEM=m
  1712. +CONFIG_NET_SCH_DRR=m
  1713. +CONFIG_NET_SCH_MQPRIO=m
  1714. +CONFIG_NET_SCH_CHOKE=m
  1715. +CONFIG_NET_SCH_QFQ=m
  1716. +CONFIG_NET_SCH_CODEL=m
  1717. +CONFIG_NET_SCH_FQ_CODEL=y
  1718. +CONFIG_NET_SCH_FQ=m
  1719. +CONFIG_NET_SCH_HHF=m
  1720. +CONFIG_NET_SCH_PIE=m
  1721. +CONFIG_NET_SCH_INGRESS=m
  1722. +CONFIG_NET_SCH_PLUG=m
  1723. +CONFIG_NET_CLS_BASIC=m
  1724. +CONFIG_NET_CLS_TCINDEX=m
  1725. +CONFIG_NET_CLS_ROUTE4=m
  1726. +CONFIG_NET_CLS_FW=m
  1727. +CONFIG_NET_CLS_U32=m
  1728. +CONFIG_CLS_U32_PERF=y
  1729. +CONFIG_CLS_U32_MARK=y
  1730. +CONFIG_NET_CLS_RSVP=m
  1731. +CONFIG_NET_CLS_RSVP6=m
  1732. +CONFIG_NET_CLS_FLOW=m
  1733. +CONFIG_NET_CLS_CGROUP=y
  1734. +CONFIG_NET_CLS_BPF=m
  1735. +CONFIG_NET_CLS_FLOWER=m
  1736. +CONFIG_NET_CLS_MATCHALL=m
  1737. +CONFIG_NET_EMATCH=y
  1738. +CONFIG_NET_EMATCH_CMP=m
  1739. +CONFIG_NET_EMATCH_NBYTE=m
  1740. +CONFIG_NET_EMATCH_U32=m
  1741. +CONFIG_NET_EMATCH_META=m
  1742. +CONFIG_NET_EMATCH_TEXT=m
  1743. +CONFIG_NET_EMATCH_CANID=m
  1744. +CONFIG_NET_EMATCH_IPSET=m
  1745. +CONFIG_NET_EMATCH_IPT=m
  1746. +CONFIG_NET_CLS_ACT=y
  1747. +CONFIG_NET_ACT_POLICE=m
  1748. +CONFIG_NET_ACT_GACT=m
  1749. +CONFIG_GACT_PROB=y
  1750. +CONFIG_NET_ACT_MIRRED=m
  1751. +CONFIG_NET_ACT_SAMPLE=m
  1752. +CONFIG_NET_ACT_IPT=m
  1753. +CONFIG_NET_ACT_NAT=m
  1754. +CONFIG_NET_ACT_PEDIT=m
  1755. +CONFIG_NET_ACT_SIMP=m
  1756. +CONFIG_NET_ACT_SKBEDIT=m
  1757. +CONFIG_NET_ACT_CSUM=m
  1758. +CONFIG_NET_ACT_VLAN=m
  1759. +CONFIG_NET_ACT_BPF=m
  1760. +CONFIG_NET_ACT_CONNMARK=m
  1761. +CONFIG_NET_ACT_SKBMOD=m
  1762. +CONFIG_NET_ACT_IFE=m
  1763. +CONFIG_NET_ACT_TUNNEL_KEY=m
  1764. +CONFIG_NET_IFE_SKBMARK=m
  1765. +CONFIG_NET_IFE_SKBPRIO=m
  1766. +CONFIG_NET_IFE_SKBTCINDEX=m
  1767. +CONFIG_DCB=y
  1768. +CONFIG_BATMAN_ADV=m
  1769. +# CONFIG_BATMAN_ADV_BATMAN_V is not set
  1770. +CONFIG_BATMAN_ADV_NC=y
  1771. +CONFIG_BATMAN_ADV_DEBUGFS=y
  1772. +CONFIG_OPENVSWITCH=m
  1773. +CONFIG_VSOCKETS=m
  1774. +CONFIG_VIRTIO_VSOCKETS=m
  1775. +CONFIG_NETLINK_DIAG=m
  1776. +CONFIG_MPLS_ROUTING=m
  1777. +CONFIG_CGROUP_NET_PRIO=y
  1778. +CONFIG_BPF_JIT=y
  1779. +CONFIG_BPF_STREAM_PARSER=y
  1780. +CONFIG_NET_PKTGEN=m
  1781. +CONFIG_HAMRADIO=y
  1782. +CONFIG_AX25=m
  1783. +CONFIG_NETROM=m
  1784. +CONFIG_ROSE=m
  1785. +CONFIG_MKISS=m
  1786. +CONFIG_6PACK=m
  1787. +CONFIG_BPQETHER=m
  1788. +CONFIG_BAYCOM_SER_FDX=m
  1789. +CONFIG_BAYCOM_SER_HDX=m
  1790. +CONFIG_YAM=m
  1791. +CONFIG_CAN=m
  1792. +CONFIG_CAN_VCAN=m
  1793. +CONFIG_CAN_VXCAN=m
  1794. +CONFIG_CAN_SLCAN=m
  1795. +CONFIG_CAN_C_CAN=m
  1796. +CONFIG_CAN_C_CAN_PLATFORM=m
  1797. +CONFIG_CAN_C_CAN_PCI=m
  1798. +CONFIG_CAN_CC770=m
  1799. +CONFIG_CAN_CC770_PLATFORM=m
  1800. +CONFIG_CAN_M_CAN=m
  1801. +CONFIG_CAN_SJA1000=m
  1802. +CONFIG_CAN_EMS_PCI=m
  1803. +CONFIG_CAN_KVASER_PCI=m
  1804. +CONFIG_CAN_PEAK_PCI=m
  1805. +CONFIG_CAN_PLX_PCI=m
  1806. +CONFIG_CAN_SJA1000_PLATFORM=m
  1807. +CONFIG_CAN_SOFTING=m
  1808. +CONFIG_CAN_8DEV_USB=m
  1809. +CONFIG_CAN_EMS_USB=m
  1810. +CONFIG_CAN_ESD_USB2=m
  1811. +CONFIG_CAN_GS_USB=m
  1812. +CONFIG_CAN_KVASER_USB=m
  1813. +CONFIG_CAN_PEAK_USB=m
  1814. +CONFIG_BT=m
  1815. +CONFIG_BT_RFCOMM=m
  1816. +CONFIG_BT_RFCOMM_TTY=y
  1817. +CONFIG_BT_BNEP=m
  1818. +CONFIG_BT_BNEP_MC_FILTER=y
  1819. +CONFIG_BT_BNEP_PROTO_FILTER=y
  1820. +CONFIG_BT_HIDP=m
  1821. +CONFIG_BT_6LOWPAN=m
  1822. +CONFIG_BT_HCIBTUSB=m
  1823. +CONFIG_BT_HCIBTSDIO=m
  1824. +CONFIG_BT_HCIUART=m
  1825. +CONFIG_BT_HCIUART_BCSP=y
  1826. +CONFIG_BT_HCIUART_ATH3K=y
  1827. +CONFIG_BT_HCIUART_LL=y
  1828. +CONFIG_BT_HCIUART_3WIRE=y
  1829. +CONFIG_BT_HCIUART_INTEL=y
  1830. +CONFIG_BT_HCIUART_BCM=y
  1831. +CONFIG_BT_HCIUART_QCA=y
  1832. +CONFIG_BT_HCIUART_MRVL=y
  1833. +CONFIG_BT_HCIBCM203X=m
  1834. +CONFIG_BT_HCIBPA10X=m
  1835. +CONFIG_BT_HCIBFUSB=m
  1836. +CONFIG_BT_HCIVHCI=m
  1837. +CONFIG_BT_MRVL=m
  1838. +CONFIG_BT_MRVL_SDIO=m
  1839. +CONFIG_BT_ATH3K=m
  1840. +CONFIG_CFG80211=m
  1841. +CONFIG_CFG80211_CERTIFICATION_ONUS=y
  1842. +# CONFIG_CFG80211_REQUIRE_SIGNED_REGDB is not set
  1843. +CONFIG_CFG80211_DEBUGFS=y
  1844. +CONFIG_MAC80211=m
  1845. +CONFIG_MAC80211_MESH=y
  1846. +CONFIG_RFKILL=m
  1847. +CONFIG_RFKILL_INPUT=y
  1848. +CONFIG_RFKILL_GPIO=m
  1849. +CONFIG_NET_9P=m
  1850. +CONFIG_NET_9P_VIRTIO=m
  1851. +CONFIG_NFC=m
  1852. +CONFIG_NFC_DIGITAL=m
  1853. +CONFIG_NFC_NCI=m
  1854. +CONFIG_NFC_HCI=m
  1855. +CONFIG_NFC_SHDLC=y
  1856. +CONFIG_NFC_SIM=m
  1857. +CONFIG_NFC_PORT100=m
  1858. +CONFIG_NFC_PN544_I2C=m
  1859. +CONFIG_NFC_MICROREAD_I2C=m
  1860. +CONFIG_NFC_MRVL_USB=m
  1861. +CONFIG_NFC_ST21NFCA_I2C=m
  1862. +CONFIG_PCI=y
  1863. +CONFIG_PCIEPORTBUS=y
  1864. +CONFIG_HOTPLUG_PCI_PCIE=y
  1865. +CONFIG_PCIEAER_INJECT=m
  1866. +CONFIG_PCIE_ECRC=y
  1867. +CONFIG_PCI_STUB=y
  1868. +CONFIG_PCI_IOV=y
  1869. +CONFIG_PCI_PRI=y
  1870. +CONFIG_PCI_PASID=y
  1871. +CONFIG_HOTPLUG_PCI=y
  1872. +CONFIG_HOTPLUG_PCI_ACPI=y
  1873. +CONFIG_PCI_HOST_GENERIC=y
  1874. +CONFIG_PCI_XGENE=y
  1875. +CONFIG_PCIE_ROCKCHIP_HOST=y
  1876. +CONFIG_PCIE_DW_PLAT_HOST=y
  1877. +CONFIG_PCI_HISI=y
  1878. +CONFIG_DEVTMPFS=y
  1879. +CONFIG_DEVTMPFS_MOUNT=y
  1880. +CONFIG_DEBUG_DEVRES=y
  1881. +CONFIG_SIMPLE_PM_BUS=y
  1882. +CONFIG_VEXPRESS_CONFIG=y
  1883. +CONFIG_CONNECTOR=y
  1884. +CONFIG_MTD=y
  1885. +CONFIG_MTD_OF_PARTS=m
  1886. +CONFIG_MTD_BLOCK=m
  1887. +CONFIG_MTD_CFI=m
  1888. +CONFIG_MTD_CFI_INTELEXT=m
  1889. +CONFIG_MTD_CFI_AMDSTD=m
  1890. +CONFIG_MTD_CFI_STAA=m
  1891. +CONFIG_MTD_PHYSMAP=m
  1892. +CONFIG_MTD_PHYSMAP_OF=y
  1893. +CONFIG_MTD_RAW_NAND=y
  1894. +CONFIG_MTD_SPI_NOR=y
  1895. +CONFIG_MTD_UBI=m
  1896. +CONFIG_BLK_DEV_NULL_BLK=m
  1897. +CONFIG_ZRAM=m
  1898. +CONFIG_BLK_DEV_UMEM=m
  1899. +CONFIG_BLK_DEV_LOOP=m
  1900. +CONFIG_BLK_DEV_LOOP_MIN_COUNT=0
  1901. +CONFIG_BLK_DEV_DRBD=m
  1902. +CONFIG_BLK_DEV_NBD=m
  1903. +CONFIG_BLK_DEV_SKD=m
  1904. +CONFIG_BLK_DEV_SX8=m
  1905. +CONFIG_BLK_DEV_RAM=m
  1906. +CONFIG_BLK_DEV_RAM_SIZE=16384
  1907. +CONFIG_CDROM_PKTCDVD=m
  1908. +CONFIG_ATA_OVER_ETH=m
  1909. +CONFIG_VIRTIO_BLK=m
  1910. +CONFIG_BLK_DEV_RBD=m
  1911. +CONFIG_BLK_DEV_NVME=m
  1912. +CONFIG_NVME_MULTIPATH=y
  1913. +CONFIG_TIFM_7XX1=m
  1914. +CONFIG_ENCLOSURE_SERVICES=m
  1915. +CONFIG_APDS9802ALS=m
  1916. +CONFIG_ISL29003=m
  1917. +CONFIG_ISL29020=m
  1918. +CONFIG_SENSORS_TSL2550=m
  1919. +CONFIG_SENSORS_BH1770=m
  1920. +CONFIG_SENSORS_APDS990X=m
  1921. +CONFIG_SRAM=y
  1922. +CONFIG_EEPROM_AT24=m
  1923. +CONFIG_EEPROM_LEGACY=m
  1924. +CONFIG_EEPROM_MAX6875=m
  1925. +CONFIG_SENSORS_LIS3_I2C=m
  1926. +CONFIG_ECHO=m
  1927. +CONFIG_RAID_ATTRS=m
  1928. +CONFIG_BLK_DEV_SD=y
  1929. +CONFIG_CHR_DEV_ST=m
  1930. +CONFIG_BLK_DEV_SR=y
  1931. +CONFIG_BLK_DEV_SR_VENDOR=y
  1932. +CONFIG_CHR_DEV_SG=y
  1933. +CONFIG_CHR_DEV_SCH=m
  1934. +CONFIG_SCSI_ENCLOSURE=m
  1935. +CONFIG_SCSI_CONSTANTS=y
  1936. +CONFIG_SCSI_LOGGING=y
  1937. +CONFIG_SCSI_SCAN_ASYNC=y
  1938. +CONFIG_SCSI_FC_ATTRS=m
  1939. +CONFIG_SCSI_SAS_ATA=y
  1940. +CONFIG_SCSI_SRP_ATTRS=m
  1941. +CONFIG_ISCSI_TCP=m
  1942. +CONFIG_SCSI_BNX2_ISCSI=m
  1943. +CONFIG_SCSI_BNX2X_FCOE=m
  1944. +CONFIG_BE2ISCSI=m
  1945. +CONFIG_SCSI_HPSA=m
  1946. +CONFIG_SCSI_MVSAS=m
  1947. +# CONFIG_SCSI_MVSAS_DEBUG is not set
  1948. +CONFIG_SCSI_MVSAS_TASKLET=y
  1949. +CONFIG_SCSI_MVUMI=m
  1950. +CONFIG_SCSI_ARCMSR=m
  1951. +CONFIG_SCSI_ESAS2R=m
  1952. +CONFIG_MEGARAID_NEWGEN=y
  1953. +CONFIG_MEGARAID_MM=m
  1954. +CONFIG_MEGARAID_MAILBOX=m
  1955. +CONFIG_MEGARAID_LEGACY=m
  1956. +CONFIG_MEGARAID_SAS=m
  1957. +CONFIG_SCSI_UFSHCD=y
  1958. +CONFIG_SCSI_UFSHCD_PCI=m
  1959. +CONFIG_SCSI_UFSHCD_PLATFORM=y
  1960. +CONFIG_SCSI_HPTIOP=m
  1961. +CONFIG_LIBFC=m
  1962. +CONFIG_LIBFCOE=m
  1963. +CONFIG_FCOE=m
  1964. +CONFIG_SCSI_SNIC=m
  1965. +CONFIG_SCSI_DMX3191D=m
  1966. +CONFIG_SCSI_INITIO=m
  1967. +CONFIG_SCSI_INIA100=m
  1968. +CONFIG_SCSI_STEX=m
  1969. +CONFIG_SCSI_SYM53C8XX_2=m
  1970. +CONFIG_SCSI_IPR=m
  1971. +CONFIG_SCSI_QLOGIC_1280=m
  1972. +CONFIG_SCSI_QLA_FC=m
  1973. +CONFIG_TCM_QLA2XXX=m
  1974. +CONFIG_SCSI_QLA_ISCSI=m
  1975. +CONFIG_SCSI_DC395x=m
  1976. +CONFIG_SCSI_AM53C974=m
  1977. +CONFIG_SCSI_WD719X=m
  1978. +CONFIG_SCSI_DEBUG=m
  1979. +CONFIG_SCSI_PMCRAID=m
  1980. +CONFIG_SCSI_VIRTIO=y
  1981. +CONFIG_SCSI_CHELSIO_FCOE=m
  1982. +CONFIG_SCSI_DH=y
  1983. +CONFIG_SCSI_DH_RDAC=m
  1984. +CONFIG_SCSI_DH_HP_SW=m
  1985. +CONFIG_SCSI_DH_EMC=m
  1986. +CONFIG_SCSI_DH_ALUA=m
  1987. +CONFIG_ATA=y
  1988. +CONFIG_SATA_AHCI=y
  1989. +CONFIG_SATA_AHCI_PLATFORM=y
  1990. +CONFIG_AHCI_XGENE=y
  1991. +CONFIG_SATA_INIC162X=m
  1992. +CONFIG_SATA_ACARD_AHCI=m
  1993. +CONFIG_SATA_SIL24=y
  1994. +CONFIG_PDC_ADMA=m
  1995. +CONFIG_SATA_QSTOR=m
  1996. +CONFIG_SATA_SX4=m
  1997. +CONFIG_ATA_PIIX=y
  1998. +CONFIG_SATA_MV=m
  1999. +CONFIG_SATA_NV=m
  2000. +CONFIG_SATA_PROMISE=m
  2001. +CONFIG_SATA_SIL=m
  2002. +CONFIG_SATA_SIS=m
  2003. +CONFIG_SATA_SVW=m
  2004. +CONFIG_SATA_ULI=m
  2005. +CONFIG_SATA_VIA=m
  2006. +CONFIG_SATA_VITESSE=m
  2007. +CONFIG_PATA_ALI=m
  2008. +CONFIG_PATA_AMD=m
  2009. +CONFIG_PATA_ARTOP=m
  2010. +CONFIG_PATA_ATIIXP=m
  2011. +CONFIG_PATA_ATP867X=m
  2012. +CONFIG_PATA_CMD64X=m
  2013. +CONFIG_PATA_CYPRESS=m
  2014. +CONFIG_PATA_EFAR=m
  2015. +CONFIG_PATA_HPT366=m
  2016. +CONFIG_PATA_HPT37X=m
  2017. +CONFIG_PATA_HPT3X2N=m
  2018. +CONFIG_PATA_HPT3X3=m
  2019. +CONFIG_PATA_IT8213=m
  2020. +CONFIG_PATA_IT821X=m
  2021. +CONFIG_PATA_JMICRON=m
  2022. +CONFIG_PATA_MARVELL=m
  2023. +CONFIG_PATA_NETCELL=m
  2024. +CONFIG_PATA_NINJA32=m
  2025. +CONFIG_PATA_NS87415=m
  2026. +CONFIG_PATA_OLDPIIX=m
  2027. +CONFIG_PATA_OPTIDMA=m
  2028. +CONFIG_PATA_PDC2027X=m
  2029. +CONFIG_PATA_PDC_OLD=m
  2030. +CONFIG_PATA_RDC=m
  2031. +CONFIG_PATA_SCH=m
  2032. +CONFIG_PATA_SERVERWORKS=m
  2033. +CONFIG_PATA_SIL680=m
  2034. +CONFIG_PATA_TOSHIBA=m
  2035. +CONFIG_PATA_TRIFLEX=m
  2036. +CONFIG_PATA_VIA=m
  2037. +CONFIG_PATA_WINBOND=m
  2038. +CONFIG_PATA_CMD640_PCI=m
  2039. +CONFIG_PATA_MPIIX=m
  2040. +CONFIG_PATA_NS87410=m
  2041. +CONFIG_PATA_OPTI=m
  2042. +CONFIG_PATA_PLATFORM=y
  2043. +CONFIG_PATA_OF_PLATFORM=y
  2044. +CONFIG_ATA_GENERIC=m
  2045. +CONFIG_MD=y
  2046. +CONFIG_BLK_DEV_MD=y
  2047. +CONFIG_MD_LINEAR=m
  2048. +CONFIG_MD_MULTIPATH=m
  2049. +CONFIG_MD_FAULTY=m
  2050. +CONFIG_MD_CLUSTER=m
  2051. +CONFIG_BCACHE=m
  2052. +CONFIG_BLK_DEV_DM=y
  2053. +CONFIG_DM_DEBUG=y
  2054. +CONFIG_DM_CRYPT=m
  2055. +CONFIG_DM_SNAPSHOT=y
  2056. +CONFIG_DM_THIN_PROVISIONING=m
  2057. +CONFIG_DM_CACHE=m
  2058. +CONFIG_DM_WRITECACHE=m
  2059. +CONFIG_DM_MIRROR=y
  2060. +CONFIG_DM_LOG_USERSPACE=m
  2061. +CONFIG_DM_RAID=m
  2062. +CONFIG_DM_ZERO=y
  2063. +CONFIG_DM_MULTIPATH=m
  2064. +CONFIG_DM_MULTIPATH_QL=m
  2065. +CONFIG_DM_MULTIPATH_ST=m
  2066. +CONFIG_DM_DELAY=m
  2067. +CONFIG_DM_DUST=m
  2068. +CONFIG_DM_INIT=y
  2069. +CONFIG_DM_UEVENT=y
  2070. +CONFIG_DM_FLAKEY=m
  2071. +CONFIG_DM_VERITY=m
  2072. +CONFIG_DM_VERITY_FEC=y
  2073. +CONFIG_DM_SWITCH=m
  2074. +CONFIG_DM_LOG_WRITES=m
  2075. +CONFIG_DM_INTEGRITY=m
  2076. +CONFIG_DM_ZONED=m
  2077. +CONFIG_TARGET_CORE=m
  2078. +CONFIG_TCM_IBLOCK=m
  2079. +CONFIG_TCM_FILEIO=m
  2080. +CONFIG_TCM_PSCSI=m
  2081. +CONFIG_TCM_USER2=m
  2082. +CONFIG_LOOPBACK_TARGET=m
  2083. +CONFIG_TCM_FC=m
  2084. +CONFIG_ISCSI_TARGET=m
  2085. +CONFIG_FIREWIRE_NOSY=m
  2086. +CONFIG_BONDING=m
  2087. +CONFIG_DUMMY=m
  2088. +CONFIG_WIREGUARD=m
  2089. +CONFIG_EQUALIZER=m
  2090. +CONFIG_NET_FC=y
  2091. +CONFIG_IFB=m
  2092. +CONFIG_NET_TEAM=m
  2093. +CONFIG_NET_TEAM_MODE_BROADCAST=m
  2094. +CONFIG_NET_TEAM_MODE_ROUNDROBIN=m
  2095. +CONFIG_NET_TEAM_MODE_RANDOM=m
  2096. +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m
  2097. +CONFIG_NET_TEAM_MODE_LOADBALANCE=m
  2098. +CONFIG_MACVLAN=m
  2099. +CONFIG_MACVTAP=m
  2100. +CONFIG_IPVLAN=m
  2101. +CONFIG_IPVTAP=m
  2102. +CONFIG_VXLAN=m
  2103. +CONFIG_GENEVE=m
  2104. +CONFIG_NETCONSOLE=m
  2105. +CONFIG_NETCONSOLE_DYNAMIC=y
  2106. +CONFIG_TUN=m
  2107. +CONFIG_VETH=m
  2108. +CONFIG_VIRTIO_NET=m
  2109. +CONFIG_NLMON=m
  2110. +CONFIG_NET_VRF=m
  2111. +# CONFIG_ATM_DRIVERS is not set
  2112. +CONFIG_NET_DSA_BCM_SF2=m
  2113. +CONFIG_NET_DSA_MV88E6060=m
  2114. +CONFIG_NET_DSA_MV88E6XXX=m
  2115. +CONFIG_NET_DSA_MV88E6XXX_PTP=y
  2116. +CONFIG_NET_DSA_QCA8K=m
  2117. +# CONFIG_NET_VENDOR_3COM is not set
  2118. +# CONFIG_NET_VENDOR_ADAPTEC is not set
  2119. +CONFIG_ET131X=m
  2120. +CONFIG_ACENIC=m
  2121. +CONFIG_ALTERA_TSE=m
  2122. +CONFIG_AMD8111_ETH=m
  2123. +CONFIG_PCNET32=m
  2124. +CONFIG_AMD_XGBE=m
  2125. +CONFIG_AQTION=m
  2126. +CONFIG_ATL2=m
  2127. +CONFIG_ATL1=m
  2128. +CONFIG_ATL1E=m
  2129. +CONFIG_ATL1C=m
  2130. +CONFIG_ALX=m
  2131. +# CONFIG_NET_VENDOR_AURORA is not set
  2132. +CONFIG_B44=m
  2133. +CONFIG_BCMGENET=m
  2134. +CONFIG_TIGON3=m
  2135. +CONFIG_BNX2X=m
  2136. +# CONFIG_NET_VENDOR_BROCADE is not set
  2137. +CONFIG_MACB=m
  2138. +# CONFIG_NET_VENDOR_CAVIUM is not set
  2139. +# CONFIG_NET_VENDOR_CHELSIO is not set
  2140. +# CONFIG_NET_VENDOR_CISCO is not set
  2141. +CONFIG_DNET=m
  2142. +# CONFIG_NET_VENDOR_DEC is not set
  2143. +CONFIG_DL2K=m
  2144. +CONFIG_SUNDANCE=m
  2145. +# CONFIG_NET_VENDOR_EMULEX is not set
  2146. +# CONFIG_NET_VENDOR_EZCHIP is not set
  2147. +CONFIG_HIX5HD2_GMAC=m
  2148. +CONFIG_HIP04_ETH=m
  2149. +CONFIG_HNS_DSAF=m
  2150. +CONFIG_HNS_ENET=m
  2151. +# CONFIG_NET_VENDOR_I825XX is not set
  2152. +CONFIG_E100=m
  2153. +CONFIG_E1000=m
  2154. +CONFIG_E1000E=m
  2155. +CONFIG_IGB=m
  2156. +CONFIG_IGBVF=m
  2157. +CONFIG_IXGB=m
  2158. +CONFIG_IXGBE=m
  2159. +CONFIG_IXGBE_DCB=y
  2160. +CONFIG_IXGBEVF=m
  2161. +CONFIG_I40E=m
  2162. +CONFIG_I40EVF=m
  2163. +CONFIG_FM10K=m
  2164. +CONFIG_JME=m
  2165. +CONFIG_MVMDIO=m
  2166. +CONFIG_SKGE=m
  2167. +CONFIG_SKGE_GENESIS=y
  2168. +CONFIG_SKY2=m
  2169. +CONFIG_MLX4_EN=m
  2170. +CONFIG_KSZ884X_PCI=m
  2171. +CONFIG_MYRI10GE=m
  2172. +CONFIG_FEALNX=m
  2173. +CONFIG_NATSEMI=m
  2174. +CONFIG_NS83820=m
  2175. +CONFIG_NE2K_PCI=m
  2176. +CONFIG_FORCEDETH=m
  2177. +CONFIG_ETHOC=m
  2178. +CONFIG_HAMACHI=m
  2179. +CONFIG_YELLOWFIN=m
  2180. +# CONFIG_NET_VENDOR_QLOGIC is not set
  2181. +# CONFIG_NET_VENDOR_QUALCOMM is not set
  2182. +CONFIG_R6040=m
  2183. +CONFIG_8139CP=m
  2184. +CONFIG_8139TOO=m
  2185. +# CONFIG_8139TOO_PIO is not set
  2186. +CONFIG_8139TOO_8129=y
  2187. +CONFIG_R8169=m
  2188. +# CONFIG_NET_VENDOR_RENESAS is not set
  2189. +CONFIG_ROCKER=m
  2190. +# CONFIG_NET_VENDOR_SAMSUNG is not set
  2191. +# CONFIG_NET_VENDOR_SEEQ is not set
  2192. +CONFIG_SC92031=m
  2193. +CONFIG_SIS900=m
  2194. +CONFIG_SIS190=m
  2195. +CONFIG_SMC91X=m
  2196. +CONFIG_EPIC100=m
  2197. +CONFIG_SMSC911X=m
  2198. +CONFIG_SMSC9420=m
  2199. +CONFIG_STMMAC_ETH=m
  2200. +CONFIG_DWMAC_DWC_QOS_ETH=m
  2201. +# CONFIG_NET_VENDOR_SUN is not set
  2202. +CONFIG_TEHUTI=m
  2203. +CONFIG_VIA_RHINE=m
  2204. +CONFIG_VIA_RHINE_MMIO=y
  2205. +CONFIG_VIA_VELOCITY=m
  2206. +# CONFIG_NET_VENDOR_WIZNET is not set
  2207. +CONFIG_NET_SB1000=y
  2208. +CONFIG_MDIO_BITBANG=m
  2209. +CONFIG_MDIO_BUS_MUX_GPIO=m
  2210. +CONFIG_MDIO_BUS_MUX_MMIOREG=m
  2211. +CONFIG_PHYLIB=y
  2212. +CONFIG_LED_TRIGGER_PHY=y
  2213. +CONFIG_SFP=m
  2214. +CONFIG_AMD_PHY=m
  2215. +CONFIG_BCM87XX_PHY=m
  2216. +CONFIG_BROADCOM_PHY=m
  2217. +CONFIG_CICADA_PHY=m
  2218. +CONFIG_DAVICOM_PHY=m
  2219. +CONFIG_DP83848_PHY=m
  2220. +CONFIG_DP83867_PHY=m
  2221. +CONFIG_ICPLUS_PHY=m
  2222. +CONFIG_LSI_ET1011C_PHY=m
  2223. +CONFIG_LXT_PHY=m
  2224. +CONFIG_MARVELL_10G_PHY=m
  2225. +CONFIG_MICREL_PHY=m
  2226. +CONFIG_NATIONAL_PHY=m
  2227. +CONFIG_AT803X_PHY=m
  2228. +CONFIG_QSEMI_PHY=m
  2229. +CONFIG_ROCKCHIP_PHY=y
  2230. +CONFIG_STE10XP=m
  2231. +CONFIG_VITESSE_PHY=m
  2232. +CONFIG_PPP=m
  2233. +CONFIG_PPP_BSDCOMP=m
  2234. +CONFIG_PPP_DEFLATE=m
  2235. +CONFIG_PPP_FILTER=y
  2236. +CONFIG_PPP_MPPE=m
  2237. +CONFIG_PPP_MULTILINK=y
  2238. +CONFIG_PPPOATM=m
  2239. +CONFIG_PPPOE=m
  2240. +CONFIG_PPTP=m
  2241. +CONFIG_PPPOL2TP=m
  2242. +CONFIG_PPP_ASYNC=m
  2243. +CONFIG_PPP_SYNC_TTY=m
  2244. +CONFIG_SLIP=m
  2245. +CONFIG_SLIP_COMPRESSED=y
  2246. +CONFIG_SLIP_SMART=y
  2247. +CONFIG_USB_CATC=m
  2248. +CONFIG_USB_KAWETH=m
  2249. +CONFIG_USB_PEGASUS=m
  2250. +CONFIG_USB_RTL8150=m
  2251. +CONFIG_USB_RTL8152=m
  2252. +CONFIG_USB_LAN78XX=m
  2253. +CONFIG_USB_NET_CDC_EEM=m
  2254. +CONFIG_USB_NET_HUAWEI_CDC_NCM=m
  2255. +CONFIG_USB_NET_CDC_MBIM=m
  2256. +CONFIG_USB_NET_DM9601=m
  2257. +CONFIG_USB_NET_SR9700=m
  2258. +CONFIG_USB_NET_SR9800=m
  2259. +CONFIG_USB_NET_SMSC75XX=m
  2260. +CONFIG_USB_NET_SMSC95XX=m
  2261. +CONFIG_USB_NET_GL620A=m
  2262. +CONFIG_USB_NET_PLUSB=m
  2263. +CONFIG_USB_NET_MCS7830=m
  2264. +CONFIG_USB_ALI_M5632=y
  2265. +CONFIG_USB_AN2720=y
  2266. +CONFIG_USB_EPSON2888=y
  2267. +CONFIG_USB_KC2190=y
  2268. +CONFIG_USB_NET_CX82310_ETH=m
  2269. +CONFIG_USB_NET_KALMIA=m
  2270. +CONFIG_USB_NET_QMI_WWAN=m
  2271. +CONFIG_USB_HSO=m
  2272. +CONFIG_USB_NET_INT51X1=m
  2273. +CONFIG_USB_IPHETH=m
  2274. +CONFIG_USB_SIERRA_NET=m
  2275. +CONFIG_USB_VL600=m
  2276. +CONFIG_USB_NET_CH9200=m
  2277. +CONFIG_ADM8211=m
  2278. +CONFIG_ATH5K=m
  2279. +CONFIG_ATH5K_DEBUG=y
  2280. +CONFIG_ATH9K=m
  2281. +CONFIG_ATH9K_AHB=y
  2282. +CONFIG_ATH9K_DEBUGFS=y
  2283. +CONFIG_ATH9K_HTC=m
  2284. +CONFIG_ATH9K_HWRNG=y
  2285. +CONFIG_ATH9K_COMMON_SPECTRAL=y
  2286. +CONFIG_CARL9170=m
  2287. +CONFIG_ATH6KL=m
  2288. +CONFIG_ATH6KL_SDIO=m
  2289. +CONFIG_ATH6KL_USB=m
  2290. +CONFIG_ATH6KL_DEBUG=y
  2291. +CONFIG_AR5523=m
  2292. +CONFIG_WIL6210=m
  2293. +CONFIG_ATH10K=m
  2294. +CONFIG_ATH10K_PCI=m
  2295. +CONFIG_ATH10K_DEBUGFS=y
  2296. +CONFIG_WCN36XX=m
  2297. +CONFIG_ATMEL=m
  2298. +CONFIG_PCI_ATMEL=m
  2299. +CONFIG_AT76C50X_USB=m
  2300. +CONFIG_B43=m
  2301. +CONFIG_B43_SDIO=y
  2302. +CONFIG_B43_DEBUG=y
  2303. +CONFIG_B43LEGACY=m
  2304. +CONFIG_BRCMSMAC=m
  2305. +CONFIG_BRCMFMAC=m
  2306. +CONFIG_BRCMFMAC_USB=y
  2307. +CONFIG_BRCMFMAC_PCIE=y
  2308. +CONFIG_BRCM_TRACING=y
  2309. +CONFIG_BRCMDBG=y
  2310. +CONFIG_IPW2100=m
  2311. +CONFIG_IPW2100_MONITOR=y
  2312. +CONFIG_IPW2200=m
  2313. +CONFIG_IPW2200_MONITOR=y
  2314. +CONFIG_IPW2200_PROMISCUOUS=y
  2315. +CONFIG_IPW2200_QOS=y
  2316. +CONFIG_IWL4965=m
  2317. +CONFIG_IWL3945=m
  2318. +CONFIG_IWLEGACY_DEBUG=y
  2319. +CONFIG_IWLEGACY_DEBUGFS=y
  2320. +CONFIG_IWLWIFI=m
  2321. +CONFIG_IWLDVM=m
  2322. +CONFIG_IWLMVM=m
  2323. +CONFIG_IWLWIFI_DEBUG=y
  2324. +CONFIG_IWLWIFI_DEBUGFS=y
  2325. +CONFIG_HOSTAP=m
  2326. +CONFIG_HOSTAP_FIRMWARE=y
  2327. +CONFIG_HOSTAP_PLX=m
  2328. +CONFIG_HOSTAP_PCI=m
  2329. +CONFIG_HERMES=m
  2330. +CONFIG_HERMES_PRISM=y
  2331. +CONFIG_PLX_HERMES=m
  2332. +CONFIG_TMD_HERMES=m
  2333. +CONFIG_NORTEL_HERMES=m
  2334. +CONFIG_PCI_HERMES=m
  2335. +CONFIG_ORINOCO_USB=m
  2336. +CONFIG_P54_COMMON=m
  2337. +CONFIG_P54_USB=m
  2338. +CONFIG_P54_PCI=m
  2339. +CONFIG_PRISM54=m
  2340. +CONFIG_LIBERTAS=m
  2341. +CONFIG_LIBERTAS_USB=m
  2342. +CONFIG_LIBERTAS_SDIO=m
  2343. +CONFIG_LIBERTAS_MESH=y
  2344. +CONFIG_LIBERTAS_THINFIRM=m
  2345. +CONFIG_LIBERTAS_THINFIRM_USB=m
  2346. +CONFIG_MWIFIEX=m
  2347. +CONFIG_MWIFIEX_SDIO=m
  2348. +CONFIG_MWIFIEX_PCIE=m
  2349. +CONFIG_MWIFIEX_USB=m
  2350. +CONFIG_MWL8K=m
  2351. +CONFIG_MT7601U=m
  2352. +CONFIG_RT2X00=m
  2353. +CONFIG_RT2400PCI=m
  2354. +CONFIG_RT2500PCI=m
  2355. +CONFIG_RT61PCI=m
  2356. +CONFIG_RT2800PCI=m
  2357. +CONFIG_RT2500USB=m
  2358. +CONFIG_RT73USB=m
  2359. +CONFIG_RT2800USB=m
  2360. +CONFIG_RT2800USB_RT3573=y
  2361. +CONFIG_RT2800USB_RT53XX=y
  2362. +CONFIG_RT2800USB_RT55XX=y
  2363. +CONFIG_RT2800USB_UNKNOWN=y
  2364. +CONFIG_RT2X00_LIB_DEBUGFS=y
  2365. +CONFIG_RTL8180=m
  2366. +CONFIG_RTL8187=m
  2367. +CONFIG_RTL8192CE=m
  2368. +CONFIG_RTL8192SE=m
  2369. +CONFIG_RTL8192DE=m
  2370. +CONFIG_RTL8723AE=m
  2371. +CONFIG_RTL8723BE=m
  2372. +CONFIG_RTL8188EE=m
  2373. +CONFIG_RTL8192EE=m
  2374. +CONFIG_RTL8821AE=m
  2375. +CONFIG_RTL8192CU=m
  2376. +CONFIG_RTL8XXXU=m
  2377. +CONFIG_RSI_91X=m
  2378. +CONFIG_CW1200=m
  2379. +CONFIG_CW1200_WLAN_SDIO=m
  2380. +CONFIG_WL1251=m
  2381. +CONFIG_WL1251_SPI=m
  2382. +CONFIG_WL1251_SDIO=m
  2383. +CONFIG_WL12XX=m
  2384. +CONFIG_WL18XX=m
  2385. +CONFIG_WLCORE_SPI=m
  2386. +CONFIG_WLCORE_SDIO=m
  2387. +CONFIG_USB_ZD1201=m
  2388. +CONFIG_ZD1211RW=m
  2389. +CONFIG_QTNFMAC_PCIE=m
  2390. +CONFIG_MAC80211_HWSIM=m
  2391. +CONFIG_USB_NET_RNDIS_WLAN=m
  2392. +CONFIG_IEEE802154_FAKELB=m
  2393. +CONFIG_IEEE802154_ATUSB=m
  2394. +CONFIG_INPUT_SPARSEKMAP=m
  2395. +CONFIG_INPUT_MOUSEDEV=y
  2396. +CONFIG_INPUT_JOYDEV=m
  2397. +CONFIG_INPUT_EVDEV=y
  2398. +CONFIG_KEYBOARD_ADC=m
  2399. +CONFIG_KEYBOARD_GPIO=m
  2400. +CONFIG_KEYBOARD_GPIO_POLLED=m
  2401. +CONFIG_KEYBOARD_CROS_EC=y
  2402. +CONFIG_MOUSE_PS2_ELANTECH=y
  2403. +CONFIG_MOUSE_PS2_SENTELIC=y
  2404. +CONFIG_MOUSE_SERIAL=m
  2405. +CONFIG_MOUSE_APPLETOUCH=m
  2406. +CONFIG_MOUSE_BCM5974=m
  2407. +CONFIG_MOUSE_CYAPA=m
  2408. +CONFIG_MOUSE_ELAN_I2C=y
  2409. +CONFIG_MOUSE_ELAN_I2C_SMBUS=y
  2410. +CONFIG_MOUSE_VSXXXAA=m
  2411. +CONFIG_MOUSE_SYNAPTICS_I2C=m
  2412. +CONFIG_MOUSE_SYNAPTICS_USB=m
  2413. +CONFIG_INPUT_JOYSTICK=y
  2414. +CONFIG_JOYSTICK_IFORCE=m
  2415. +CONFIG_JOYSTICK_IFORCE_USB=m
  2416. +CONFIG_JOYSTICK_IFORCE_232=m
  2417. +CONFIG_JOYSTICK_WARRIOR=m
  2418. +CONFIG_JOYSTICK_MAGELLAN=m
  2419. +CONFIG_JOYSTICK_SPACEORB=m
  2420. +CONFIG_JOYSTICK_SPACEBALL=m
  2421. +CONFIG_JOYSTICK_STINGER=m
  2422. +CONFIG_JOYSTICK_TWIDJOY=m
  2423. +CONFIG_JOYSTICK_ZHENHUA=m
  2424. +CONFIG_JOYSTICK_XPAD=m
  2425. +CONFIG_JOYSTICK_XPAD_FF=y
  2426. +CONFIG_JOYSTICK_XPAD_LEDS=y
  2427. +CONFIG_INPUT_TABLET=y
  2428. +CONFIG_TABLET_USB_ACECAD=m
  2429. +CONFIG_TABLET_USB_AIPTEK=m
  2430. +CONFIG_TABLET_USB_GTCO=m
  2431. +CONFIG_TABLET_USB_HANWANG=m
  2432. +CONFIG_TABLET_USB_KBTAB=m
  2433. +CONFIG_TABLET_USB_PEGASUS=m
  2434. +CONFIG_TABLET_SERIAL_WACOM4=m
  2435. +CONFIG_INPUT_TOUCHSCREEN=y
  2436. +CONFIG_TOUCHSCREEN_ATMEL_MXT=y
  2437. +CONFIG_TOUCHSCREEN_AUO_PIXCIR=m
  2438. +CONFIG_TOUCHSCREEN_DYNAPRO=m
  2439. +CONFIG_TOUCHSCREEN_EETI=m
  2440. +CONFIG_TOUCHSCREEN_EGALAX=m
  2441. +CONFIG_TOUCHSCREEN_FUJITSU=m
  2442. +CONFIG_TOUCHSCREEN_ILI210X=m
  2443. +CONFIG_TOUCHSCREEN_GUNZE=m
  2444. +CONFIG_TOUCHSCREEN_ELAN=m
  2445. +CONFIG_TOUCHSCREEN_ELO=m
  2446. +CONFIG_TOUCHSCREEN_WACOM_W8001=m
  2447. +CONFIG_TOUCHSCREEN_WACOM_I2C=m
  2448. +CONFIG_TOUCHSCREEN_MCS5000=m
  2449. +CONFIG_TOUCHSCREEN_MMS114=m
  2450. +CONFIG_TOUCHSCREEN_MTOUCH=m
  2451. +CONFIG_TOUCHSCREEN_INEXIO=m
  2452. +CONFIG_TOUCHSCREEN_MK712=m
  2453. +CONFIG_TOUCHSCREEN_PENMOUNT=m
  2454. +CONFIG_TOUCHSCREEN_EDT_FT5X06=m
  2455. +CONFIG_TOUCHSCREEN_TOUCHRIGHT=m
  2456. +CONFIG_TOUCHSCREEN_TOUCHWIN=m
  2457. +CONFIG_TOUCHSCREEN_PIXCIR=m
  2458. +CONFIG_TOUCHSCREEN_USB_COMPOSITE=m
  2459. +CONFIG_TOUCHSCREEN_TOUCHIT213=m
  2460. +CONFIG_TOUCHSCREEN_TSC_SERIO=m
  2461. +CONFIG_TOUCHSCREEN_TSC2007=m
  2462. +CONFIG_TOUCHSCREEN_ST1232=m
  2463. +CONFIG_TOUCHSCREEN_ZFORCE=m
  2464. +CONFIG_INPUT_MISC=y
  2465. +CONFIG_INPUT_E3X0_BUTTON=m
  2466. +CONFIG_INPUT_MMA8450=m
  2467. +CONFIG_INPUT_GP2A=m
  2468. +CONFIG_INPUT_ATI_REMOTE2=m
  2469. +CONFIG_INPUT_KEYSPAN_REMOTE=m
  2470. +CONFIG_INPUT_KXTJ9=m
  2471. +CONFIG_INPUT_POWERMATE=m
  2472. +CONFIG_INPUT_YEALINK=m
  2473. +CONFIG_INPUT_CM109=m
  2474. +CONFIG_INPUT_AXP20X_PEK=m
  2475. +CONFIG_INPUT_UINPUT=m
  2476. +CONFIG_INPUT_PWM_BEEPER=m
  2477. +CONFIG_INPUT_RK805_PWRKEY=m
  2478. +CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
  2479. +CONFIG_INPUT_CMA3000=m
  2480. +CONFIG_INPUT_CMA3000_I2C=m
  2481. +CONFIG_SERIO_AMBAKMI=y
  2482. +CONFIG_SERIO_RAW=m
  2483. +CONFIG_SERIO_ALTERA_PS2=m
  2484. +CONFIG_SERIO_ARC_PS2=m
  2485. +# CONFIG_LEGACY_PTYS is not set
  2486. +CONFIG_SERIAL_NONSTANDARD=y
  2487. +CONFIG_ROCKETPORT=m
  2488. +CONFIG_CYCLADES=m
  2489. +CONFIG_SYNCLINKMP=m
  2490. +CONFIG_SYNCLINK_GT=m
  2491. +CONFIG_NOZOMI=m
  2492. +CONFIG_N_HDLC=m
  2493. +CONFIG_N_GSM=m
  2494. +CONFIG_SERIAL_8250=y
  2495. +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
  2496. +CONFIG_SERIAL_8250_CONSOLE=y
  2497. +CONFIG_SERIAL_8250_NR_UARTS=32
  2498. +CONFIG_SERIAL_8250_EXTENDED=y
  2499. +CONFIG_SERIAL_8250_MANY_PORTS=y
  2500. +CONFIG_SERIAL_8250_SHARE_IRQ=y
  2501. +CONFIG_SERIAL_8250_RSA=y
  2502. +CONFIG_SERIAL_8250_DW=y
  2503. +CONFIG_SERIAL_OF_PLATFORM=y
  2504. +CONFIG_SERIAL_AMBA_PL011=y
  2505. +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
  2506. +CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST=y
  2507. +CONFIG_SERIAL_JSM=m
  2508. +CONFIG_SERIAL_ARC=m
  2509. +CONFIG_SERIAL_FSL_LPUART=y
  2510. +CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
  2511. +CONFIG_SERIAL_DEV_BUS=y
  2512. +CONFIG_VIRTIO_CONSOLE=y
  2513. +CONFIG_IPMI_HANDLER=y
  2514. +CONFIG_IPMI_DEVICE_INTERFACE=m
  2515. +CONFIG_IPMI_SSIF=m
  2516. +CONFIG_IPMI_WATCHDOG=m
  2517. +CONFIG_IPMI_POWEROFF=m
  2518. +CONFIG_HW_RANDOM=y
  2519. +CONFIG_HW_RANDOM_TIMERIOMEM=m
  2520. +CONFIG_HW_RANDOM_VIRTIO=m
  2521. +CONFIG_RAW_DRIVER=y
  2522. +CONFIG_MAX_RAW_DEVS=8192
  2523. +CONFIG_TCG_TPM=y
  2524. +CONFIG_TCG_TIS_I2C_INFINEON=y
  2525. +CONFIG_TCG_ATMEL=m
  2526. +CONFIG_I2C_CHARDEV=m
  2527. +CONFIG_I2C_ARB_GPIO_CHALLENGE=m
  2528. +CONFIG_I2C_MUX_GPIO=m
  2529. +CONFIG_I2C_MUX_GPMUX=m
  2530. +CONFIG_I2C_MUX_PCA9541=m
  2531. +CONFIG_I2C_MUX_PCA954x=y
  2532. +CONFIG_I2C_MUX_PINCTRL=m
  2533. +CONFIG_I2C_MUX_REG=m
  2534. +CONFIG_I2C_DEMUX_PINCTRL=m
  2535. +CONFIG_I2C_NFORCE2=m
  2536. +CONFIG_I2C_SCMI=y
  2537. +CONFIG_I2C_DESIGNWARE_PLATFORM=y
  2538. +CONFIG_I2C_DESIGNWARE_PCI=m
  2539. +CONFIG_I2C_GPIO=m
  2540. +CONFIG_I2C_PCA_PLATFORM=m
  2541. +CONFIG_I2C_RK3X=y
  2542. +CONFIG_I2C_SIMTEC=m
  2543. +CONFIG_I2C_DIOLAN_U2C=m
  2544. +CONFIG_I2C_TINY_USB=m
  2545. +CONFIG_I2C_VIPERBOARD=m
  2546. +CONFIG_I2C_CROS_EC_TUNNEL=y
  2547. +CONFIG_I2C_STUB=m
  2548. +CONFIG_I2C_SLAVE=y
  2549. +CONFIG_I2C_SLAVE_EEPROM=m
  2550. +CONFIG_SPI=y
  2551. +CONFIG_SPI_NXP_FLEXSPI=y
  2552. +CONFIG_SPI_GPIO=y
  2553. +CONFIG_SPI_PL022=y
  2554. +CONFIG_SPI_ROCKCHIP=y
  2555. +CONFIG_SPI_SPIDEV=m
  2556. +CONFIG_SPMI=y
  2557. +CONFIG_PPS_CLIENT_LDISC=m
  2558. +CONFIG_PPS_CLIENT_GPIO=m
  2559. +CONFIG_DP83640_PHY=m
  2560. +CONFIG_PINCTRL_AMD=y
  2561. +CONFIG_PINCTRL_SINGLE=y
  2562. +CONFIG_PINCTRL_MAX77620=y
  2563. +CONFIG_PINCTRL_RK805=y
  2564. +CONFIG_GPIO_SYSFS=y
  2565. +CONFIG_GPIO_DWAPB=y
  2566. +CONFIG_GPIO_PL061=y
  2567. +CONFIG_GPIO_SYSCON=y
  2568. +CONFIG_GPIO_XGENE=y
  2569. +CONFIG_GPIO_PCA953X=y
  2570. +CONFIG_GPIO_PCA953X_IRQ=y
  2571. +CONFIG_GPIO_MAX77620=y
  2572. +CONFIG_GPIO_VIPERBOARD=m
  2573. +CONFIG_W1=m
  2574. +CONFIG_W1_MASTER_DS2490=m
  2575. +CONFIG_W1_MASTER_DS2482=m
  2576. +CONFIG_W1_MASTER_DS1WM=m
  2577. +CONFIG_W1_SLAVE_THERM=m
  2578. +CONFIG_W1_SLAVE_SMEM=m
  2579. +CONFIG_W1_SLAVE_DS2408=m
  2580. +# CONFIG_W1_SLAVE_DS2408_READBACK is not set
  2581. +CONFIG_W1_SLAVE_DS2413=m
  2582. +CONFIG_W1_SLAVE_DS2406=m
  2583. +CONFIG_W1_SLAVE_DS2423=m
  2584. +CONFIG_W1_SLAVE_DS2431=m
  2585. +CONFIG_W1_SLAVE_DS2433=m
  2586. +CONFIG_W1_SLAVE_DS2433_CRC=y
  2587. +CONFIG_W1_SLAVE_DS2780=m
  2588. +CONFIG_W1_SLAVE_DS2781=m
  2589. +CONFIG_W1_SLAVE_DS28E04=m
  2590. +CONFIG_POWER_AVS=y
  2591. +CONFIG_ROCKCHIP_IODOMAIN=y
  2592. +CONFIG_POWER_RESET_GPIO=y
  2593. +CONFIG_POWER_RESET_GPIO_RESTART=y
  2594. +CONFIG_POWER_RESET_RESTART=y
  2595. +CONFIG_POWER_RESET_VEXPRESS=y
  2596. +CONFIG_POWER_RESET_XGENE=y
  2597. +CONFIG_POWER_RESET_SYSCON=y
  2598. +CONFIG_POWER_RESET_SYSCON_POWEROFF=y
  2599. +CONFIG_SYSCON_REBOOT_MODE=y
  2600. +CONFIG_BATTERY_CW2015=m
  2601. +CONFIG_BATTERY_SBS=m
  2602. +CONFIG_CHARGER_SBS=m
  2603. +CONFIG_MANAGER_SBS=m
  2604. +CONFIG_CHARGER_AXP20X=m
  2605. +CONFIG_CHARGER_GPIO=y
  2606. +CONFIG_CHARGER_SMB347=m
  2607. +CONFIG_CHARGER_CROS_USBPD=m
  2608. +CONFIG_SENSORS_AD7414=m
  2609. +CONFIG_SENSORS_AD7418=m
  2610. +CONFIG_SENSORS_ADM1021=m
  2611. +CONFIG_SENSORS_ADM1025=m
  2612. +CONFIG_SENSORS_ADM1026=m
  2613. +CONFIG_SENSORS_ADM1029=m
  2614. +CONFIG_SENSORS_ADM1031=m
  2615. +CONFIG_SENSORS_ADM9240=m
  2616. +CONFIG_SENSORS_ADT7410=m
  2617. +CONFIG_SENSORS_ADT7411=m
  2618. +CONFIG_SENSORS_ADT7462=m
  2619. +CONFIG_SENSORS_ADT7470=m
  2620. +CONFIG_SENSORS_ADT7475=m
  2621. +CONFIG_SENSORS_ASC7621=m
  2622. +CONFIG_SENSORS_ARM_SCPI=y
  2623. +CONFIG_SENSORS_ATXP1=m
  2624. +CONFIG_SENSORS_DS620=m
  2625. +CONFIG_SENSORS_DS1621=m
  2626. +CONFIG_SENSORS_F71805F=m
  2627. +CONFIG_SENSORS_F71882FG=m
  2628. +CONFIG_SENSORS_F75375S=m
  2629. +CONFIG_SENSORS_GL518SM=m
  2630. +CONFIG_SENSORS_GL520SM=m
  2631. +CONFIG_SENSORS_G760A=m
  2632. +CONFIG_SENSORS_G762=m
  2633. +CONFIG_SENSORS_GPIO_FAN=m
  2634. +CONFIG_SENSORS_IBMAEM=m
  2635. +CONFIG_SENSORS_IBMPEX=m
  2636. +CONFIG_SENSORS_IIO_HWMON=m
  2637. +CONFIG_SENSORS_IT87=m
  2638. +CONFIG_SENSORS_POWR1220=m
  2639. +CONFIG_SENSORS_LINEAGE=m
  2640. +CONFIG_SENSORS_LTC2945=m
  2641. +CONFIG_SENSORS_LTC4151=m
  2642. +CONFIG_SENSORS_LTC4215=m
  2643. +CONFIG_SENSORS_LTC4222=m
  2644. +CONFIG_SENSORS_LTC4245=m
  2645. +CONFIG_SENSORS_LTC4260=m
  2646. +CONFIG_SENSORS_LTC4261=m
  2647. +CONFIG_SENSORS_MAX16065=m
  2648. +CONFIG_SENSORS_MAX1619=m
  2649. +CONFIG_SENSORS_MAX1668=m
  2650. +CONFIG_SENSORS_MAX197=m
  2651. +CONFIG_SENSORS_MAX6639=m
  2652. +CONFIG_SENSORS_MAX6642=m
  2653. +CONFIG_SENSORS_MAX6650=m
  2654. +CONFIG_SENSORS_MAX6697=m
  2655. +CONFIG_SENSORS_MCP3021=m
  2656. +CONFIG_SENSORS_LM63=m
  2657. +CONFIG_SENSORS_LM73=m
  2658. +CONFIG_SENSORS_LM75=m
  2659. +CONFIG_SENSORS_LM77=m
  2660. +CONFIG_SENSORS_LM78=m
  2661. +CONFIG_SENSORS_LM80=m
  2662. +CONFIG_SENSORS_LM83=m
  2663. +CONFIG_SENSORS_LM85=m
  2664. +CONFIG_SENSORS_LM87=m
  2665. +CONFIG_SENSORS_LM90=m
  2666. +CONFIG_SENSORS_LM92=m
  2667. +CONFIG_SENSORS_LM93=m
  2668. +CONFIG_SENSORS_LM95234=m
  2669. +CONFIG_SENSORS_LM95241=m
  2670. +CONFIG_SENSORS_LM95245=m
  2671. +CONFIG_SENSORS_PC87360=m
  2672. +CONFIG_SENSORS_PC87427=m
  2673. +CONFIG_SENSORS_NTC_THERMISTOR=m
  2674. +CONFIG_SENSORS_NCT6683=m
  2675. +CONFIG_SENSORS_NCT6775=m
  2676. +CONFIG_SENSORS_NCT7802=m
  2677. +CONFIG_SENSORS_NCT7904=m
  2678. +CONFIG_SENSORS_PCF8591=m
  2679. +CONFIG_PMBUS=m
  2680. +CONFIG_SENSORS_ADM1275=m
  2681. +CONFIG_SENSORS_LM25066=m
  2682. +CONFIG_SENSORS_LTC2978=m
  2683. +CONFIG_SENSORS_MAX16064=m
  2684. +CONFIG_SENSORS_MAX34440=m
  2685. +CONFIG_SENSORS_MAX8688=m
  2686. +CONFIG_SENSORS_TPS40422=m
  2687. +CONFIG_SENSORS_UCD9000=m
  2688. +CONFIG_SENSORS_UCD9200=m
  2689. +CONFIG_SENSORS_ZL6100=m
  2690. +CONFIG_SENSORS_PWM_FAN=m
  2691. +CONFIG_SENSORS_SHT15=m
  2692. +CONFIG_SENSORS_SHT21=m
  2693. +CONFIG_SENSORS_SHT3x=m
  2694. +CONFIG_SENSORS_SHTC1=m
  2695. +CONFIG_SENSORS_SIS5595=m
  2696. +CONFIG_SENSORS_DME1737=m
  2697. +CONFIG_SENSORS_EMC1403=m
  2698. +CONFIG_SENSORS_EMC6W201=m
  2699. +CONFIG_SENSORS_SMSC47M1=m
  2700. +CONFIG_SENSORS_SMSC47M192=m
  2701. +CONFIG_SENSORS_SMSC47B397=m
  2702. +CONFIG_SENSORS_SCH5627=m
  2703. +CONFIG_SENSORS_SCH5636=m
  2704. +CONFIG_SENSORS_ADC128D818=m
  2705. +CONFIG_SENSORS_ADS7828=m
  2706. +CONFIG_SENSORS_AMC6821=m
  2707. +CONFIG_SENSORS_INA209=m
  2708. +CONFIG_SENSORS_INA2XX=m
  2709. +CONFIG_SENSORS_INA3221=m
  2710. +CONFIG_SENSORS_TC74=m
  2711. +CONFIG_SENSORS_THMC50=m
  2712. +CONFIG_SENSORS_TMP102=m
  2713. +CONFIG_SENSORS_TMP103=m
  2714. +CONFIG_SENSORS_TMP108=m
  2715. +CONFIG_SENSORS_TMP401=m
  2716. +CONFIG_SENSORS_TMP421=m
  2717. +CONFIG_SENSORS_VEXPRESS=m
  2718. +CONFIG_SENSORS_VIA686A=m
  2719. +CONFIG_SENSORS_VT1211=m
  2720. +CONFIG_SENSORS_VT8231=m
  2721. +CONFIG_SENSORS_W83781D=m
  2722. +CONFIG_SENSORS_W83791D=m
  2723. +CONFIG_SENSORS_W83792D=m
  2724. +CONFIG_SENSORS_W83793=m
  2725. +CONFIG_SENSORS_W83795=m
  2726. +CONFIG_SENSORS_W83L785TS=m
  2727. +CONFIG_SENSORS_W83L786NG=m
  2728. +CONFIG_SENSORS_W83627HF=m
  2729. +CONFIG_SENSORS_W83627EHF=m
  2730. +CONFIG_SENSORS_ACPI_POWER=m
  2731. +CONFIG_THERMAL_WRITABLE_TRIPS=y
  2732. +CONFIG_THERMAL_GOV_FAIR_SHARE=y
  2733. +CONFIG_THERMAL_GOV_BANG_BANG=y
  2734. +CONFIG_THERMAL_GOV_USER_SPACE=y
  2735. +CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
  2736. +CONFIG_CPU_THERMAL=y
  2737. +CONFIG_CLOCK_THERMAL=y
  2738. +CONFIG_DEVFREQ_THERMAL=y
  2739. +CONFIG_THERMAL_EMULATION=y
  2740. +CONFIG_MAX77620_THERMAL=m
  2741. +CONFIG_ROCKCHIP_THERMAL=m
  2742. +CONFIG_GENERIC_ADC_THERMAL=m
  2743. +CONFIG_WATCHDOG=y
  2744. +CONFIG_WATCHDOG_CORE=y
  2745. +CONFIG_SOFT_WATCHDOG=m
  2746. +CONFIG_GPIO_WATCHDOG=m
  2747. +CONFIG_ARM_SP805_WATCHDOG=m
  2748. +CONFIG_ARM_SBSA_WATCHDOG=m
  2749. +CONFIG_DW_WATCHDOG=m
  2750. +CONFIG_MAX77620_WATCHDOG=m
  2751. +CONFIG_ALIM7101_WDT=m
  2752. +CONFIG_I6300ESB_WDT=m
  2753. +CONFIG_PCIPCWATCHDOG=m
  2754. +CONFIG_WDTPCI=m
  2755. +CONFIG_USBPCWATCHDOG=m
  2756. +CONFIG_SSB_DRIVER_GPIO=y
  2757. +CONFIG_BCMA_DRIVER_GMAC_CMN=y
  2758. +CONFIG_BCMA_DRIVER_GPIO=y
  2759. +CONFIG_MFD_AXP20X_I2C=y
  2760. +CONFIG_MFD_MAX77620=y
  2761. +CONFIG_MFD_VIPERBOARD=m
  2762. +CONFIG_MFD_RK808=y
  2763. +CONFIG_MFD_SEC_CORE=y
  2764. +CONFIG_MFD_SM501=m
  2765. +CONFIG_MFD_SM501_GPIO=y
  2766. +CONFIG_MFD_VX855=m
  2767. +CONFIG_REGULATOR_FIXED_VOLTAGE=y
  2768. +CONFIG_REGULATOR_AXP20X=y
  2769. +CONFIG_REGULATOR_FAN53555=y
  2770. +CONFIG_REGULATOR_GPIO=y
  2771. +CONFIG_REGULATOR_MAX77620=y
  2772. +CONFIG_REGULATOR_PFUZE100=y
  2773. +CONFIG_REGULATOR_PWM=y
  2774. +CONFIG_REGULATOR_QCOM_SPMI=y
  2775. +CONFIG_REGULATOR_RK808=y
  2776. +CONFIG_REGULATOR_S2MPS11=y
  2777. +CONFIG_REGULATOR_VCTRL=y
  2778. +CONFIG_REGULATOR_VEXPRESS=y
  2779. +CONFIG_RC_CORE=y
  2780. +CONFIG_LIRC=y
  2781. +CONFIG_BPF_LIRC_MODE2=y
  2782. +CONFIG_RC_DECODERS=y
  2783. +CONFIG_IR_NEC_DECODER=m
  2784. +CONFIG_IR_RC5_DECODER=m
  2785. +CONFIG_IR_RC6_DECODER=m
  2786. +CONFIG_IR_JVC_DECODER=m
  2787. +CONFIG_IR_SONY_DECODER=m
  2788. +CONFIG_IR_SANYO_DECODER=m
  2789. +CONFIG_IR_SHARP_DECODER=m
  2790. +CONFIG_IR_MCE_KBD_DECODER=m
  2791. +CONFIG_IR_XMP_DECODER=m
  2792. +CONFIG_IR_IMON_DECODER=m
  2793. +CONFIG_IR_RCMM_DECODER=m
  2794. +CONFIG_RC_DEVICES=y
  2795. +CONFIG_RC_ATI_REMOTE=m
  2796. +CONFIG_IR_ENE=m
  2797. +CONFIG_IR_HIX5HD2=m
  2798. +CONFIG_IR_IMON=m
  2799. +CONFIG_IR_IMON_RAW=m
  2800. +CONFIG_IR_MCEUSB=m
  2801. +CONFIG_IR_ITE_CIR=m
  2802. +CONFIG_IR_FINTEK=m
  2803. +CONFIG_IR_NUVOTON=m
  2804. +CONFIG_IR_REDRAT3=m
  2805. +CONFIG_IR_SPI=m
  2806. +CONFIG_IR_STREAMZAP=m
  2807. +CONFIG_IR_IGORPLUGUSB=m
  2808. +CONFIG_IR_IGUANA=m
  2809. +CONFIG_IR_TTUSBIR=m
  2810. +CONFIG_RC_LOOPBACK=m
  2811. +CONFIG_IR_GPIO_CIR=m
  2812. +CONFIG_IR_SERIAL=m
  2813. +CONFIG_IR_SERIAL_TRANSMITTER=y
  2814. +CONFIG_IR_SIR=m
  2815. +CONFIG_RC_XBOX_DVD=m
  2816. +CONFIG_MEDIA_SUPPORT=y
  2817. +CONFIG_MEDIA_CAMERA_SUPPORT=y
  2818. +CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
  2819. +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
  2820. +CONFIG_MEDIA_RADIO_SUPPORT=y
  2821. +CONFIG_MEDIA_SDR_SUPPORT=y
  2822. +CONFIG_MEDIA_CEC_SUPPORT=y
  2823. +CONFIG_MEDIA_CEC_RC=y
  2824. +CONFIG_MEDIA_CONTROLLER_REQUEST_API=y
  2825. +CONFIG_VIDEO_V4L2_SUBDEV_API=y
  2826. +CONFIG_DVB_MAX_ADAPTERS=8
  2827. +CONFIG_DVB_DYNAMIC_MINORS=y
  2828. +CONFIG_MEDIA_USB_SUPPORT=y
  2829. +CONFIG_USB_VIDEO_CLASS=m
  2830. +CONFIG_USB_M5602=m
  2831. +CONFIG_USB_STV06XX=m
  2832. +CONFIG_USB_GL860=m
  2833. +CONFIG_USB_GSPCA_BENQ=m
  2834. +CONFIG_USB_GSPCA_CONEX=m
  2835. +CONFIG_USB_GSPCA_CPIA1=m
  2836. +CONFIG_USB_GSPCA_DTCS033=m
  2837. +CONFIG_USB_GSPCA_ETOMS=m
  2838. +CONFIG_USB_GSPCA_FINEPIX=m
  2839. +CONFIG_USB_GSPCA_JEILINJ=m
  2840. +CONFIG_USB_GSPCA_JL2005BCD=m
  2841. +CONFIG_USB_GSPCA_KINECT=m
  2842. +CONFIG_USB_GSPCA_KONICA=m
  2843. +CONFIG_USB_GSPCA_MARS=m
  2844. +CONFIG_USB_GSPCA_MR97310A=m
  2845. +CONFIG_USB_GSPCA_NW80X=m
  2846. +CONFIG_USB_GSPCA_OV519=m
  2847. +CONFIG_USB_GSPCA_OV534=m
  2848. +CONFIG_USB_GSPCA_OV534_9=m
  2849. +CONFIG_USB_GSPCA_PAC207=m
  2850. +CONFIG_USB_GSPCA_PAC7302=m
  2851. +CONFIG_USB_GSPCA_PAC7311=m
  2852. +CONFIG_USB_GSPCA_SE401=m
  2853. +CONFIG_USB_GSPCA_SN9C2028=m
  2854. +CONFIG_USB_GSPCA_SN9C20X=m
  2855. +CONFIG_USB_GSPCA_SONIXB=m
  2856. +CONFIG_USB_GSPCA_SONIXJ=m
  2857. +CONFIG_USB_GSPCA_SPCA500=m
  2858. +CONFIG_USB_GSPCA_SPCA501=m
  2859. +CONFIG_USB_GSPCA_SPCA505=m
  2860. +CONFIG_USB_GSPCA_SPCA506=m
  2861. +CONFIG_USB_GSPCA_SPCA508=m
  2862. +CONFIG_USB_GSPCA_SPCA561=m
  2863. +CONFIG_USB_GSPCA_SPCA1528=m
  2864. +CONFIG_USB_GSPCA_SQ905=m
  2865. +CONFIG_USB_GSPCA_SQ905C=m
  2866. +CONFIG_USB_GSPCA_SQ930X=m
  2867. +CONFIG_USB_GSPCA_STK014=m
  2868. +CONFIG_USB_GSPCA_STK1135=m
  2869. +CONFIG_USB_GSPCA_STV0680=m
  2870. +CONFIG_USB_GSPCA_SUNPLUS=m
  2871. +CONFIG_USB_GSPCA_T613=m
  2872. +CONFIG_USB_GSPCA_TOPRO=m
  2873. +CONFIG_USB_GSPCA_TOUPTEK=m
  2874. +CONFIG_USB_GSPCA_TV8532=m
  2875. +CONFIG_USB_GSPCA_VC032X=m
  2876. +CONFIG_USB_GSPCA_VICAM=m
  2877. +CONFIG_USB_GSPCA_XIRLINK_CIT=m
  2878. +CONFIG_USB_GSPCA_ZC3XX=m
  2879. +CONFIG_USB_PWC=m
  2880. +CONFIG_VIDEO_CPIA2=m
  2881. +CONFIG_USB_ZR364XX=m
  2882. +CONFIG_USB_STKWEBCAM=m
  2883. +CONFIG_USB_S2255=m
  2884. +CONFIG_VIDEO_USBTV=m
  2885. +CONFIG_VIDEO_PVRUSB2=m
  2886. +CONFIG_VIDEO_HDPVR=m
  2887. +CONFIG_VIDEO_USBVISION=m
  2888. +CONFIG_VIDEO_STK1160_COMMON=m
  2889. +CONFIG_VIDEO_GO7007=m
  2890. +CONFIG_VIDEO_GO7007_USB=m
  2891. +CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m
  2892. +CONFIG_VIDEO_AU0828=m
  2893. +CONFIG_VIDEO_AU0828_RC=y
  2894. +CONFIG_VIDEO_CX231XX=m
  2895. +CONFIG_VIDEO_CX231XX_ALSA=m
  2896. +CONFIG_VIDEO_CX231XX_DVB=m
  2897. +CONFIG_VIDEO_TM6000=m
  2898. +CONFIG_VIDEO_TM6000_ALSA=m
  2899. +CONFIG_VIDEO_TM6000_DVB=m
  2900. +CONFIG_DVB_USB=m
  2901. +CONFIG_DVB_USB_A800=m
  2902. +CONFIG_DVB_USB_DIBUSB_MB=m
  2903. +CONFIG_DVB_USB_DIBUSB_MC=m
  2904. +CONFIG_DVB_USB_DIB0700=m
  2905. +CONFIG_DVB_USB_UMT_010=m
  2906. +CONFIG_DVB_USB_CXUSB=m
  2907. +CONFIG_DVB_USB_M920X=m
  2908. +CONFIG_DVB_USB_DIGITV=m
  2909. +CONFIG_DVB_USB_VP7045=m
  2910. +CONFIG_DVB_USB_VP702X=m
  2911. +CONFIG_DVB_USB_GP8PSK=m
  2912. +CONFIG_DVB_USB_NOVA_T_USB2=m
  2913. +CONFIG_DVB_USB_TTUSB2=m
  2914. +CONFIG_DVB_USB_DTT200U=m
  2915. +CONFIG_DVB_USB_OPERA1=m
  2916. +CONFIG_DVB_USB_AF9005=m
  2917. +CONFIG_DVB_USB_AF9005_REMOTE=m
  2918. +CONFIG_DVB_USB_PCTV452E=m
  2919. +CONFIG_DVB_USB_DW2102=m
  2920. +CONFIG_DVB_USB_CINERGY_T2=m
  2921. +CONFIG_DVB_USB_DTV5100=m
  2922. +CONFIG_DVB_USB_AZ6027=m
  2923. +CONFIG_DVB_USB_TECHNISAT_USB2=m
  2924. +CONFIG_DVB_USB_V2=m
  2925. +CONFIG_DVB_USB_AF9015=m
  2926. +CONFIG_DVB_USB_AF9035=m
  2927. +CONFIG_DVB_USB_ANYSEE=m
  2928. +CONFIG_DVB_USB_AU6610=m
  2929. +CONFIG_DVB_USB_AZ6007=m
  2930. +CONFIG_DVB_USB_CE6230=m
  2931. +CONFIG_DVB_USB_EC168=m
  2932. +CONFIG_DVB_USB_GL861=m
  2933. +CONFIG_DVB_USB_LME2510=m
  2934. +CONFIG_DVB_USB_MXL111SF=m
  2935. +CONFIG_DVB_USB_RTL28XXU=m
  2936. +CONFIG_DVB_USB_DVBSKY=m
  2937. +CONFIG_DVB_USB_ZD1301=m
  2938. +CONFIG_DVB_TTUSB_BUDGET=m
  2939. +CONFIG_DVB_TTUSB_DEC=m
  2940. +CONFIG_SMS_USB_DRV=m
  2941. +CONFIG_DVB_B2C2_FLEXCOP_USB=m
  2942. +CONFIG_DVB_AS102=m
  2943. +CONFIG_VIDEO_EM28XX=m
  2944. +CONFIG_VIDEO_EM28XX_V4L2=m
  2945. +CONFIG_VIDEO_EM28XX_ALSA=m
  2946. +CONFIG_VIDEO_EM28XX_DVB=m
  2947. +CONFIG_USB_AIRSPY=m
  2948. +CONFIG_USB_HACKRF=m
  2949. +CONFIG_USB_PULSE8_CEC=m
  2950. +CONFIG_USB_RAINSHADOW_CEC=m
  2951. +CONFIG_MEDIA_PCI_SUPPORT=y
  2952. +CONFIG_VIDEO_SOLO6X10=m
  2953. +CONFIG_VIDEO_TW68=m
  2954. +CONFIG_VIDEO_IVTV=m
  2955. +CONFIG_VIDEO_IVTV_ALSA=m
  2956. +CONFIG_VIDEO_FB_IVTV=m
  2957. +CONFIG_VIDEO_HEXIUM_GEMINI=m
  2958. +CONFIG_VIDEO_HEXIUM_ORION=m
  2959. +CONFIG_VIDEO_MXB=m
  2960. +CONFIG_VIDEO_DT3155=m
  2961. +CONFIG_VIDEO_CX18=m
  2962. +CONFIG_VIDEO_CX18_ALSA=m
  2963. +CONFIG_VIDEO_CX23885=m
  2964. +CONFIG_MEDIA_ALTERA_CI=m
  2965. +CONFIG_VIDEO_CX25821=m
  2966. +CONFIG_VIDEO_CX25821_ALSA=m
  2967. +CONFIG_VIDEO_CX88=m
  2968. +CONFIG_VIDEO_CX88_ALSA=m
  2969. +CONFIG_VIDEO_CX88_BLACKBIRD=m
  2970. +CONFIG_VIDEO_CX88_DVB=m
  2971. +CONFIG_VIDEO_BT848=m
  2972. +CONFIG_DVB_BT8XX=m
  2973. +CONFIG_VIDEO_SAA7134=m
  2974. +CONFIG_VIDEO_SAA7134_ALSA=m
  2975. +CONFIG_VIDEO_SAA7134_DVB=m
  2976. +CONFIG_VIDEO_SAA7134_GO7007=m
  2977. +CONFIG_VIDEO_SAA7164=m
  2978. +CONFIG_DVB_AV7110=m
  2979. +CONFIG_DVB_BUDGET_CORE=m
  2980. +CONFIG_DVB_BUDGET=m
  2981. +CONFIG_DVB_BUDGET_CI=m
  2982. +CONFIG_DVB_BUDGET_AV=m
  2983. +CONFIG_DVB_BUDGET_PATCH=m
  2984. +CONFIG_DVB_B2C2_FLEXCOP_PCI=m
  2985. +CONFIG_DVB_PLUTO2=m
  2986. +CONFIG_DVB_DM1105=m
  2987. +CONFIG_DVB_PT1=m
  2988. +CONFIG_DVB_PT3=m
  2989. +CONFIG_MANTIS_CORE=m
  2990. +CONFIG_DVB_MANTIS=m
  2991. +CONFIG_DVB_HOPPER=m
  2992. +CONFIG_DVB_NGENE=m
  2993. +CONFIG_DVB_DDBRIDGE=m
  2994. +CONFIG_DVB_SMIPCIE=m
  2995. +CONFIG_V4L_PLATFORM_DRIVERS=y
  2996. +CONFIG_V4L_MEM2MEM_DRIVERS=y
  2997. +CONFIG_VIDEO_ROCKCHIP_RGA=m
  2998. +CONFIG_SMS_SDIO_DRV=m
  2999. +CONFIG_RADIO_SI470X=m
  3000. +CONFIG_USB_SI470X=m
  3001. +CONFIG_I2C_SI470X=m
  3002. +CONFIG_RADIO_SI4713=m
  3003. +CONFIG_USB_SI4713=m
  3004. +CONFIG_PLATFORM_SI4713=m
  3005. +CONFIG_USB_MR800=m
  3006. +CONFIG_USB_DSBR=m
  3007. +CONFIG_RADIO_MAXIRADIO=m
  3008. +CONFIG_RADIO_SHARK=m
  3009. +CONFIG_RADIO_SHARK2=m
  3010. +CONFIG_USB_KEENE=m
  3011. +CONFIG_USB_RAREMONO=m
  3012. +CONFIG_USB_MA901=m
  3013. +CONFIG_RADIO_TEA5764=m
  3014. +CONFIG_RADIO_SAA7706H=m
  3015. +CONFIG_RADIO_TEF6862=m
  3016. +CONFIG_RADIO_WL1273=m
  3017. +CONFIG_DRM=m
  3018. +CONFIG_DRM_LOAD_EDID_FIRMWARE=y
  3019. +CONFIG_DRM_I2C_NXP_TDA998X=m
  3020. +CONFIG_DRM_HDLCD=m
  3021. +CONFIG_DRM_MALI_DISPLAY=m
  3022. +CONFIG_DRM_RADEON=m
  3023. +CONFIG_DRM_RADEON_USERPTR=y
  3024. +CONFIG_DRM_AMDGPU=m
  3025. +CONFIG_DRM_NOUVEAU=m
  3026. +CONFIG_DRM_VGEM=m
  3027. +CONFIG_DRM_ROCKCHIP=m
  3028. +CONFIG_ROCKCHIP_ANALOGIX_DP=y
  3029. +CONFIG_ROCKCHIP_CDN_DP=y
  3030. +CONFIG_ROCKCHIP_DW_HDMI=y
  3031. +CONFIG_ROCKCHIP_DW_MIPI_DSI=y
  3032. +CONFIG_ROCKCHIP_INNO_HDMI=y
  3033. +CONFIG_ROCKCHIP_LVDS=y
  3034. +CONFIG_ROCKCHIP_RGB=y
  3035. +CONFIG_DRM_UDL=m
  3036. +CONFIG_DRM_AST=m
  3037. +CONFIG_DRM_MGAG200=m
  3038. +CONFIG_DRM_CIRRUS_QEMU=m
  3039. +CONFIG_DRM_QXL=m
  3040. +CONFIG_DRM_BOCHS=m
  3041. +CONFIG_DRM_VIRTIO_GPU=m
  3042. +CONFIG_DRM_PANEL_SIMPLE=m
  3043. +CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=m
  3044. +CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m
  3045. +CONFIG_DRM_NXP_PTN3460=m
  3046. +CONFIG_DRM_PARADE_PS8622=m
  3047. +CONFIG_DRM_SIL_SII8620=m
  3048. +CONFIG_DRM_SII902X=m
  3049. +CONFIG_DRM_TOSHIBA_TC358767=m
  3050. +CONFIG_DRM_TI_TFP410=m
  3051. +CONFIG_DRM_ANALOGIX_ANX78XX=m
  3052. +CONFIG_DRM_I2C_ADV7511=m
  3053. +CONFIG_DRM_I2C_ADV7511_AUDIO=y
  3054. +CONFIG_DRM_DW_HDMI_CEC=m
  3055. +CONFIG_DRM_HISI_KIRIN=m
  3056. +CONFIG_DRM_PL111=m
  3057. +CONFIG_DRM_PANFROST=m
  3058. +CONFIG_FB=y
  3059. +CONFIG_FIRMWARE_EDID=y
  3060. +CONFIG_FB_TILEBLITTING=y
  3061. +CONFIG_FB_UDL=m
  3062. +CONFIG_FB_VIRTUAL=m
  3063. +CONFIG_FB_SIMPLE=y
  3064. +CONFIG_FB_SSD1307=m
  3065. +CONFIG_LCD_CLASS_DEVICE=m
  3066. +CONFIG_LCD_PLATFORM=m
  3067. +CONFIG_BACKLIGHT_CLASS_DEVICE=y
  3068. +CONFIG_BACKLIGHT_GENERIC=m
  3069. +CONFIG_BACKLIGHT_PWM=m
  3070. +CONFIG_BACKLIGHT_LP855X=m
  3071. +CONFIG_BACKLIGHT_GPIO=m
  3072. +CONFIG_FRAMEBUFFER_CONSOLE=y
  3073. +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
  3074. +CONFIG_SOUND=y
  3075. +CONFIG_SND=y
  3076. +CONFIG_SND_OSSEMUL=y
  3077. +CONFIG_SND_MIXER_OSS=m
  3078. +CONFIG_SND_PCM_OSS=m
  3079. +CONFIG_SND_HRTIMER=m
  3080. +# CONFIG_SND_SUPPORT_OLD_API is not set
  3081. +CONFIG_SND_VERBOSE_PRINTK=y
  3082. +CONFIG_SND_DEBUG=y
  3083. +CONFIG_SND_DEBUG_VERBOSE=y
  3084. +CONFIG_SND_SEQUENCER=m
  3085. +CONFIG_SND_SEQ_DUMMY=m
  3086. +CONFIG_SND_SEQUENCER_OSS=m
  3087. +CONFIG_SND_DUMMY=m
  3088. +CONFIG_SND_ALOOP=m
  3089. +CONFIG_SND_VIRMIDI=m
  3090. +CONFIG_SND_MTPAV=m
  3091. +CONFIG_SND_SERIAL_U16550=m
  3092. +CONFIG_SND_MPU401=m
  3093. +CONFIG_SND_AC97_POWER_SAVE=y
  3094. +CONFIG_SND_AD1889=m
  3095. +CONFIG_SND_ATIIXP=m
  3096. +CONFIG_SND_ATIIXP_MODEM=m
  3097. +CONFIG_SND_AU8810=m
  3098. +CONFIG_SND_AU8820=m
  3099. +CONFIG_SND_AU8830=m
  3100. +CONFIG_SND_BT87X=m
  3101. +CONFIG_SND_CA0106=m
  3102. +CONFIG_SND_CMIPCI=m
  3103. +CONFIG_SND_OXYGEN=m
  3104. +CONFIG_SND_CS4281=m
  3105. +CONFIG_SND_CS46XX=m
  3106. +CONFIG_SND_CTXFI=m
  3107. +CONFIG_SND_DARLA20=m
  3108. +CONFIG_SND_GINA20=m
  3109. +CONFIG_SND_LAYLA20=m
  3110. +CONFIG_SND_DARLA24=m
  3111. +CONFIG_SND_GINA24=m
  3112. +CONFIG_SND_LAYLA24=m
  3113. +CONFIG_SND_MONA=m
  3114. +CONFIG_SND_MIA=m
  3115. +CONFIG_SND_ECHO3G=m
  3116. +CONFIG_SND_INDIGO=m
  3117. +CONFIG_SND_INDIGOIO=m
  3118. +CONFIG_SND_INDIGODJ=m
  3119. +CONFIG_SND_INDIGOIOX=m
  3120. +CONFIG_SND_INDIGODJX=m
  3121. +CONFIG_SND_ENS1370=m
  3122. +CONFIG_SND_ENS1371=m
  3123. +CONFIG_SND_FM801=m
  3124. +CONFIG_SND_FM801_TEA575X_BOOL=y
  3125. +CONFIG_SND_HDSP=m
  3126. +CONFIG_SND_HDSPM=m
  3127. +CONFIG_SND_ICE1724=m
  3128. +CONFIG_SND_INTEL8X0=m
  3129. +CONFIG_SND_INTEL8X0M=m
  3130. +CONFIG_SND_KORG1212=m
  3131. +CONFIG_SND_LOLA=m
  3132. +CONFIG_SND_LX6464ES=m
  3133. +CONFIG_SND_MIXART=m
  3134. +CONFIG_SND_NM256=m
  3135. +CONFIG_SND_PCXHR=m
  3136. +CONFIG_SND_RIPTIDE=m
  3137. +CONFIG_SND_RME32=m
  3138. +CONFIG_SND_RME96=m
  3139. +CONFIG_SND_RME9652=m
  3140. +CONFIG_SND_VIA82XX=m
  3141. +CONFIG_SND_VIA82XX_MODEM=m
  3142. +CONFIG_SND_VIRTUOSO=m
  3143. +CONFIG_SND_VX222=m
  3144. +CONFIG_SND_YMFPCI=m
  3145. +CONFIG_SND_HDA_INTEL=m
  3146. +CONFIG_SND_HDA_HWDEP=y
  3147. +CONFIG_SND_HDA_INPUT_BEEP=y
  3148. +CONFIG_SND_HDA_INPUT_BEEP_MODE=0
  3149. +CONFIG_SND_HDA_PATCH_LOADER=y
  3150. +CONFIG_SND_HDA_CODEC_REALTEK=m
  3151. +CONFIG_SND_HDA_CODEC_ANALOG=m
  3152. +CONFIG_SND_HDA_CODEC_SIGMATEL=m
  3153. +CONFIG_SND_HDA_CODEC_VIA=m
  3154. +CONFIG_SND_HDA_CODEC_HDMI=m
  3155. +CONFIG_SND_HDA_CODEC_CIRRUS=m
  3156. +CONFIG_SND_HDA_CODEC_CONEXANT=m
  3157. +CONFIG_SND_HDA_CODEC_CA0110=m
  3158. +CONFIG_SND_HDA_CODEC_CA0132=m
  3159. +CONFIG_SND_HDA_CODEC_CA0132_DSP=y
  3160. +CONFIG_SND_HDA_CODEC_CMEDIA=m
  3161. +CONFIG_SND_HDA_CODEC_SI3054=m
  3162. +CONFIG_SND_HDA_PREALLOC_SIZE=4096
  3163. +CONFIG_SND_USB_AUDIO=m
  3164. +CONFIG_SND_USB_UA101=m
  3165. +CONFIG_SND_USB_CAIAQ=m
  3166. +CONFIG_SND_USB_CAIAQ_INPUT=y
  3167. +CONFIG_SND_USB_6FIRE=m
  3168. +CONFIG_SND_USB_HIFACE=m
  3169. +CONFIG_SND_USB_POD=m
  3170. +CONFIG_SND_USB_PODHD=m
  3171. +CONFIG_SND_USB_TONEPORT=m
  3172. +CONFIG_SND_USB_VARIAX=m
  3173. +CONFIG_SND_SOC=y
  3174. +CONFIG_SND_SOC_AMD_ACP=m
  3175. +CONFIG_SND_I2S_HI6210_I2S=m
  3176. +CONFIG_SND_SOC_ROCKCHIP=m
  3177. +CONFIG_SND_SOC_ROCKCHIP_PDM=m
  3178. +CONFIG_SND_SOC_ROCKCHIP_SPDIF=m
  3179. +CONFIG_SND_SOC_ROCKCHIP_MAX98090=m
  3180. +CONFIG_SND_SOC_ROCKCHIP_RT5645=m
  3181. +CONFIG_SND_SOC_RK3288_HDMI_ANALOG=m
  3182. +CONFIG_SND_SOC_RK3399_GRU_SOUND=m
  3183. +CONFIG_SND_SOC_CROS_EC_CODEC=m
  3184. +CONFIG_SND_SOC_ES8316=m
  3185. +CONFIG_SND_SOC_MSM8916_WCD_ANALOG=y
  3186. +CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=y
  3187. +CONFIG_SND_SOC_PCM3168A_I2C=m
  3188. +CONFIG_SND_SOC_RK3328=m
  3189. +CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
  3190. +CONFIG_SND_SIMPLE_CARD=m
  3191. +CONFIG_SND_AUDIO_GRAPH_CARD=m
  3192. +CONFIG_HID_BATTERY_STRENGTH=y
  3193. +CONFIG_HIDRAW=y
  3194. +CONFIG_UHID=m
  3195. +CONFIG_HID_A4TECH=m
  3196. +CONFIG_HID_ACCUTOUCH=m
  3197. +CONFIG_HID_ACRUX=m
  3198. +CONFIG_HID_ACRUX_FF=y
  3199. +CONFIG_HID_APPLE=m
  3200. +CONFIG_HID_APPLEIR=m
  3201. +CONFIG_HID_AUREAL=m
  3202. +CONFIG_HID_BELKIN=m
  3203. +CONFIG_HID_BETOP_FF=m
  3204. +CONFIG_HID_CHERRY=m
  3205. +CONFIG_HID_CHICONY=m
  3206. +CONFIG_HID_CORSAIR=m
  3207. +CONFIG_HID_COUGAR=m
  3208. +CONFIG_HID_MACALLY=m
  3209. +CONFIG_HID_PRODIKEYS=m
  3210. +CONFIG_HID_CMEDIA=m
  3211. +CONFIG_HID_CP2112=m
  3212. +CONFIG_HID_CYPRESS=m
  3213. +CONFIG_HID_DRAGONRISE=m
  3214. +CONFIG_DRAGONRISE_FF=y
  3215. +CONFIG_HID_EMS_FF=m
  3216. +CONFIG_HID_ELECOM=m
  3217. +CONFIG_HID_ELO=m
  3218. +CONFIG_HID_EZKEY=m
  3219. +CONFIG_HID_GEMBIRD=m
  3220. +CONFIG_HID_GFRM=m
  3221. +CONFIG_HID_HOLTEK=m
  3222. +CONFIG_HOLTEK_FF=y
  3223. +CONFIG_HID_GT683R=m
  3224. +CONFIG_HID_KEYTOUCH=m
  3225. +CONFIG_HID_KYE=m
  3226. +CONFIG_HID_UCLOGIC=m
  3227. +CONFIG_HID_WALTOP=m
  3228. +CONFIG_HID_VIEWSONIC=m
  3229. +CONFIG_HID_GYRATION=m
  3230. +CONFIG_HID_ICADE=m
  3231. +CONFIG_HID_ITE=m
  3232. +CONFIG_HID_JABRA=m
  3233. +CONFIG_HID_TWINHAN=m
  3234. +CONFIG_HID_KENSINGTON=m
  3235. +CONFIG_HID_LCPOWER=m
  3236. +CONFIG_HID_LENOVO=m
  3237. +CONFIG_HID_LOGITECH=m
  3238. +CONFIG_HID_LOGITECH_DJ=m
  3239. +CONFIG_LOGITECH_FF=y
  3240. +CONFIG_LOGIRUMBLEPAD2_FF=y
  3241. +CONFIG_LOGIG940_FF=y
  3242. +CONFIG_HID_MAGICMOUSE=m
  3243. +CONFIG_HID_MALTRON=m
  3244. +CONFIG_HID_MAYFLASH=m
  3245. +CONFIG_HID_REDRAGON=m
  3246. +CONFIG_HID_MICROSOFT=m
  3247. +CONFIG_HID_MONTEREY=m
  3248. +CONFIG_HID_MULTITOUCH=m
  3249. +CONFIG_HID_NTI=m
  3250. +CONFIG_HID_NTRIG=m
  3251. +CONFIG_HID_ORTEK=m
  3252. +CONFIG_HID_PANTHERLORD=m
  3253. +CONFIG_PANTHERLORD_FF=y
  3254. +CONFIG_HID_PENMOUNT=m
  3255. +CONFIG_HID_PETALYNX=m
  3256. +CONFIG_HID_PICOLCD=m
  3257. +CONFIG_HID_PICOLCD_FB=y
  3258. +CONFIG_HID_PICOLCD_BACKLIGHT=y
  3259. +CONFIG_HID_PICOLCD_LCD=y
  3260. +CONFIG_HID_PICOLCD_LEDS=y
  3261. +CONFIG_HID_PICOLCD_CIR=y
  3262. +CONFIG_HID_PLANTRONICS=m
  3263. +CONFIG_HID_PRIMAX=m
  3264. +CONFIG_HID_RETRODE=m
  3265. +CONFIG_HID_ROCCAT=m
  3266. +CONFIG_HID_SAITEK=m
  3267. +CONFIG_HID_SAMSUNG=m
  3268. +CONFIG_HID_SONY=m
  3269. +CONFIG_SONY_FF=y
  3270. +CONFIG_HID_SPEEDLINK=m
  3271. +CONFIG_HID_STEAM=m
  3272. +CONFIG_HID_STEELSERIES=m
  3273. +CONFIG_HID_SUNPLUS=m
  3274. +CONFIG_HID_RMI=m
  3275. +CONFIG_HID_GREENASIA=m
  3276. +CONFIG_GREENASIA_FF=y
  3277. +CONFIG_HID_SMARTJOYPLUS=m
  3278. +CONFIG_SMARTJOYPLUS_FF=y
  3279. +CONFIG_HID_TIVO=m
  3280. +CONFIG_HID_TOPSEED=m
  3281. +CONFIG_HID_THINGM=m
  3282. +CONFIG_HID_THRUSTMASTER=m
  3283. +CONFIG_THRUSTMASTER_FF=y
  3284. +CONFIG_HID_UDRAW_PS3=m
  3285. +CONFIG_HID_U2FZERO=m
  3286. +CONFIG_HID_WACOM=m
  3287. +CONFIG_HID_WIIMOTE=m
  3288. +CONFIG_HID_XINMO=m
  3289. +CONFIG_HID_ZEROPLUS=m
  3290. +CONFIG_ZEROPLUS_FF=y
  3291. +CONFIG_HID_ZYDACRON=m
  3292. +CONFIG_HID_SENSOR_HUB=m
  3293. +CONFIG_HID_SENSOR_CUSTOM_SENSOR=m
  3294. +CONFIG_HID_ALPS=m
  3295. +CONFIG_HID_PID=y
  3296. +CONFIG_USB_HIDDEV=y
  3297. +CONFIG_I2C_HID=m
  3298. +CONFIG_USB_LED_TRIG=y
  3299. +CONFIG_USB=y
  3300. +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
  3301. +CONFIG_USB_OTG=y
  3302. +CONFIG_USB_MON=y
  3303. +CONFIG_USB_XHCI_HCD=y
  3304. +CONFIG_USB_EHCI_HCD=y
  3305. +CONFIG_USB_EHCI_HCD_PLATFORM=y
  3306. +CONFIG_USB_MAX3421_HCD=y
  3307. +CONFIG_USB_OHCI_HCD=y
  3308. +CONFIG_USB_OHCI_HCD_PLATFORM=y
  3309. +CONFIG_USB_UHCI_HCD=y
  3310. +CONFIG_USB_U132_HCD=m
  3311. +CONFIG_USB_SL811_HCD=m
  3312. +CONFIG_USB_SL811_HCD_ISO=y
  3313. +CONFIG_USB_PRINTER=m
  3314. +CONFIG_USB_TMC=m
  3315. +CONFIG_USB_STORAGE=y
  3316. +CONFIG_USB_STORAGE_REALTEK=y
  3317. +CONFIG_USB_STORAGE_DATAFAB=y
  3318. +CONFIG_USB_STORAGE_FREECOM=y
  3319. +CONFIG_USB_STORAGE_ISD200=y
  3320. +CONFIG_USB_STORAGE_USBAT=y
  3321. +CONFIG_USB_STORAGE_SDDR09=y
  3322. +CONFIG_USB_STORAGE_SDDR55=y
  3323. +CONFIG_USB_STORAGE_JUMPSHOT=y
  3324. +CONFIG_USB_STORAGE_ALAUDA=y
  3325. +CONFIG_USB_STORAGE_ONETOUCH=y
  3326. +CONFIG_USB_STORAGE_KARMA=y
  3327. +CONFIG_USB_STORAGE_CYPRESS_ATACB=y
  3328. +CONFIG_USB_STORAGE_ENE_UB6250=y
  3329. +CONFIG_USB_UAS=y
  3330. +CONFIG_USB_MDC800=m
  3331. +CONFIG_USB_MICROTEK=m
  3332. +CONFIG_USBIP_CORE=m
  3333. +CONFIG_USBIP_VHCI_HCD=m
  3334. +CONFIG_USBIP_HOST=m
  3335. +CONFIG_USBIP_VUDC=m
  3336. +CONFIG_USB_MUSB_HDRC=y
  3337. +CONFIG_USB_DWC3=y
  3338. +CONFIG_USB_DWC3_ULPI=y
  3339. +CONFIG_USB_DWC2=y
  3340. +CONFIG_USB_DWC2_PCI=y
  3341. +CONFIG_USB_CHIPIDEA=y
  3342. +CONFIG_USB_CHIPIDEA_UDC=y
  3343. +CONFIG_USB_CHIPIDEA_HOST=y
  3344. +CONFIG_USB_ISP1760=y
  3345. +CONFIG_USB_SERIAL=y
  3346. +CONFIG_USB_SERIAL_CONSOLE=y
  3347. +CONFIG_USB_SERIAL_GENERIC=y
  3348. +CONFIG_USB_SERIAL_SIMPLE=m
  3349. +CONFIG_USB_SERIAL_AIRCABLE=m
  3350. +CONFIG_USB_SERIAL_ARK3116=m
  3351. +CONFIG_USB_SERIAL_BELKIN=m
  3352. +CONFIG_USB_SERIAL_CH341=m
  3353. +CONFIG_USB_SERIAL_WHITEHEAT=m
  3354. +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
  3355. +CONFIG_USB_SERIAL_CP210X=m
  3356. +CONFIG_USB_SERIAL_CYPRESS_M8=m
  3357. +CONFIG_USB_SERIAL_EMPEG=m
  3358. +CONFIG_USB_SERIAL_FTDI_SIO=m
  3359. +CONFIG_USB_SERIAL_VISOR=m
  3360. +CONFIG_USB_SERIAL_IPAQ=m
  3361. +CONFIG_USB_SERIAL_IR=m
  3362. +CONFIG_USB_SERIAL_EDGEPORT=m
  3363. +CONFIG_USB_SERIAL_EDGEPORT_TI=m
  3364. +CONFIG_USB_SERIAL_F81232=m
  3365. +CONFIG_USB_SERIAL_F8153X=m
  3366. +CONFIG_USB_SERIAL_GARMIN=m
  3367. +CONFIG_USB_SERIAL_IPW=m
  3368. +CONFIG_USB_SERIAL_IUU=m
  3369. +CONFIG_USB_SERIAL_KEYSPAN_PDA=m
  3370. +CONFIG_USB_SERIAL_KEYSPAN=m
  3371. +CONFIG_USB_SERIAL_KLSI=m
  3372. +CONFIG_USB_SERIAL_KOBIL_SCT=m
  3373. +CONFIG_USB_SERIAL_MCT_U232=m
  3374. +CONFIG_USB_SERIAL_METRO=m
  3375. +CONFIG_USB_SERIAL_MOS7720=m
  3376. +CONFIG_USB_SERIAL_MOS7840=m
  3377. +CONFIG_USB_SERIAL_MXUPORT=m
  3378. +CONFIG_USB_SERIAL_NAVMAN=m
  3379. +CONFIG_USB_SERIAL_PL2303=m
  3380. +CONFIG_USB_SERIAL_OTI6858=m
  3381. +CONFIG_USB_SERIAL_QCAUX=m
  3382. +CONFIG_USB_SERIAL_QUALCOMM=m
  3383. +CONFIG_USB_SERIAL_SPCP8X5=m
  3384. +CONFIG_USB_SERIAL_SAFE=m
  3385. +CONFIG_USB_SERIAL_SAFE_PADDED=y
  3386. +CONFIG_USB_SERIAL_SIERRAWIRELESS=m
  3387. +CONFIG_USB_SERIAL_SYMBOL=m
  3388. +CONFIG_USB_SERIAL_TI=m
  3389. +CONFIG_USB_SERIAL_CYBERJACK=m
  3390. +CONFIG_USB_SERIAL_XIRCOM=m
  3391. +CONFIG_USB_SERIAL_OPTION=m
  3392. +CONFIG_USB_SERIAL_OMNINET=m
  3393. +CONFIG_USB_SERIAL_OPTICON=m
  3394. +CONFIG_USB_SERIAL_XSENS_MT=m
  3395. +CONFIG_USB_SERIAL_WISHBONE=m
  3396. +CONFIG_USB_SERIAL_SSU100=m
  3397. +CONFIG_USB_SERIAL_QT2=m
  3398. +CONFIG_USB_SERIAL_UPD78F0730=m
  3399. +CONFIG_USB_SERIAL_DEBUG=m
  3400. +CONFIG_USB_EMI62=m
  3401. +CONFIG_USB_EMI26=m
  3402. +CONFIG_USB_ADUTUX=m
  3403. +CONFIG_USB_SEVSEG=m
  3404. +CONFIG_USB_LEGOTOWER=m
  3405. +CONFIG_USB_LCD=m
  3406. +CONFIG_USB_IDMOUSE=m
  3407. +CONFIG_USB_FTDI_ELAN=m
  3408. +CONFIG_USB_APPLEDISPLAY=m
  3409. +CONFIG_USB_SISUSBVGA=m
  3410. +CONFIG_USB_SISUSBVGA_CON=y
  3411. +CONFIG_USB_LD=m
  3412. +CONFIG_USB_TRANCEVIBRATOR=m
  3413. +CONFIG_USB_IOWARRIOR=m
  3414. +CONFIG_USB_ISIGHTFW=m
  3415. +CONFIG_USB_YUREX=m
  3416. +CONFIG_USB_HSIC_USB3503=y
  3417. +CONFIG_USB_HSIC_USB4604=y
  3418. +CONFIG_USB_CHAOSKEY=m
  3419. +CONFIG_USB_ATM=m
  3420. +CONFIG_USB_CXACRU=m
  3421. +CONFIG_USB_UEAGLEATM=m
  3422. +CONFIG_USB_XUSBATM=m
  3423. +CONFIG_USB_GPIO_VBUS=y
  3424. +CONFIG_USB_ISP1301=y
  3425. +CONFIG_USB_ULPI=y
  3426. +CONFIG_USB_GADGET=y
  3427. +CONFIG_USB_GADGET_VBUS_DRAW=500
  3428. +CONFIG_USB_CONFIGFS=m
  3429. +CONFIG_USB_CONFIGFS_SERIAL=y
  3430. +CONFIG_USB_CONFIGFS_ACM=y
  3431. +CONFIG_USB_CONFIGFS_OBEX=y
  3432. +CONFIG_USB_CONFIGFS_NCM=y
  3433. +CONFIG_USB_CONFIGFS_ECM=y
  3434. +CONFIG_USB_CONFIGFS_ECM_SUBSET=y
  3435. +CONFIG_USB_CONFIGFS_RNDIS=y
  3436. +CONFIG_USB_CONFIGFS_EEM=y
  3437. +CONFIG_USB_CONFIGFS_MASS_STORAGE=y
  3438. +CONFIG_USB_CONFIGFS_F_FS=y
  3439. +CONFIG_USB_CONFIGFS_F_UAC1=y
  3440. +CONFIG_USB_CONFIGFS_F_UAC1_LEGACY=y
  3441. +CONFIG_USB_CONFIGFS_F_UAC2=y
  3442. +CONFIG_USB_CONFIGFS_F_MIDI=y
  3443. +CONFIG_USB_CONFIGFS_F_HID=y
  3444. +CONFIG_USB_CONFIGFS_F_UVC=y
  3445. +CONFIG_USB_CONFIGFS_F_PRINTER=y
  3446. +CONFIG_USB_CONFIGFS_F_TCM=y
  3447. +CONFIG_USB_AUDIO=m
  3448. +CONFIG_GADGET_UAC1=y
  3449. +CONFIG_USB_ETH=m
  3450. +CONFIG_USB_ETH_EEM=y
  3451. +CONFIG_USB_G_NCM=m
  3452. +CONFIG_USB_GADGETFS=m
  3453. +CONFIG_USB_FUNCTIONFS=m
  3454. +CONFIG_USB_FUNCTIONFS_ETH=y
  3455. +CONFIG_USB_FUNCTIONFS_RNDIS=y
  3456. +CONFIG_USB_FUNCTIONFS_GENERIC=y
  3457. +CONFIG_USB_MASS_STORAGE=m
  3458. +CONFIG_USB_GADGET_TARGET=m
  3459. +CONFIG_USB_G_SERIAL=m
  3460. +CONFIG_USB_MIDI_GADGET=m
  3461. +CONFIG_USB_G_PRINTER=m
  3462. +CONFIG_USB_CDC_COMPOSITE=m
  3463. +CONFIG_USB_G_ACM_MS=m
  3464. +CONFIG_USB_G_MULTI=m
  3465. +CONFIG_USB_G_MULTI_CDC=y
  3466. +CONFIG_USB_G_HID=m
  3467. +CONFIG_USB_G_WEBCAM=m
  3468. +CONFIG_TYPEC=y
  3469. +CONFIG_TYPEC_TCPM=y
  3470. +CONFIG_TYPEC_TCPCI=y
  3471. +CONFIG_TYPEC_FUSB302=y
  3472. +CONFIG_TYPEC_DP_ALTMODE=y
  3473. +CONFIG_MMC=y
  3474. +CONFIG_PWRSEQ_SD8787=m
  3475. +CONFIG_MMC_BLOCK_MINORS=32
  3476. +CONFIG_SDIO_UART=m
  3477. +CONFIG_MMC_ARMMMCI=y
  3478. +# CONFIG_MMC_STM32_SDMMC is not set
  3479. +CONFIG_MMC_SDHCI=y
  3480. +CONFIG_MMC_SDHCI_PCI=y
  3481. +CONFIG_MMC_SDHCI_ACPI=y
  3482. +CONFIG_MMC_SDHCI_PLTFM=y
  3483. +CONFIG_MMC_SDHCI_OF_ARASAN=y
  3484. +CONFIG_MMC_SDHCI_OF_AT91=y
  3485. +CONFIG_MMC_SDHCI_CADENCE=y
  3486. +CONFIG_MMC_SDHCI_F_SDH30=y
  3487. +CONFIG_MMC_TIFM_SD=y
  3488. +CONFIG_MMC_SPI=y
  3489. +CONFIG_MMC_CB710=y
  3490. +CONFIG_MMC_VIA_SDMMC=y
  3491. +CONFIG_MMC_DW=y
  3492. +CONFIG_MMC_DW_EXYNOS=y
  3493. +CONFIG_MMC_DW_K3=y
  3494. +CONFIG_MMC_DW_PCI=y
  3495. +CONFIG_MMC_DW_ROCKCHIP=y
  3496. +CONFIG_MMC_VUB300=m
  3497. +CONFIG_MMC_USHC=m
  3498. +CONFIG_MMC_USDHI6ROL0=y
  3499. +CONFIG_MMC_TOSHIBA_PCI=y
  3500. +CONFIG_MMC_MTK=y
  3501. +CONFIG_MMC_SDHCI_XENON=y
  3502. +CONFIG_MEMSTICK=m
  3503. +CONFIG_MSPRO_BLOCK=m
  3504. +CONFIG_MEMSTICK_TIFM_MS=m
  3505. +CONFIG_MEMSTICK_JMICRON_38X=m
  3506. +CONFIG_MEMSTICK_R592=m
  3507. +CONFIG_LEDS_CLASS=y
  3508. +CONFIG_LEDS_CLASS_FLASH=m
  3509. +CONFIG_LEDS_LM3530=m
  3510. +CONFIG_LEDS_GPIO=y
  3511. +CONFIG_LEDS_LP3944=m
  3512. +CONFIG_LEDS_PCA955X=m
  3513. +CONFIG_LEDS_PCA963X=m
  3514. +CONFIG_LEDS_PWM=m
  3515. +CONFIG_LEDS_LT3593=m
  3516. +CONFIG_LEDS_BLINKM=m
  3517. +CONFIG_LEDS_SYSCON=y
  3518. +CONFIG_LEDS_USER=m
  3519. +CONFIG_LEDS_TRIGGER_TIMER=y
  3520. +CONFIG_LEDS_TRIGGER_ONESHOT=y
  3521. +CONFIG_LEDS_TRIGGER_DISK=y
  3522. +CONFIG_LEDS_TRIGGER_MTD=y
  3523. +CONFIG_LEDS_TRIGGER_HEARTBEAT=y
  3524. +CONFIG_LEDS_TRIGGER_BACKLIGHT=y
  3525. +CONFIG_LEDS_TRIGGER_CPU=y
  3526. +CONFIG_LEDS_TRIGGER_ACTIVITY=y
  3527. +CONFIG_LEDS_TRIGGER_GPIO=y
  3528. +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
  3529. +CONFIG_LEDS_TRIGGER_TRANSIENT=y
  3530. +CONFIG_LEDS_TRIGGER_CAMERA=y
  3531. +CONFIG_LEDS_TRIGGER_PANIC=y
  3532. +CONFIG_LEDS_TRIGGER_NETDEV=y
  3533. +CONFIG_LEDS_TRIGGER_PATTERN=m
  3534. +CONFIG_LEDS_TRIGGER_AUDIO=m
  3535. +CONFIG_ACCESSIBILITY=y
  3536. +CONFIG_A11Y_BRAILLE_CONSOLE=y
  3537. +CONFIG_EDAC=y
  3538. +CONFIG_EDAC_XGENE=m
  3539. +CONFIG_RTC_CLASS=y
  3540. +# CONFIG_RTC_SYSTOHC is not set
  3541. +CONFIG_RTC_INTF_DEV_UIE_EMUL=y
  3542. +CONFIG_RTC_DRV_ABX80X=m
  3543. +CONFIG_RTC_DRV_DS1307=m
  3544. +CONFIG_RTC_DRV_DS1374=m
  3545. +CONFIG_RTC_DRV_DS1374_WDT=y
  3546. +CONFIG_RTC_DRV_DS1672=m
  3547. +CONFIG_RTC_DRV_MAX6900=m
  3548. +CONFIG_RTC_DRV_RK808=y
  3549. +CONFIG_RTC_DRV_RS5C372=m
  3550. +CONFIG_RTC_DRV_ISL1208=m
  3551. +CONFIG_RTC_DRV_ISL12022=m
  3552. +CONFIG_RTC_DRV_X1205=m
  3553. +CONFIG_RTC_DRV_PCF8523=m
  3554. +CONFIG_RTC_DRV_PCF85063=m
  3555. +CONFIG_RTC_DRV_PCF85363=m
  3556. +CONFIG_RTC_DRV_PCF8563=m
  3557. +CONFIG_RTC_DRV_PCF8583=m
  3558. +CONFIG_RTC_DRV_M41T80=m
  3559. +CONFIG_RTC_DRV_M41T80_WDT=y
  3560. +CONFIG_RTC_DRV_BQ32K=m
  3561. +CONFIG_RTC_DRV_FM3130=m
  3562. +CONFIG_RTC_DRV_RX8581=m
  3563. +CONFIG_RTC_DRV_RX8025=m
  3564. +CONFIG_RTC_DRV_EM3027=m
  3565. +CONFIG_RTC_DRV_DS3232=m
  3566. +CONFIG_RTC_DRV_PCF2127=m
  3567. +CONFIG_RTC_DRV_RV3029C2=m
  3568. +CONFIG_RTC_DRV_DS1286=m
  3569. +CONFIG_RTC_DRV_DS1511=m
  3570. +CONFIG_RTC_DRV_DS1553=m
  3571. +CONFIG_RTC_DRV_DS1685_FAMILY=m
  3572. +CONFIG_RTC_DRV_DS1742=m
  3573. +CONFIG_RTC_DRV_DS2404=m
  3574. +CONFIG_RTC_DRV_EFI=y
  3575. +CONFIG_RTC_DRV_STK17TA8=m
  3576. +CONFIG_RTC_DRV_M48T35=m
  3577. +CONFIG_RTC_DRV_M48T59=m
  3578. +CONFIG_RTC_DRV_MSM6242=m
  3579. +CONFIG_RTC_DRV_BQ4802=m
  3580. +CONFIG_RTC_DRV_RP5C01=m
  3581. +CONFIG_RTC_DRV_V3020=m
  3582. +CONFIG_RTC_DRV_CROS_EC=y
  3583. +CONFIG_RTC_DRV_PL031=y
  3584. +CONFIG_MV_XOR_V2=y
  3585. +CONFIG_PL330_DMA=y
  3586. +CONFIG_QCOM_HIDMA_MGMT=y
  3587. +CONFIG_QCOM_HIDMA=y
  3588. +CONFIG_DW_DMAC=m
  3589. +CONFIG_DW_DMAC_PCI=m
  3590. +CONFIG_ASYNC_TX_DMA=y
  3591. +CONFIG_AUXDISPLAY=y
  3592. +CONFIG_UIO_CIF=m
  3593. +CONFIG_UIO_AEC=m
  3594. +CONFIG_UIO_SERCOS3=m
  3595. +CONFIG_UIO_PCI_GENERIC=m
  3596. +CONFIG_VFIO=m
  3597. +CONFIG_VFIO_PCI=m
  3598. +CONFIG_VFIO_PLATFORM=m
  3599. +CONFIG_VFIO_AMBA=m
  3600. +CONFIG_VFIO_PLATFORM_CALXEDAXGMAC_RESET=m
  3601. +CONFIG_VFIO_PLATFORM_AMDXGBE_RESET=m
  3602. +CONFIG_VIRTIO_PCI=y
  3603. +CONFIG_VIRTIO_BALLOON=m
  3604. +CONFIG_VIRTIO_INPUT=m
  3605. +CONFIG_VIRTIO_MMIO=m
  3606. +CONFIG_STAGING=y
  3607. +CONFIG_PRISM2_USB=m
  3608. +CONFIG_RTL8192U=m
  3609. +CONFIG_RTLLIB=m
  3610. +CONFIG_RTL8192E=m
  3611. +CONFIG_R8712U=m
  3612. +CONFIG_R8188EU=m
  3613. +CONFIG_ADIS16203=m
  3614. +CONFIG_ADIS16240=m
  3615. +CONFIG_AD7816=m
  3616. +CONFIG_AD7192=m
  3617. +CONFIG_AD7280=m
  3618. +CONFIG_ADT7316=m
  3619. +CONFIG_ADT7316_I2C=m
  3620. +CONFIG_AD7150=m
  3621. +CONFIG_AD7746=m
  3622. +CONFIG_AD9832=m
  3623. +CONFIG_AD9834=m
  3624. +CONFIG_AD5933=m
  3625. +CONFIG_ADE7854=m
  3626. +CONFIG_AD2S1210=m
  3627. +CONFIG_STAGING_MEDIA=y
  3628. +CONFIG_VIDEO_HANTRO=y
  3629. +CONFIG_FB_TFT=m
  3630. +CONFIG_FB_TFT_AGM1264K_FL=m
  3631. +CONFIG_FB_TFT_BD663474=m
  3632. +CONFIG_FB_TFT_HX8340BN=m
  3633. +CONFIG_FB_TFT_HX8347D=m
  3634. +CONFIG_FB_TFT_HX8353D=m
  3635. +CONFIG_FB_TFT_HX8357D=m
  3636. +CONFIG_FB_TFT_ILI9163=m
  3637. +CONFIG_FB_TFT_ILI9320=m
  3638. +CONFIG_FB_TFT_ILI9325=m
  3639. +CONFIG_FB_TFT_ILI9340=m
  3640. +CONFIG_FB_TFT_ILI9341=m
  3641. +CONFIG_FB_TFT_ILI9481=m
  3642. +CONFIG_FB_TFT_ILI9486=m
  3643. +CONFIG_FB_TFT_PCD8544=m
  3644. +CONFIG_FB_TFT_RA8875=m
  3645. +CONFIG_FB_TFT_S6D02A1=m
  3646. +CONFIG_FB_TFT_S6D1121=m
  3647. +CONFIG_FB_TFT_SH1106=m
  3648. +CONFIG_FB_TFT_SSD1289=m
  3649. +CONFIG_FB_TFT_SSD1305=m
  3650. +CONFIG_FB_TFT_SSD1306=m
  3651. +CONFIG_FB_TFT_SSD1331=m
  3652. +CONFIG_FB_TFT_SSD1351=m
  3653. +CONFIG_FB_TFT_ST7735R=m
  3654. +CONFIG_FB_TFT_ST7789V=m
  3655. +CONFIG_FB_TFT_TINYLCD=m
  3656. +CONFIG_FB_TFT_TLS8204=m
  3657. +CONFIG_FB_TFT_UC1611=m
  3658. +CONFIG_FB_TFT_UC1701=m
  3659. +CONFIG_FB_TFT_UPD161704=m
  3660. +CONFIG_FB_TFT_WATTEROTT=m
  3661. +CONFIG_USB_WUSB_CBAF=m
  3662. +CONFIG_USB_HWA_HCD=m
  3663. +CONFIG_UWB=m
  3664. +CONFIG_UWB_WHCI=m
  3665. +CONFIG_UWB_I1480U=m
  3666. +# CONFIG_NET_VENDOR_HP is not set
  3667. +CONFIG_MFD_CROS_EC=y
  3668. +CONFIG_CHROMEOS_TBMC=m
  3669. +CONFIG_CROS_EC_I2C=y
  3670. +CONFIG_CROS_EC_RPMSG=m
  3671. +CONFIG_CROS_EC_SPI=y
  3672. +CONFIG_CROS_KBD_LED_BACKLIGHT=y
  3673. +CONFIG_CROS_EC_LIGHTBAR=m
  3674. +CONFIG_CROS_EC_VBC=m
  3675. +CONFIG_CROS_EC_DEBUGFS=m
  3676. +CONFIG_CROS_EC_SYSFS=m
  3677. +CONFIG_COMMON_CLK_VERSATILE=y
  3678. +CONFIG_CLK_SP810=y
  3679. +CONFIG_CLK_VEXPRESS_OSC=y
  3680. +CONFIG_COMMON_CLK_RK808=y
  3681. +CONFIG_COMMON_CLK_SCPI=y
  3682. +CONFIG_COMMON_CLK_XGENE=y
  3683. +CONFIG_COMMON_CLK_PWM=y
  3684. +CONFIG_HWSPINLOCK=y
  3685. +CONFIG_ARM_MHU=y
  3686. +CONFIG_PLATFORM_MHU=y
  3687. +CONFIG_ROCKCHIP_MBOX=y
  3688. +CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y
  3689. +CONFIG_ROCKCHIP_IOMMU=y
  3690. +CONFIG_ARM_SMMU=y
  3691. +CONFIG_ARM_SMMU_V3=y
  3692. +CONFIG_REMOTEPROC=y
  3693. +CONFIG_RPMSG_CHAR=y
  3694. +CONFIG_RPMSG_QCOM_GLINK_RPM=y
  3695. +CONFIG_ROCKCHIP_PM_DOMAINS=y
  3696. +CONFIG_ROCKCHIP_SUSPEND_MODE=y
  3697. +CONFIG_DEVFREQ_GOV_PERFORMANCE=y
  3698. +CONFIG_ARM_RK3399_DMC_DEVFREQ=y
  3699. +CONFIG_EXTCON_ADC_JACK=m
  3700. +CONFIG_EXTCON_GPIO=y
  3701. +CONFIG_EXTCON_USB_GPIO=y
  3702. +CONFIG_EXTCON_USBC_CROS_EC=y
  3703. +CONFIG_MEMORY=y
  3704. +CONFIG_IIO=y
  3705. +CONFIG_IIO_BUFFER_CB=y
  3706. +CONFIG_IIO_BUFFER_HW_CONSUMER=m
  3707. +CONFIG_IIO_SW_DEVICE=m
  3708. +CONFIG_IIO_SW_TRIGGER=m
  3709. +CONFIG_ADIS16201=m
  3710. +CONFIG_ADIS16209=m
  3711. +CONFIG_ADXL345_I2C=m
  3712. +CONFIG_ADXL345_SPI=m
  3713. +CONFIG_ADXL372_SPI=m
  3714. +CONFIG_ADXL372_I2C=m
  3715. +CONFIG_BMA180=m
  3716. +CONFIG_BMA220=m
  3717. +CONFIG_BMC150_ACCEL=m
  3718. +CONFIG_DA280=m
  3719. +CONFIG_DA311=m
  3720. +CONFIG_DMARD06=m
  3721. +CONFIG_DMARD09=m
  3722. +CONFIG_DMARD10=m
  3723. +CONFIG_HID_SENSOR_ACCEL_3D=m
  3724. +CONFIG_IIO_CROS_EC_ACCEL_LEGACY=m
  3725. +CONFIG_IIO_ST_ACCEL_3AXIS=m
  3726. +CONFIG_KXSD9=m
  3727. +CONFIG_KXCJK1013=m
  3728. +CONFIG_MC3230=m
  3729. +CONFIG_MMA7455_I2C=m
  3730. +CONFIG_MMA7455_SPI=m
  3731. +CONFIG_MMA7660=m
  3732. +CONFIG_MMA8452=m
  3733. +CONFIG_MMA9551=m
  3734. +CONFIG_MMA9553=m
  3735. +CONFIG_MXC4005=m
  3736. +CONFIG_MXC6255=m
  3737. +CONFIG_SCA3000=m
  3738. +CONFIG_STK8312=m
  3739. +CONFIG_STK8BA50=m
  3740. +CONFIG_AD7124=m
  3741. +CONFIG_AD7266=m
  3742. +CONFIG_AD7291=m
  3743. +CONFIG_AD7298=m
  3744. +CONFIG_AD7476=m
  3745. +CONFIG_AD7606_IFACE_PARALLEL=m
  3746. +CONFIG_AD7606_IFACE_SPI=m
  3747. +CONFIG_AD7766=m
  3748. +CONFIG_AD7768_1=m
  3749. +CONFIG_AD7780=m
  3750. +CONFIG_AD7791=m
  3751. +CONFIG_AD7793=m
  3752. +CONFIG_AD7887=m
  3753. +CONFIG_AD7923=m
  3754. +CONFIG_AD7949=m
  3755. +CONFIG_AD799X=m
  3756. +CONFIG_AXP20X_ADC=m
  3757. +CONFIG_AXP288_ADC=m
  3758. +CONFIG_CC10001_ADC=m
  3759. +CONFIG_ENVELOPE_DETECTOR=m
  3760. +CONFIG_HI8435=m
  3761. +CONFIG_HX711=m
  3762. +CONFIG_INA2XX_ADC=m
  3763. +CONFIG_LTC2471=m
  3764. +CONFIG_LTC2485=m
  3765. +CONFIG_LTC2497=m
  3766. +CONFIG_MAX1027=m
  3767. +CONFIG_MAX11100=m
  3768. +CONFIG_MAX1118=m
  3769. +CONFIG_MAX1363=m
  3770. +CONFIG_MAX9611=m
  3771. +CONFIG_MCP320X=m
  3772. +CONFIG_MCP3422=m
  3773. +CONFIG_MCP3911=m
  3774. +CONFIG_NAU7802=m
  3775. +CONFIG_QCOM_SPMI_IADC=m
  3776. +CONFIG_QCOM_SPMI_VADC=y
  3777. +CONFIG_QCOM_SPMI_ADC5=m
  3778. +CONFIG_ROCKCHIP_SARADC=m
  3779. +CONFIG_SD_ADC_MODULATOR=m
  3780. +CONFIG_TI_ADC081C=m
  3781. +CONFIG_TI_ADC0832=m
  3782. +CONFIG_TI_ADC084S021=m
  3783. +CONFIG_TI_ADC12138=m
  3784. +CONFIG_TI_ADC108S102=m
  3785. +CONFIG_TI_ADC128S052=m
  3786. +CONFIG_TI_ADC161S626=m
  3787. +CONFIG_TI_ADS1015=m
  3788. +CONFIG_TI_ADS7950=m
  3789. +CONFIG_TI_ADS8344=m
  3790. +CONFIG_TI_ADS8688=m
  3791. +CONFIG_TI_ADS124S08=m
  3792. +CONFIG_TI_TLC4541=m
  3793. +CONFIG_VF610_ADC=m
  3794. +CONFIG_VIPERBOARD_ADC=m
  3795. +CONFIG_IIO_RESCALE=m
  3796. +CONFIG_AD8366=m
  3797. +CONFIG_ATLAS_PH_SENSOR=m
  3798. +CONFIG_BME680=m
  3799. +CONFIG_CCS811=m
  3800. +CONFIG_IAQCORE=m
  3801. +CONFIG_PMS7003=m
  3802. +CONFIG_SENSIRION_SGP30=m
  3803. +CONFIG_SPS30=m
  3804. +CONFIG_VZ89X=m
  3805. +CONFIG_IIO_CROS_EC_SENSORS_CORE=m
  3806. +CONFIG_IIO_CROS_EC_SENSORS=m
  3807. +CONFIG_AD5064=m
  3808. +CONFIG_AD5360=m
  3809. +CONFIG_AD5380=m
  3810. +CONFIG_AD5421=m
  3811. +CONFIG_AD5446=m
  3812. +CONFIG_AD5449=m
  3813. +CONFIG_AD5592R=m
  3814. +CONFIG_AD5593R=m
  3815. +CONFIG_AD5504=m
  3816. +CONFIG_AD5624R_SPI=m
  3817. +CONFIG_LTC1660=m
  3818. +CONFIG_LTC2632=m
  3819. +CONFIG_AD5686_SPI=m
  3820. +CONFIG_AD5696_I2C=m
  3821. +CONFIG_AD5755=m
  3822. +CONFIG_AD5758=m
  3823. +CONFIG_AD5761=m
  3824. +CONFIG_AD5764=m
  3825. +CONFIG_AD5791=m
  3826. +CONFIG_AD7303=m
  3827. +CONFIG_AD8801=m
  3828. +CONFIG_DPOT_DAC=m
  3829. +CONFIG_DS4424=m
  3830. +CONFIG_M62332=m
  3831. +CONFIG_MAX517=m
  3832. +CONFIG_MAX5821=m
  3833. +CONFIG_MCP4725=m
  3834. +CONFIG_MCP4922=m
  3835. +CONFIG_TI_DAC082S085=m
  3836. +CONFIG_TI_DAC5571=m
  3837. +CONFIG_TI_DAC7311=m
  3838. +CONFIG_TI_DAC7612=m
  3839. +CONFIG_VF610_DAC=m
  3840. +CONFIG_AD9523=m
  3841. +CONFIG_ADF4350=m
  3842. +CONFIG_ADIS16080=m
  3843. +CONFIG_ADIS16130=m
  3844. +CONFIG_ADIS16136=m
  3845. +CONFIG_ADIS16260=m
  3846. +CONFIG_ADXRS450=m
  3847. +CONFIG_BMG160=m
  3848. +CONFIG_FXAS21002C=m
  3849. +CONFIG_HID_SENSOR_GYRO_3D=m
  3850. +CONFIG_MPU3050_I2C=m
  3851. +CONFIG_IIO_ST_GYRO_3AXIS=m
  3852. +CONFIG_ITG3200=m
  3853. +CONFIG_AFE4403=m
  3854. +CONFIG_AFE4404=m
  3855. +CONFIG_MAX30100=m
  3856. +CONFIG_MAX30102=m
  3857. +CONFIG_AM2315=m
  3858. +CONFIG_DHT11=m
  3859. +CONFIG_HDC100X=m
  3860. +CONFIG_HID_SENSOR_HUMIDITY=m
  3861. +CONFIG_HTS221=m
  3862. +CONFIG_HTU21=m
  3863. +CONFIG_SI7005=m
  3864. +CONFIG_SI7020=m
  3865. +CONFIG_ADIS16400=m
  3866. +CONFIG_ADIS16480=m
  3867. +CONFIG_BMI160_I2C=m
  3868. +CONFIG_BMI160_SPI=m
  3869. +CONFIG_KMX61=m
  3870. +CONFIG_INV_MPU6050_I2C=m
  3871. +CONFIG_INV_MPU6050_SPI=m
  3872. +CONFIG_IIO_ST_LSM6DSX=m
  3873. +CONFIG_ACPI_ALS=m
  3874. +CONFIG_ADJD_S311=m
  3875. +CONFIG_AL3320A=m
  3876. +CONFIG_APDS9300=m
  3877. +CONFIG_APDS9960=m
  3878. +CONFIG_BH1750=m
  3879. +CONFIG_BH1780=m
  3880. +CONFIG_CM32181=m
  3881. +CONFIG_CM3232=m
  3882. +CONFIG_CM3323=m
  3883. +CONFIG_CM3605=m
  3884. +CONFIG_CM36651=m
  3885. +CONFIG_IIO_CROS_EC_LIGHT_PROX=m
  3886. +CONFIG_GP2AP020A00F=m
  3887. +CONFIG_SENSORS_ISL29018=m
  3888. +CONFIG_SENSORS_ISL29028=m
  3889. +CONFIG_ISL29125=m
  3890. +CONFIG_HID_SENSOR_ALS=m
  3891. +CONFIG_HID_SENSOR_PROX=m
  3892. +CONFIG_JSA1212=m
  3893. +CONFIG_RPR0521=m
  3894. +CONFIG_LTR501=m
  3895. +CONFIG_LV0104CS=m
  3896. +CONFIG_MAX44000=m
  3897. +CONFIG_MAX44009=m
  3898. +CONFIG_OPT3001=m
  3899. +CONFIG_PA12203001=m
  3900. +CONFIG_SI1133=m
  3901. +CONFIG_SI1145=m
  3902. +CONFIG_STK3310=m
  3903. +CONFIG_ST_UVIS25=m
  3904. +CONFIG_TCS3414=m
  3905. +CONFIG_TCS3472=m
  3906. +CONFIG_SENSORS_TSL2563=m
  3907. +CONFIG_TSL2583=m
  3908. +CONFIG_TSL2772=m
  3909. +CONFIG_TSL4531=m
  3910. +CONFIG_US5182D=m
  3911. +CONFIG_VCNL4000=m
  3912. +CONFIG_VCNL4035=m
  3913. +CONFIG_VEML6070=m
  3914. +CONFIG_VL6180=m
  3915. +CONFIG_ZOPT2201=m
  3916. +CONFIG_AK8974=m
  3917. +CONFIG_AK09911=m
  3918. +CONFIG_BMC150_MAGN_I2C=m
  3919. +CONFIG_BMC150_MAGN_SPI=m
  3920. +CONFIG_MAG3110=m
  3921. +CONFIG_HID_SENSOR_MAGNETOMETER_3D=m
  3922. +CONFIG_MMC35240=m
  3923. +CONFIG_IIO_ST_MAGN_3AXIS=m
  3924. +CONFIG_SENSORS_HMC5843_I2C=m
  3925. +CONFIG_SENSORS_HMC5843_SPI=m
  3926. +CONFIG_SENSORS_RM3100_I2C=m
  3927. +CONFIG_SENSORS_RM3100_SPI=m
  3928. +CONFIG_IIO_MUX=y
  3929. +CONFIG_HID_SENSOR_INCLINOMETER_3D=m
  3930. +CONFIG_HID_SENSOR_DEVICE_ROTATION=m
  3931. +CONFIG_IIO_HRTIMER_TRIGGER=m
  3932. +CONFIG_IIO_INTERRUPT_TRIGGER=m
  3933. +CONFIG_IIO_TIGHTLOOP_TRIGGER=m
  3934. +CONFIG_IIO_SYSFS_TRIGGER=m
  3935. +CONFIG_AD5272=m
  3936. +CONFIG_DS1803=m
  3937. +CONFIG_MAX5481=m
  3938. +CONFIG_MAX5487=m
  3939. +CONFIG_MCP4018=m
  3940. +CONFIG_MCP4131=m
  3941. +CONFIG_MCP4531=m
  3942. +CONFIG_MCP41010=m
  3943. +CONFIG_TPL0102=m
  3944. +CONFIG_LMP91000=m
  3945. +CONFIG_ABP060MG=m
  3946. +CONFIG_BMP280=m
  3947. +CONFIG_IIO_CROS_EC_BARO=m
  3948. +CONFIG_HID_SENSOR_PRESS=m
  3949. +CONFIG_HP03=m
  3950. +CONFIG_MPL115_I2C=m
  3951. +CONFIG_MPL115_SPI=m
  3952. +CONFIG_MPL3115=m
  3953. +CONFIG_MS5611=m
  3954. +CONFIG_MS5611_I2C=m
  3955. +CONFIG_MS5611_SPI=m
  3956. +CONFIG_MS5637=m
  3957. +CONFIG_IIO_ST_PRESS=m
  3958. +CONFIG_T5403=m
  3959. +CONFIG_HP206C=m
  3960. +CONFIG_ZPA2326=m
  3961. +CONFIG_AS3935=m
  3962. +CONFIG_ISL29501=m
  3963. +CONFIG_LIDAR_LITE_V2=m
  3964. +CONFIG_MB1232=m
  3965. +CONFIG_RFD77402=m
  3966. +CONFIG_SRF04=m
  3967. +CONFIG_SX9500=m
  3968. +CONFIG_SRF08=m
  3969. +CONFIG_VL53L0X_I2C=m
  3970. +CONFIG_AD2S90=m
  3971. +CONFIG_AD2S1200=m
  3972. +CONFIG_MAXIM_THERMOCOUPLE=m
  3973. +CONFIG_HID_SENSOR_TEMP=m
  3974. +CONFIG_MLX90614=m
  3975. +CONFIG_MLX90632=m
  3976. +CONFIG_TMP006=m
  3977. +CONFIG_TMP007=m
  3978. +CONFIG_TSYS01=m
  3979. +CONFIG_TSYS02D=m
  3980. +CONFIG_MAX31856=m
  3981. +CONFIG_PWM_CROS_EC=m
  3982. +CONFIG_PWM_ROCKCHIP=y
  3983. +CONFIG_PHY_XGENE=y
  3984. +CONFIG_PHY_QCOM_USB_HS=y
  3985. +CONFIG_PHY_QCOM_USB_HSIC=y
  3986. +CONFIG_PHY_ROCKCHIP_DP=y
  3987. +CONFIG_PHY_ROCKCHIP_EMMC=y
  3988. +CONFIG_PHY_ROCKCHIP_INNO_HDMI=y
  3989. +CONFIG_PHY_ROCKCHIP_INNO_USB2=y
  3990. +CONFIG_PHY_ROCKCHIP_PCIE=y
  3991. +CONFIG_PHY_ROCKCHIP_TYPEC=y
  3992. +CONFIG_POWERCAP=y
  3993. +CONFIG_ARM_CCI_PMU=y
  3994. +CONFIG_ARM_CCN=y
  3995. +CONFIG_HISI_PMU=y
  3996. +CONFIG_LIBNVDIMM=y
  3997. +CONFIG_BLK_DEV_PMEM=m
  3998. +CONFIG_ND_BLK=m
  3999. +CONFIG_ROCKCHIP_EFUSE=y
  4000. +CONFIG_MUX_GPIO=y
  4001. +CONFIG_VALIDATE_FS_PARSER=y
  4002. +CONFIG_EXT4_FS=y
  4003. +CONFIG_EXT4_FS_POSIX_ACL=y
  4004. +CONFIG_EXT4_FS_SECURITY=y
  4005. +CONFIG_REISERFS_FS=m
  4006. +CONFIG_REISERFS_PROC_INFO=y
  4007. +CONFIG_REISERFS_FS_XATTR=y
  4008. +CONFIG_REISERFS_FS_POSIX_ACL=y
  4009. +CONFIG_REISERFS_FS_SECURITY=y
  4010. +CONFIG_JFS_FS=m
  4011. +CONFIG_JFS_POSIX_ACL=y
  4012. +CONFIG_JFS_SECURITY=y
  4013. +CONFIG_XFS_FS=y
  4014. +CONFIG_XFS_QUOTA=y
  4015. +CONFIG_XFS_POSIX_ACL=y
  4016. +CONFIG_GFS2_FS=m
  4017. +CONFIG_GFS2_FS_LOCKING_DLM=y
  4018. +CONFIG_OCFS2_FS=m
  4019. +# CONFIG_OCFS2_FS_STATS is not set
  4020. +# CONFIG_OCFS2_DEBUG_MASKLOG is not set
  4021. +CONFIG_BTRFS_FS=m
  4022. +CONFIG_BTRFS_FS_POSIX_ACL=y
  4023. +CONFIG_NILFS2_FS=m
  4024. +CONFIG_F2FS_FS=y
  4025. +CONFIG_F2FS_FS_SECURITY=y
  4026. +CONFIG_FS_ENCRYPTION=y
  4027. +CONFIG_FANOTIFY=y
  4028. +CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y
  4029. +CONFIG_QUOTA_NETLINK_INTERFACE=y
  4030. +# CONFIG_PRINT_QUOTA_WARNING is not set
  4031. +CONFIG_QFMT_V2=y
  4032. +CONFIG_AUTOFS4_FS=y
  4033. +CONFIG_FUSE_FS=y
  4034. +CONFIG_CUSE=y
  4035. +CONFIG_OVERLAY_FS=m
  4036. +CONFIG_FSCACHE=m
  4037. +CONFIG_FSCACHE_STATS=y
  4038. +CONFIG_FSCACHE_OBJECT_LIST=y
  4039. +CONFIG_CACHEFILES=m
  4040. +CONFIG_ISO9660_FS=m
  4041. +CONFIG_JOLIET=y
  4042. +CONFIG_ZISOFS=y
  4043. +CONFIG_UDF_FS=m
  4044. +CONFIG_MSDOS_FS=y
  4045. +CONFIG_VFAT_FS=y
  4046. +CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
  4047. +CONFIG_NTFS_FS=y
  4048. +CONFIG_NTFS_RW=y
  4049. +CONFIG_PROC_KCORE=y
  4050. +CONFIG_TMPFS=y
  4051. +CONFIG_TMPFS_POSIX_ACL=y
  4052. +CONFIG_HUGETLBFS=y
  4053. +CONFIG_EFIVAR_FS=y
  4054. +CONFIG_AFFS_FS=m
  4055. +CONFIG_ECRYPT_FS=m
  4056. +CONFIG_HFS_FS=m
  4057. +CONFIG_HFSPLUS_FS=m
  4058. +CONFIG_BEFS_FS=m
  4059. +CONFIG_UBIFS_FS=m
  4060. +CONFIG_CRAMFS=m
  4061. +CONFIG_SQUASHFS=m
  4062. +CONFIG_SQUASHFS_XATTR=y
  4063. +CONFIG_SQUASHFS_LZ4=y
  4064. +CONFIG_SQUASHFS_LZO=y
  4065. +CONFIG_SQUASHFS_XZ=y
  4066. +CONFIG_MINIX_FS=m
  4067. +CONFIG_ROMFS_FS=m
  4068. +CONFIG_PSTORE=y
  4069. +CONFIG_PSTORE_RAM=m
  4070. +CONFIG_SYSV_FS=m
  4071. +CONFIG_UFS_FS=m
  4072. +CONFIG_NFS_FS=y
  4073. +# CONFIG_NFS_V2 is not set
  4074. +CONFIG_NFS_V3_ACL=y
  4075. +CONFIG_NFS_V4=y
  4076. +CONFIG_NFS_SWAP=y
  4077. +CONFIG_NFS_V4_1=y
  4078. +CONFIG_NFS_V4_2=y
  4079. +# CONFIG_NFS_DISABLE_UDP_SUPPORT is not set
  4080. +CONFIG_NFSD=m
  4081. +CONFIG_NFSD_V3_ACL=y
  4082. +CONFIG_NFSD_V4=y
  4083. +CONFIG_NFSD_BLOCKLAYOUT=y
  4084. +CONFIG_NFSD_SCSILAYOUT=y
  4085. +CONFIG_NFSD_FLEXFILELAYOUT=y
  4086. +CONFIG_NFSD_V4_SECURITY_LABEL=y
  4087. +CONFIG_SUNRPC_DEBUG=y
  4088. +CONFIG_CEPH_FS=m
  4089. +CONFIG_CEPH_FSCACHE=y
  4090. +CONFIG_CEPH_FS_POSIX_ACL=y
  4091. +CONFIG_CIFS=m
  4092. +CONFIG_CIFS_WEAK_PW_HASH=y
  4093. +CONFIG_CIFS_UPCALL=y
  4094. +CONFIG_CIFS_XATTR=y
  4095. +CONFIG_CIFS_POSIX=y
  4096. +CONFIG_CIFS_DFS_UPCALL=y
  4097. +CONFIG_CIFS_FSCACHE=y
  4098. +CONFIG_CODA_FS=m
  4099. +CONFIG_9P_FS=m
  4100. +CONFIG_9P_FSCACHE=y
  4101. +CONFIG_9P_FS_POSIX_ACL=y
  4102. +CONFIG_9P_FS_SECURITY=y
  4103. +CONFIG_NLS_DEFAULT="utf8"
  4104. +CONFIG_NLS_CODEPAGE_437=y
  4105. +CONFIG_NLS_CODEPAGE_737=m
  4106. +CONFIG_NLS_CODEPAGE_775=m
  4107. +CONFIG_NLS_CODEPAGE_850=m
  4108. +CONFIG_NLS_CODEPAGE_852=m
  4109. +CONFIG_NLS_CODEPAGE_855=m
  4110. +CONFIG_NLS_CODEPAGE_857=m
  4111. +CONFIG_NLS_CODEPAGE_860=m
  4112. +CONFIG_NLS_CODEPAGE_861=m
  4113. +CONFIG_NLS_CODEPAGE_862=m
  4114. +CONFIG_NLS_CODEPAGE_863=m
  4115. +CONFIG_NLS_CODEPAGE_864=m
  4116. +CONFIG_NLS_CODEPAGE_865=m
  4117. +CONFIG_NLS_CODEPAGE_866=m
  4118. +CONFIG_NLS_CODEPAGE_869=m
  4119. +CONFIG_NLS_CODEPAGE_936=m
  4120. +CONFIG_NLS_CODEPAGE_950=m
  4121. +CONFIG_NLS_CODEPAGE_932=m
  4122. +CONFIG_NLS_CODEPAGE_949=m
  4123. +CONFIG_NLS_CODEPAGE_874=m
  4124. +CONFIG_NLS_ISO8859_8=m
  4125. +CONFIG_NLS_CODEPAGE_1250=m
  4126. +CONFIG_NLS_CODEPAGE_1251=m
  4127. +CONFIG_NLS_ASCII=y
  4128. +CONFIG_NLS_ISO8859_1=m
  4129. +CONFIG_NLS_ISO8859_2=m
  4130. +CONFIG_NLS_ISO8859_3=m
  4131. +CONFIG_NLS_ISO8859_4=m
  4132. +CONFIG_NLS_ISO8859_5=m
  4133. +CONFIG_NLS_ISO8859_6=m
  4134. +CONFIG_NLS_ISO8859_7=m
  4135. +CONFIG_NLS_ISO8859_9=m
  4136. +CONFIG_NLS_ISO8859_13=m
  4137. +CONFIG_NLS_ISO8859_14=m
  4138. +CONFIG_NLS_ISO8859_15=m
  4139. +CONFIG_NLS_KOI8_R=m
  4140. +CONFIG_NLS_KOI8_U=m
  4141. +CONFIG_NLS_MAC_ROMAN=m
  4142. +CONFIG_NLS_MAC_CELTIC=m
  4143. +CONFIG_NLS_MAC_CENTEURO=m
  4144. +CONFIG_NLS_MAC_CROATIAN=m
  4145. +CONFIG_NLS_MAC_CYRILLIC=m
  4146. +CONFIG_NLS_MAC_GAELIC=m
  4147. +CONFIG_NLS_MAC_GREEK=m
  4148. +CONFIG_NLS_MAC_ICELAND=m
  4149. +CONFIG_NLS_MAC_INUIT=m
  4150. +CONFIG_NLS_MAC_ROMANIAN=m
  4151. +CONFIG_NLS_MAC_TURKISH=m
  4152. +CONFIG_DLM=m
  4153. +CONFIG_DLM_DEBUG=y
  4154. +CONFIG_PERSISTENT_KEYRINGS=y
  4155. +CONFIG_BIG_KEYS=y
  4156. +CONFIG_TRUSTED_KEYS=m
  4157. +CONFIG_ENCRYPTED_KEYS=y
  4158. +CONFIG_SECURITY=y
  4159. +CONFIG_SECURITY_NETWORK=y
  4160. +CONFIG_SECURITY_NETWORK_XFRM=y
  4161. +CONFIG_SECURITY_YAMA=y
  4162. +# CONFIG_INTEGRITY is not set
  4163. +CONFIG_LSM="yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor"
  4164. +CONFIG_CRYPTO_USER=m
  4165. +# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set
  4166. +CONFIG_CRYPTO_PCRYPT=m
  4167. +CONFIG_CRYPTO_DH=m
  4168. +CONFIG_CRYPTO_AEGIS128=m
  4169. +CONFIG_CRYPTO_CFB=m
  4170. +CONFIG_CRYPTO_LRW=m
  4171. +CONFIG_CRYPTO_OFB=m
  4172. +CONFIG_CRYPTO_PCBC=m
  4173. +CONFIG_CRYPTO_KEYWRAP=m
  4174. +CONFIG_CRYPTO_ADIANTUM=m
  4175. +CONFIG_CRYPTO_XCBC=m
  4176. +CONFIG_CRYPTO_VMAC=m
  4177. +CONFIG_CRYPTO_RMD128=m
  4178. +CONFIG_CRYPTO_RMD160=m
  4179. +CONFIG_CRYPTO_RMD256=m
  4180. +CONFIG_CRYPTO_RMD320=m
  4181. +CONFIG_CRYPTO_TGR192=m
  4182. +CONFIG_CRYPTO_WP512=m
  4183. +CONFIG_CRYPTO_ANUBIS=m
  4184. +CONFIG_CRYPTO_BLOWFISH=m
  4185. +CONFIG_CRYPTO_CAMELLIA=m
  4186. +CONFIG_CRYPTO_CAST5=m
  4187. +CONFIG_CRYPTO_CAST6=m
  4188. +CONFIG_CRYPTO_FCRYPT=m
  4189. +CONFIG_CRYPTO_KHAZAD=m
  4190. +CONFIG_CRYPTO_SALSA20=m
  4191. +CONFIG_CRYPTO_SEED=m
  4192. +CONFIG_CRYPTO_SERPENT=m
  4193. +CONFIG_CRYPTO_TEA=m
  4194. +CONFIG_CRYPTO_TWOFISH=m
  4195. +CONFIG_CRYPTO_842=m
  4196. +CONFIG_CRYPTO_LZ4=m
  4197. +CONFIG_CRYPTO_LZ4HC=m
  4198. +CONFIG_CRYPTO_ANSI_CPRNG=m
  4199. +CONFIG_CRYPTO_DRBG_HASH=y
  4200. +CONFIG_CRYPTO_DRBG_CTR=y
  4201. +CONFIG_CRYPTO_USER_API_HASH=y
  4202. +CONFIG_CRYPTO_USER_API_SKCIPHER=y
  4203. +CONFIG_CRYPTO_USER_API_RNG=y
  4204. +CONFIG_CRYPTO_USER_API_AEAD=y
  4205. +CONFIG_CRYPTO_DEV_CCP=y
  4206. +CONFIG_CRYPTO_DEV_ROCKCHIP=m
  4207. +CONFIG_CRYPTO_DEV_SAFEXCEL=m
  4208. +CONFIG_CRYPTO_DEV_CCREE=m
  4209. +CONFIG_ASYMMETRIC_KEY_TYPE=y
  4210. +CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
  4211. +CONFIG_X509_CERTIFICATE_PARSER=y
  4212. +CONFIG_PKCS7_MESSAGE_PARSER=y
  4213. +CONFIG_SYSTEM_TRUSTED_KEYRING=y
  4214. +# CONFIG_XZ_DEC_X86 is not set
  4215. +# CONFIG_XZ_DEC_POWERPC is not set
  4216. +# CONFIG_XZ_DEC_IA64 is not set
  4217. +# CONFIG_XZ_DEC_SPARC is not set
  4218. +CONFIG_DMA_CMA=y
  4219. +CONFIG_CMA_SIZE_MBYTES=64
  4220. +CONFIG_PRINTK_TIME=y
  4221. +CONFIG_BOOT_PRINTK_DELAY=y
  4222. +CONFIG_DYNAMIC_DEBUG=y
  4223. +CONFIG_FRAME_WARN=1024
  4224. +CONFIG_STRIP_ASM_SYMS=y
  4225. +CONFIG_DEBUG_SECTION_MISMATCH=y
  4226. +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x0
  4227. +# CONFIG_MAGIC_SYSRQ_SERIAL is not set
  4228. +CONFIG_KGDB=y
  4229. +CONFIG_KGDB_TESTS=y
  4230. +CONFIG_DEBUG_VM=y
  4231. +CONFIG_SOFTLOCKUP_DETECTOR=y
  4232. +CONFIG_SCHEDSTATS=y
  4233. +CONFIG_STACKTRACE=y
  4234. +CONFIG_DEBUG_LIST=y
  4235. +CONFIG_RCU_TORTURE_TEST=m
  4236. +CONFIG_RCU_CPU_STALL_TIMEOUT=60
  4237. +# CONFIG_RCU_TRACE is not set
  4238. +# CONFIG_FTRACE is not set
  4239. +# CONFIG_RUNTIME_TESTING_MENU is not set
  4240. diff -uNr '--exclude=.git' linux-5.6-rc7/Documentation/devicetree/bindings/power/supply/cw2015_battery.txt linux-pinebook-pro_v5.6/Documentation/devicetree/bindings/power/supply/cw2015_battery.txt
  4241. --- linux-5.6-rc7/Documentation/devicetree/bindings/power/supply/cw2015_battery.txt 1969-12-31 16:00:00.000000000 -0800
  4242. +++ linux-pinebook-pro_v5.6/Documentation/devicetree/bindings/power/supply/cw2015_battery.txt 2020-03-23 07:26:32.000000000 -0700
  4243. @@ -0,0 +1,40 @@
  4244. +cw2015_battery
  4245. +~~~~~~~~~~~~~~~~
  4246. +
  4247. +The cellwise CW2015 is a shuntless single cell battery fuel gauge.
  4248. +
  4249. +Required properties :
  4250. + - compatible : "cellwise,cw2015"
  4251. + - reg: i2c address
  4252. +
  4253. +Optional properties :
  4254. + - cellwise,bat-config-info : 64 byte binary battery info blob
  4255. + - cellwise,monitor-interval-ms : Measurement interval in milliseconds
  4256. + - power-supplies: List of phandles from chargers
  4257. + - monitored-battery: phandle of a simpl-battery
  4258. +
  4259. +Example:
  4260. + bat: battery {
  4261. + compatible = "simple-battery";
  4262. + voltage-min-design-microvolt = <3000000>;
  4263. + voltage-max-design-microvolt = <4350000>;
  4264. + charge-full-design-microamp-hours = <9800000>;
  4265. + }
  4266. +
  4267. + cw2015@62 {
  4268. + compatible = "cellwise,cw201x";
  4269. + reg = <0x62>;
  4270. + cellwise,bat-config-info = /bits/ 8 <
  4271. + 0x17 0x67 0x80 0x73 0x6E 0x6C 0x6B 0x63
  4272. + 0x77 0x51 0x5C 0x58 0x50 0x4C 0x48 0x36
  4273. + 0x15 0x0C 0x0C 0x19 0x5B 0x7D 0x6F 0x69
  4274. + 0x69 0x5B 0x0C 0x29 0x20 0x40 0x52 0x59
  4275. + 0x57 0x56 0x54 0x4F 0x3B 0x1F 0x7F 0x17
  4276. + 0x06 0x1A 0x30 0x5A 0x85 0x93 0x96 0x2D
  4277. + 0x48 0x77 0x9C 0xB3 0x80 0x52 0x94 0xCB
  4278. + 0x2F 0x00 0x64 0xA5 0xB5 0x11 0xF0 0x11
  4279. + >;
  4280. + cellwise,monitor-interval-ms = <5000>;
  4281. + power-supplies = <&mains_charger>, <&usb_charger>;
  4282. + monitored-battery = <&bat>;
  4283. + }
  4284. diff -uNr '--exclude=.git' linux-5.6-rc7/Documentation/devicetree/bindings/power/supply/cw2015_battery.yaml linux-pinebook-pro_v5.6/Documentation/devicetree/bindings/power/supply/cw2015_battery.yaml
  4285. --- linux-5.6-rc7/Documentation/devicetree/bindings/power/supply/cw2015_battery.yaml 1969-12-31 16:00:00.000000000 -0800
  4286. +++ linux-pinebook-pro_v5.6/Documentation/devicetree/bindings/power/supply/cw2015_battery.yaml 2020-03-23 07:26:32.000000000 -0700
  4287. @@ -0,0 +1,82 @@
  4288. +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  4289. +%YAML 1.2
  4290. +---
  4291. +$id: http://devicetree.org/schemas/power/supply/cw2015_battery.yaml#
  4292. +$schema: http://devicetree.org/meta-schemas/core.yaml#
  4293. +
  4294. +title: Battery driver for CW2015 shuntless fuel gauge by CellWise.
  4295. +
  4296. +maintainers:
  4297. + - Tobias Schramm <t.schramm@manjaro.org>
  4298. +
  4299. +description: |
  4300. + The driver can utilize information from a simple-battery linked via a
  4301. + phandle in monitored-battery. If specified the driver uses the
  4302. + charge-full-design-microamp-hours property of the battery.
  4303. +
  4304. +properties:
  4305. + compatible:
  4306. + const: cellwise,cw2015
  4307. +
  4308. + reg:
  4309. + maxItems: 1
  4310. +
  4311. + cellwise,battery-profile:
  4312. + description: |
  4313. + This property specifies characteristics of the battery used. The format
  4314. + of this binary blob is kept secret by CellWise. The only way to obtain
  4315. + it is to mail two batteries to a test facility of CellWise and receive
  4316. + back a test report with the binary blob.
  4317. + allOf:
  4318. + - $ref: /schemas/types.yaml#definitions/uint8-array
  4319. + items:
  4320. + - minItems: 64
  4321. + maxItems: 64
  4322. +
  4323. + cellwise,monitor-interval-ms:
  4324. + description:
  4325. + Specifies the interval in milliseconds gauge values are polled at
  4326. + minimum: 250
  4327. +
  4328. + power-supplies:
  4329. + description:
  4330. + Specifies supplies used for charging the battery connected to this gauge
  4331. + allOf:
  4332. + - $ref: /schemas/types.yaml#/definitions/phandle-array
  4333. + - minItems: 1
  4334. + maxItems: 8 # Should be enough
  4335. +
  4336. + monitored-battery:
  4337. + description:
  4338. + Specifies the phandle of a simple-battery connected to this gauge
  4339. + $ref: /schemas/types.yaml#/definitions/phandle
  4340. +
  4341. +required:
  4342. + - compatible
  4343. + - reg
  4344. +
  4345. +examples:
  4346. + - |
  4347. + i2c {
  4348. + #address-cells = <1>;
  4349. + #size-cells = <0>;
  4350. +
  4351. + cw2015@62 {
  4352. + compatible = "cellwise,cw201x";
  4353. + reg = <0x62>;
  4354. + cellwise,battery-profile = /bits/ 8 <
  4355. + 0x17 0x67 0x80 0x73 0x6E 0x6C 0x6B 0x63
  4356. + 0x77 0x51 0x5C 0x58 0x50 0x4C 0x48 0x36
  4357. + 0x15 0x0C 0x0C 0x19 0x5B 0x7D 0x6F 0x69
  4358. + 0x69 0x5B 0x0C 0x29 0x20 0x40 0x52 0x59
  4359. + 0x57 0x56 0x54 0x4F 0x3B 0x1F 0x7F 0x17
  4360. + 0x06 0x1A 0x30 0x5A 0x85 0x93 0x96 0x2D
  4361. + 0x48 0x77 0x9C 0xB3 0x80 0x52 0x94 0xCB
  4362. + 0x2F 0x00 0x64 0xA5 0xB5 0x11 0xF0 0x11
  4363. + >;
  4364. + cellwise,monitor-interval-ms = <5000>;
  4365. + monitored-battery = <&bat>;
  4366. + power-supplies = <&mains_charger>, <&usb_charger>;
  4367. + };
  4368. + };
  4369. +
  4370. diff -uNr '--exclude=.git' linux-5.6-rc7/Documentation/devicetree/bindings/soc/rockchip/rockchip-pm-config.txt linux-pinebook-pro_v5.6/Documentation/devicetree/bindings/soc/rockchip/rockchip-pm-config.txt
  4371. --- linux-5.6-rc7/Documentation/devicetree/bindings/soc/rockchip/rockchip-pm-config.txt 1969-12-31 16:00:00.000000000 -0800
  4372. +++ linux-pinebook-pro_v5.6/Documentation/devicetree/bindings/soc/rockchip/rockchip-pm-config.txt 2020-03-23 07:26:32.000000000 -0700
  4373. @@ -0,0 +1,39 @@
  4374. +* the suspend mode config
  4375. +
  4376. +- compatible: "rockchip,pm-config"
  4377. + Compatibility with rk3399
  4378. +
  4379. +- rockchip,sleep-mode-config : the sleep mode config,
  4380. + ARMOFF, OSC disabled ...
  4381. +
  4382. +- rockchip,wakeup-config: the wake up sourece enable.
  4383. + GPIO, USB, SD...
  4384. +
  4385. +- rockchip,pwm-regulator-config: the pwm regulator name.
  4386. +
  4387. +Example:
  4388. + rockchip_suspend: rockchip_suspend {
  4389. + compatible = "rockchip,pm-rk3399";
  4390. + status = "okay";
  4391. + rockchip,sleep-mode-config = <
  4392. + (0
  4393. + | RKPM_SLP_ARMPD
  4394. + | RKPM_SLP_PERILPPD
  4395. + | RKPM_SLP_DDR_RET
  4396. + | RKPM_SLP_PLLPD
  4397. + | RKPM_SLP_OSC_DIS
  4398. + | RKPM_SLP_CENTER_PD
  4399. + | RKPM_SLP_AP_PWROFF
  4400. + )
  4401. + >;
  4402. + rockchip,wakeup-config = <
  4403. + (0 |
  4404. + RKPM_GPIO_WKUP_EN |
  4405. + RKPM_PWM_WKUP_EN)
  4406. + >;
  4407. + rockchip,pwm-regulator-config = <
  4408. + (0 |
  4409. + PWM2_REGULATOR_EN
  4410. + )
  4411. + >;
  4412. + };
  4413. diff -uNr '--exclude=.git' linux-5.6-rc7/Documentation/devicetree/bindings/vendor-prefixes.yaml linux-pinebook-pro_v5.6/Documentation/devicetree/bindings/vendor-prefixes.yaml
  4414. --- linux-5.6-rc7/Documentation/devicetree/bindings/vendor-prefixes.yaml 2020-03-22 18:31:56.000000000 -0700
  4415. +++ linux-pinebook-pro_v5.6/Documentation/devicetree/bindings/vendor-prefixes.yaml 2020-03-23 07:26:32.000000000 -0700
  4416. @@ -177,6 +177,8 @@
  4417. description: Cadence Design Systems Inc.
  4418. "^cdtech,.*":
  4419. description: CDTech(H.K.) Electronics Limited
  4420. + "^cellwise,.*":
  4421. + description: CellWise Microelectronics Co., Ltd
  4422. "^ceva,.*":
  4423. description: Ceva, Inc.
  4424. "^chipidea,.*":
  4425. diff -uNr '--exclude=.git' linux-5.6-rc7/drivers/bluetooth/hci_bcm.c linux-pinebook-pro_v5.6/drivers/bluetooth/hci_bcm.c
  4426. --- linux-5.6-rc7/drivers/bluetooth/hci_bcm.c 2020-03-22 18:31:56.000000000 -0700
  4427. +++ linux-pinebook-pro_v5.6/drivers/bluetooth/hci_bcm.c 2020-03-23 07:26:33.000000000 -0700
  4428. @@ -1472,6 +1472,23 @@
  4429. hci_uart_unregister_device(&bcmdev->serdev_hu);
  4430. }
  4431.  
  4432. +static void bcm_serdev_shutdown(struct serdev_device *serdev)
  4433. +{
  4434. + struct bcm_device *bcmdev = serdev_device_get_drvdata(serdev);
  4435. +
  4436. +/*
  4437. + if (test_bit(HCI_UART_REGISTERED, &bcmdev->hu->flags)) {
  4438. + hci_uart_unregister_device(&bcmdev->serdev_hu);
  4439. + }
  4440. +*/
  4441. + dev_info(bcmdev->dev, "Cutting power to bluetooth module\n");
  4442. + if (bcm_gpio_set_power(bcmdev, false)) {
  4443. + dev_err(bcmdev->dev, "Failed to power down\n");
  4444. + }
  4445. + usleep_range(500000, 1000000);
  4446. +}
  4447. +
  4448. +
  4449. #ifdef CONFIG_OF
  4450. static struct bcm_device_data bcm4354_device_data = {
  4451. .no_early_set_baudrate = true,
  4452. @@ -1497,6 +1514,7 @@
  4453. static struct serdev_device_driver bcm_serdev_driver = {
  4454. .probe = bcm_serdev_probe,
  4455. .remove = bcm_serdev_remove,
  4456. + .shutdown = bcm_serdev_shutdown,
  4457. .driver = {
  4458. .name = "hci_uart_bcm",
  4459. .of_match_table = of_match_ptr(bcm_bluetooth_of_match),
  4460. diff -uNr '--exclude=.git' linux-5.6-rc7/drivers/bluetooth/hci_serdev.c linux-pinebook-pro_v5.6/drivers/bluetooth/hci_serdev.c
  4461. --- linux-5.6-rc7/drivers/bluetooth/hci_serdev.c 2020-03-22 18:31:56.000000000 -0700
  4462. +++ linux-pinebook-pro_v5.6/drivers/bluetooth/hci_serdev.c 2020-03-23 07:26:33.000000000 -0700
  4463. @@ -364,5 +364,7 @@
  4464.  
  4465. hu->proto->close(hu);
  4466. serdev_device_close(hu->serdev);
  4467. +
  4468. + clear_bit(HCI_UART_REGISTERED, &hu->flags);
  4469. }
  4470. EXPORT_SYMBOL_GPL(hci_uart_unregister_device);
  4471. diff -uNr '--exclude=.git' linux-5.6-rc7/drivers/firmware/Kconfig linux-pinebook-pro_v5.6/drivers/firmware/Kconfig
  4472. --- linux-5.6-rc7/drivers/firmware/Kconfig 2020-03-22 18:31:56.000000000 -0700
  4473. +++ linux-pinebook-pro_v5.6/drivers/firmware/Kconfig 2020-03-23 07:26:34.000000000 -0700
  4474. @@ -298,6 +298,13 @@
  4475. config HAVE_ARM_SMCCC
  4476. bool
  4477.  
  4478. +config ROCKCHIP_SIP
  4479. + bool "Rockchip SIP interface"
  4480. + depends on ARM64 && ARM_PSCI_FW
  4481. + help
  4482. + Say Y here if you want to enable SIP callbacks for Rockchip platforms
  4483. + This option enables support for communicating with the ATF.
  4484. +
  4485. source "drivers/firmware/psci/Kconfig"
  4486. source "drivers/firmware/broadcom/Kconfig"
  4487. source "drivers/firmware/google/Kconfig"
  4488. diff -uNr '--exclude=.git' linux-5.6-rc7/drivers/firmware/Makefile linux-pinebook-pro_v5.6/drivers/firmware/Makefile
  4489. --- linux-5.6-rc7/drivers/firmware/Makefile 2020-03-22 18:31:56.000000000 -0700
  4490. +++ linux-pinebook-pro_v5.6/drivers/firmware/Makefile 2020-03-23 07:26:34.000000000 -0700
  4491. @@ -29,6 +29,7 @@
  4492. obj-$(CONFIG_GOOGLE_FIRMWARE) += google/
  4493. obj-$(CONFIG_EFI) += efi/
  4494. obj-$(CONFIG_UEFI_CPER) += efi/
  4495. +obj-$(CONFIG_ROCKCHIP_SIP) += rockchip_sip.o
  4496. obj-y += imx/
  4497. obj-y += tegra/
  4498. obj-y += xilinx/
  4499. diff -uNr '--exclude=.git' linux-5.6-rc7/drivers/firmware/rockchip_sip.c linux-pinebook-pro_v5.6/drivers/firmware/rockchip_sip.c
  4500. --- linux-5.6-rc7/drivers/firmware/rockchip_sip.c 1969-12-31 16:00:00.000000000 -0800
  4501. +++ linux-pinebook-pro_v5.6/drivers/firmware/rockchip_sip.c 2020-03-23 07:26:34.000000000 -0700
  4502. @@ -0,0 +1,262 @@
  4503. +/*
  4504. + * This program is free software; you can redistribute it and/or modify
  4505. + * it under the terms of the GNU General Public License version 2 as
  4506. + * published by the Free Software Foundation.
  4507. + *
  4508. + * This program is distributed in the hope that it will be useful,
  4509. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  4510. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  4511. + * GNU General Public License for more details.
  4512. + *
  4513. + * Copyright (C) 2016, Fuzhou Rockchip Electronics Co., Ltd
  4514. + */
  4515. +
  4516. +#include <linux/arm-smccc.h>
  4517. +#include <linux/io.h>
  4518. +#include <linux/rockchip/rockchip_sip.h>
  4519. +#include <asm/cputype.h>
  4520. +#include <asm/smp_plat.h>
  4521. +#include <uapi/linux/psci.h>
  4522. +#include <linux/ptrace.h>
  4523. +
  4524. +#ifdef CONFIG_64BIT
  4525. +#define PSCI_FN_NATIVE(version, name) PSCI_##version##_FN64_##name
  4526. +#else
  4527. +#define PSCI_FN_NATIVE(version, name) PSCI_##version##_FN_##name
  4528. +#endif
  4529. +
  4530. +#define SIZE_PAGE(n) ((n) << 12)
  4531. +
  4532. +static struct arm_smccc_res __invoke_sip_fn_smc(unsigned long function_id,
  4533. + unsigned long arg0,
  4534. + unsigned long arg1,
  4535. + unsigned long arg2)
  4536. +{
  4537. + struct arm_smccc_res res;
  4538. +
  4539. + arm_smccc_smc(function_id, arg0, arg1, arg2, 0, 0, 0, 0, &res);
  4540. + return res;
  4541. +}
  4542. +
  4543. +struct arm_smccc_res sip_smc_ddr_cfg(u32 arg0, u32 arg1, u32 arg2)
  4544. +{
  4545. + return __invoke_sip_fn_smc(SIP_DDR_CFG, arg0, arg1, arg2);
  4546. +}
  4547. +
  4548. +struct arm_smccc_res sip_smc_get_atf_version(void)
  4549. +{
  4550. + return __invoke_sip_fn_smc(SIP_ATF_VERSION, 0, 0, 0);
  4551. +}
  4552. +
  4553. +struct arm_smccc_res sip_smc_get_sip_version(void)
  4554. +{
  4555. + return __invoke_sip_fn_smc(SIP_SIP_VERSION, 0, 0, 0);
  4556. +}
  4557. +
  4558. +int sip_smc_set_suspend_mode(u32 ctrl, u32 config1, u32 config2)
  4559. +{
  4560. + struct arm_smccc_res res;
  4561. +
  4562. + res = __invoke_sip_fn_smc(SIP_SUSPEND_MODE, ctrl, config1, config2);
  4563. + return res.a0;
  4564. +}
  4565. +
  4566. +int sip_smc_virtual_poweroff(void)
  4567. +{
  4568. + struct arm_smccc_res res;
  4569. +
  4570. + res = __invoke_sip_fn_smc(PSCI_FN_NATIVE(1_0, SYSTEM_SUSPEND), 0, 0, 0);
  4571. + return res.a0;
  4572. +}
  4573. +
  4574. +struct arm_smccc_res sip_smc_request_share_mem(u32 page_num,
  4575. + share_page_type_t page_type)
  4576. +{
  4577. + struct arm_smccc_res res;
  4578. + unsigned long share_mem_phy;
  4579. +
  4580. + res = __invoke_sip_fn_smc(SIP_SHARE_MEM, page_num, page_type, 0);
  4581. + if (IS_SIP_ERROR(res.a0))
  4582. + goto error;
  4583. +
  4584. + share_mem_phy = res.a1;
  4585. + res.a1 = (unsigned long)ioremap(share_mem_phy, SIZE_PAGE(page_num));
  4586. +
  4587. +error:
  4588. + return res;
  4589. +}
  4590. +
  4591. +struct arm_smccc_res sip_smc_mcu_el3fiq(u32 arg0, u32 arg1, u32 arg2)
  4592. +{
  4593. + return __invoke_sip_fn_smc(SIP_MCU_EL3FIQ_CFG, arg0, arg1, arg2);
  4594. +}
  4595. +
  4596. +/************************** fiq debugger **************************************/
  4597. +#ifdef CONFIG_ARM64
  4598. +#define SIP_UARTDBG_FN SIP_UARTDBG_CFG64
  4599. +#else
  4600. +#define SIP_UARTDBG_FN SIP_UARTDBG_CFG
  4601. +#endif
  4602. +
  4603. +static int fiq_sip_enabled;
  4604. +static int fiq_target_cpu;
  4605. +static phys_addr_t ft_fiq_mem_phy;
  4606. +static void __iomem *ft_fiq_mem_base;
  4607. +static void (*sip_fiq_debugger_uart_irq_tf)(struct pt_regs _pt_regs,
  4608. + unsigned long cpu);
  4609. +int sip_fiq_debugger_is_enabled(void)
  4610. +{
  4611. + return fiq_sip_enabled;
  4612. +}
  4613. +
  4614. +static struct pt_regs sip_fiq_debugger_get_pt_regs(void *reg_base,
  4615. + unsigned long sp_el1)
  4616. +{
  4617. + struct pt_regs fiq_pt_regs;
  4618. +
  4619. +#ifdef CONFIG_ARM64
  4620. + /* copy cpu context */
  4621. + memcpy(&fiq_pt_regs, reg_base, 8 * 31);
  4622. +
  4623. + /* copy pstate */
  4624. + memcpy(&fiq_pt_regs.pstate, reg_base + 0x110, 8);
  4625. +
  4626. + /* EL1 mode */
  4627. + if (fiq_pt_regs.pstate & 0x10)
  4628. + memcpy(&fiq_pt_regs.sp, reg_base + 0xf8, 8);
  4629. + /* EL0 mode */
  4630. + else
  4631. + fiq_pt_regs.sp = sp_el1;
  4632. +
  4633. + /* copy pc */
  4634. + memcpy(&fiq_pt_regs.pc, reg_base + 0x118, 8);
  4635. +#else
  4636. + struct sm_nsec_ctx *nsec_ctx = reg_base;
  4637. +
  4638. + fiq_pt_regs.ARM_r0 = nsec_ctx->r0;
  4639. + fiq_pt_regs.ARM_r1 = nsec_ctx->r1;
  4640. + fiq_pt_regs.ARM_r2 = nsec_ctx->r2;
  4641. + fiq_pt_regs.ARM_r3 = nsec_ctx->r3;
  4642. + fiq_pt_regs.ARM_r4 = nsec_ctx->r4;
  4643. + fiq_pt_regs.ARM_r5 = nsec_ctx->r5;
  4644. + fiq_pt_regs.ARM_r6 = nsec_ctx->r6;
  4645. + fiq_pt_regs.ARM_r7 = nsec_ctx->r7;
  4646. + fiq_pt_regs.ARM_r8 = nsec_ctx->r8;
  4647. + fiq_pt_regs.ARM_r9 = nsec_ctx->r9;
  4648. + fiq_pt_regs.ARM_r10 = nsec_ctx->r10;
  4649. + fiq_pt_regs.ARM_fp = nsec_ctx->r11;
  4650. + fiq_pt_regs.ARM_ip = nsec_ctx->r12;
  4651. + fiq_pt_regs.ARM_sp = nsec_ctx->svc_sp;
  4652. + fiq_pt_regs.ARM_lr = nsec_ctx->svc_lr;
  4653. + fiq_pt_regs.ARM_pc = nsec_ctx->mon_lr;
  4654. + fiq_pt_regs.ARM_cpsr = nsec_ctx->mon_spsr;
  4655. +#endif
  4656. +
  4657. + return fiq_pt_regs;
  4658. +}
  4659. +
  4660. +static void sip_fiq_debugger_uart_irq_tf_cb(unsigned long sp_el1,
  4661. + unsigned long offset,
  4662. + unsigned long cpu)
  4663. +{
  4664. + struct pt_regs fiq_pt_regs;
  4665. + char *cpu_context;
  4666. +
  4667. + /* calling fiq handler */
  4668. + if (ft_fiq_mem_base) {
  4669. + cpu_context = (char *)ft_fiq_mem_base + offset;
  4670. + fiq_pt_regs = sip_fiq_debugger_get_pt_regs(cpu_context, sp_el1);
  4671. + sip_fiq_debugger_uart_irq_tf(fiq_pt_regs, cpu);
  4672. + }
  4673. +
  4674. + /* fiq handler done, return to EL3(then EL3 return to EL1 entry) */
  4675. + __invoke_sip_fn_smc(SIP_UARTDBG_FN, 0, 0, UARTDBG_CFG_OSHDL_TO_OS);
  4676. +}
  4677. +
  4678. +int sip_fiq_debugger_uart_irq_tf_init(u32 irq_id, void *callback_fn)
  4679. +{
  4680. + struct arm_smccc_res res;
  4681. +
  4682. + fiq_target_cpu = 0;
  4683. +
  4684. + /* init fiq debugger callback */
  4685. + sip_fiq_debugger_uart_irq_tf = callback_fn;
  4686. + res = __invoke_sip_fn_smc(SIP_UARTDBG_FN, irq_id,
  4687. + (unsigned long)sip_fiq_debugger_uart_irq_tf_cb,
  4688. + UARTDBG_CFG_INIT);
  4689. + if (IS_SIP_ERROR(res.a0)) {
  4690. + pr_err("%s error: %d\n", __func__, (int)res.a0);
  4691. + return res.a0;
  4692. + }
  4693. +
  4694. + /* share memory ioremap */
  4695. + if (!ft_fiq_mem_base) {
  4696. + ft_fiq_mem_phy = res.a1;
  4697. + ft_fiq_mem_base = ioremap(ft_fiq_mem_phy,
  4698. + FIQ_UARTDBG_SHARE_MEM_SIZE);
  4699. + if (!ft_fiq_mem_base) {
  4700. + pr_err("%s: share memory ioremap failed\n", __func__);
  4701. + return -ENOMEM;
  4702. + }
  4703. + }
  4704. +
  4705. + fiq_sip_enabled = 1;
  4706. +
  4707. + return SIP_RET_SUCCESS;
  4708. +}
  4709. +
  4710. +int sip_fiq_debugger_switch_cpu(u32 cpu)
  4711. +{
  4712. + struct arm_smccc_res res;
  4713. +
  4714. + fiq_target_cpu = cpu;
  4715. + res = __invoke_sip_fn_smc(SIP_UARTDBG_FN, cpu_logical_map(cpu),
  4716. + 0, UARTDBG_CFG_OSHDL_CPUSW);
  4717. + return res.a0;
  4718. +}
  4719. +
  4720. +void sip_fiq_debugger_enable_debug(bool enable)
  4721. +{
  4722. + unsigned long val;
  4723. +
  4724. + val = enable ? UARTDBG_CFG_OSHDL_DEBUG_ENABLE :
  4725. + UARTDBG_CFG_OSHDL_DEBUG_DISABLE;
  4726. +
  4727. + __invoke_sip_fn_smc(SIP_UARTDBG_FN, 0, 0, val);
  4728. +}
  4729. +
  4730. +int sip_fiq_debugger_set_print_port(u32 port_phyaddr, u32 baudrate)
  4731. +{
  4732. + struct arm_smccc_res res;
  4733. +
  4734. + res = __invoke_sip_fn_smc(SIP_UARTDBG_FN, port_phyaddr, baudrate,
  4735. + UARTDBG_CFG_PRINT_PORT);
  4736. + return res.a0;
  4737. +}
  4738. +
  4739. +int sip_fiq_debugger_request_share_memory(void)
  4740. +{
  4741. + struct arm_smccc_res res;
  4742. +
  4743. + /* request page share memory */
  4744. + res = sip_smc_request_share_mem(FIQ_UARTDBG_PAGE_NUMS,
  4745. + SHARE_PAGE_TYPE_UARTDBG);
  4746. + if (IS_SIP_ERROR(res.a0))
  4747. + return res.a0;
  4748. +
  4749. + return SIP_RET_SUCCESS;
  4750. +}
  4751. +
  4752. +int sip_fiq_debugger_get_target_cpu(void)
  4753. +{
  4754. + return fiq_target_cpu;
  4755. +}
  4756. +
  4757. +void sip_fiq_debugger_enable_fiq(bool enable, uint32_t tgt_cpu)
  4758. +{
  4759. + u32 en;
  4760. +
  4761. + fiq_target_cpu = tgt_cpu;
  4762. + en = enable ? UARTDBG_CFG_FIQ_ENABEL : UARTDBG_CFG_FIQ_DISABEL;
  4763. + __invoke_sip_fn_smc(SIP_UARTDBG_FN, tgt_cpu, 0, en);
  4764. +}
  4765. diff -uNr '--exclude=.git' linux-5.6-rc7/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c linux-pinebook-pro_v5.6/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c
  4766. --- linux-5.6-rc7/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c 2020-03-22 18:31:56.000000000 -0700
  4767. +++ linux-pinebook-pro_v5.6/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c 2020-03-23 07:26:34.000000000 -0700
  4768. @@ -604,6 +604,7 @@
  4769. static int anx78xx_dp_link_training(struct anx78xx *anx78xx)
  4770. {
  4771. u8 dp_bw, dpcd[2];
  4772. + unsigned int max_link_rate;
  4773. int err;
  4774.  
  4775. err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_HDMI_MUTE_CTRL_REG,
  4776. @@ -722,8 +723,8 @@
  4777. if (err)
  4778. return err;
  4779.  
  4780. - dpcd[0] = drm_dp_max_link_rate(anx78xx->dpcd);
  4781. - dpcd[0] = drm_dp_link_rate_to_bw_code(dpcd[0]);
  4782. + max_link_rate = drm_dp_max_link_rate(anx78xx->dpcd);
  4783. + dpcd[0] = drm_dp_link_rate_to_bw_code(max_link_rate);
  4784. err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
  4785. SP_DP_MAIN_LINK_BW_SET_REG, dpcd[0]);
  4786. if (err)
  4787. diff -uNr '--exclude=.git' linux-5.6-rc7/drivers/leds/led-core.c linux-pinebook-pro_v5.6/drivers/leds/led-core.c
  4788. --- linux-5.6-rc7/drivers/leds/led-core.c 2020-03-22 18:31:56.000000000 -0700
  4789. +++ linux-pinebook-pro_v5.6/drivers/leds/led-core.c 2020-03-23 07:26:34.000000000 -0700
  4790. @@ -175,6 +175,7 @@
  4791. unsigned long *delay_off)
  4792. {
  4793. if (!test_bit(LED_BLINK_ONESHOT, &led_cdev->work_flags) &&
  4794. + !test_bit(LED_BLINK_INVERT, &led_cdev->work_flags) &&
  4795. led_cdev->blink_set &&
  4796. !led_cdev->blink_set(led_cdev, delay_on, delay_off))
  4797. return;
  4798. diff -uNr '--exclude=.git' linux-5.6-rc7/drivers/leds/led-triggers.c linux-pinebook-pro_v5.6/drivers/leds/led-triggers.c
  4799. --- linux-5.6-rc7/drivers/leds/led-triggers.c 2020-03-22 18:31:56.000000000 -0700
  4800. +++ linux-pinebook-pro_v5.6/drivers/leds/led-triggers.c 2020-03-23 07:26:34.000000000 -0700
  4801. @@ -27,14 +27,80 @@
  4802.  
  4803. /* Used by LED Class */
  4804.  
  4805. +#define TRIGGER_INVERT_SUFFIX "-inverted"
  4806. +
  4807. +/*
  4808. + * Check suffix of trigger name agains TRIGGER_INVERT_SUFFIX
  4809. + */
  4810. +static bool led_trigger_is_inverted(const char *trigname)
  4811. +{
  4812. + if (strlen(trigname) >= strlen(TRIGGER_INVERT_SUFFIX)) {
  4813. + return !strcmp(trigname + strlen(trigname) -
  4814. + strlen(TRIGGER_INVERT_SUFFIX),
  4815. + TRIGGER_INVERT_SUFFIX);
  4816. + }
  4817. +
  4818. + return false;
  4819. +}
  4820. +
  4821. +/*
  4822. + * Get length of trigger name name without TRIGGER_INVERT_SUFFIX
  4823. + */
  4824. +static size_t led_trigger_get_name_len(const char *trigname)
  4825. +{
  4826. + // Subtract length of TRIGGER_INVERT_SUFFIX if trigger is inverted
  4827. + if (led_trigger_is_inverted(trigname))
  4828. + return strlen(trigname) - strlen(TRIGGER_INVERT_SUFFIX);
  4829. + return strlen(trigname);
  4830. +}
  4831. +
  4832. +/*
  4833. + * Find and set led trigger by name
  4834. + */
  4835. +static int led_trigger_set_str_(struct led_classdev *led_cdev,
  4836. + const char *trigname, bool lock)
  4837. +{
  4838. + struct led_trigger *trig;
  4839. + bool inverted = led_trigger_is_inverted(trigname);
  4840. + size_t len = led_trigger_get_name_len(trigname);
  4841. +
  4842. + down_read(&triggers_list_lock);
  4843. + list_for_each_entry(trig, &trigger_list, next_trig) {
  4844. + /* Compare trigger name without inversion suffix */
  4845. + if (strlen(trig->name) == len &&
  4846. + !strncmp(trigname, trig->name, len)) {
  4847. + if (lock)
  4848. + down_write(&led_cdev->trigger_lock);
  4849. + led_trigger_set(led_cdev, trig);
  4850. + if (inverted)
  4851. + led_cdev->flags |= LED_INVERT_TRIGGER;
  4852. + else
  4853. + led_cdev->flags &= ~LED_INVERT_TRIGGER;
  4854. + if (lock)
  4855. + up_write(&led_cdev->trigger_lock);
  4856. +
  4857. + up_read(&triggers_list_lock);
  4858. + return 0;
  4859. + }
  4860. + }
  4861. + /* we come here only if trigname matches no trigger */
  4862. + up_read(&triggers_list_lock);
  4863. + return -EINVAL;
  4864. +}
  4865. +
  4866. +#define led_trigger_set_str(cdev, name) led_trigger_set_str_(cdev, name, true)
  4867. +#define led_trigger_set_str_unlocked(cdev, name) \
  4868. + led_trigger_set_str_(cdev, name, false)
  4869. +
  4870. +
  4871. ssize_t led_trigger_write(struct file *filp, struct kobject *kobj,
  4872. struct bin_attribute *bin_attr, char *buf,
  4873. loff_t pos, size_t count)
  4874. {
  4875. struct device *dev = kobj_to_dev(kobj);
  4876. struct led_classdev *led_cdev = dev_get_drvdata(dev);
  4877. - struct led_trigger *trig;
  4878. int ret = count;
  4879. + char *name;
  4880.  
  4881. mutex_lock(&led_cdev->led_access);
  4882.  
  4883. @@ -48,20 +114,10 @@
  4884. goto unlock;
  4885. }
  4886.  
  4887. - down_read(&triggers_list_lock);
  4888. - list_for_each_entry(trig, &trigger_list, next_trig) {
  4889. - if (sysfs_streq(buf, trig->name)) {
  4890. - down_write(&led_cdev->trigger_lock);
  4891. - led_trigger_set(led_cdev, trig);
  4892. - up_write(&led_cdev->trigger_lock);
  4893. -
  4894. - up_read(&triggers_list_lock);
  4895. - goto unlock;
  4896. - }
  4897. - }
  4898. - /* we come here only if buf matches no trigger */
  4899. - ret = -EINVAL;
  4900. - up_read(&triggers_list_lock);
  4901. + name = strim(buf);
  4902. + ret = led_trigger_set_str(led_cdev, name);
  4903. + if (!ret)
  4904. + ret = count;
  4905.  
  4906. unlock:
  4907. mutex_unlock(&led_cdev->led_access);
  4908. @@ -93,12 +149,22 @@
  4909. led_cdev->trigger ? "none" : "[none]");
  4910.  
  4911. list_for_each_entry(trig, &trigger_list, next_trig) {
  4912. - bool hit = led_cdev->trigger &&
  4913. - !strcmp(led_cdev->trigger->name, trig->name);
  4914. + bool hit = led_cdev->trigger == trig;
  4915. + bool inverted = led_cdev->flags & LED_INVERT_TRIGGER;
  4916. +
  4917. + /* print non-inverted trigger */
  4918. + len += led_trigger_snprintf(buf + len, size - len,
  4919. + " %s%s%s",
  4920. + hit && !inverted ? "[" : "",
  4921. + trig->name,
  4922. + hit && !inverted ? "]" : "");
  4923.  
  4924. + /* print inverted trigger */
  4925. len += led_trigger_snprintf(buf + len, size - len,
  4926. - " %s%s%s", hit ? "[" : "",
  4927. - trig->name, hit ? "]" : "");
  4928. + " %s%s"TRIGGER_INVERT_SUFFIX"%s",
  4929. + hit && inverted ? "[" : "",
  4930. + trig->name,
  4931. + hit && inverted ? "]" : "");
  4932. }
  4933.  
  4934. len += led_trigger_snprintf(buf + len, size - len, "\n");
  4935. @@ -235,21 +301,15 @@
  4936.  
  4937. void led_trigger_set_default(struct led_classdev *led_cdev)
  4938. {
  4939. - struct led_trigger *trig;
  4940. + bool found;
  4941.  
  4942. if (!led_cdev->default_trigger)
  4943. return;
  4944.  
  4945. down_read(&triggers_list_lock);
  4946. - down_write(&led_cdev->trigger_lock);
  4947. - list_for_each_entry(trig, &trigger_list, next_trig) {
  4948. - if (!strcmp(led_cdev->default_trigger, trig->name)) {
  4949. - led_cdev->flags |= LED_INIT_DEFAULT_TRIGGER;
  4950. - led_trigger_set(led_cdev, trig);
  4951. - break;
  4952. - }
  4953. - }
  4954. - up_write(&led_cdev->trigger_lock);
  4955. + found = !led_trigger_set_str(led_cdev, led_cdev->default_trigger);
  4956. + if (found)
  4957. + led_cdev->flags |= LED_INIT_DEFAULT_TRIGGER;
  4958. up_read(&triggers_list_lock);
  4959. }
  4960. EXPORT_SYMBOL_GPL(led_trigger_set_default);
  4961. @@ -292,11 +352,14 @@
  4962. /* Register with any LEDs that have this as a default trigger */
  4963. down_read(&leds_list_lock);
  4964. list_for_each_entry(led_cdev, &leds_list, node) {
  4965. + bool found;
  4966. +
  4967. down_write(&led_cdev->trigger_lock);
  4968. - if (!led_cdev->trigger && led_cdev->default_trigger &&
  4969. - !strcmp(led_cdev->default_trigger, trig->name)) {
  4970. - led_cdev->flags |= LED_INIT_DEFAULT_TRIGGER;
  4971. - led_trigger_set(led_cdev, trig);
  4972. + if (!led_cdev->trigger && led_cdev->default_trigger) {
  4973. + found = !led_trigger_set_str_unlocked(led_cdev,
  4974. + led_cdev->default_trigger);
  4975. + if (found)
  4976. + led_cdev->flags |= LED_INIT_DEFAULT_TRIGGER;
  4977. }
  4978. up_write(&led_cdev->trigger_lock);
  4979. }
  4980. @@ -369,8 +432,14 @@
  4981. return;
  4982.  
  4983. read_lock(&trig->leddev_list_lock);
  4984. - list_for_each_entry(led_cdev, &trig->led_cdevs, trig_list)
  4985. - led_set_brightness(led_cdev, brightness);
  4986. + list_for_each_entry(led_cdev, &trig->led_cdevs, trig_list) {
  4987. + /* Reverse brightness if LED is inverted */
  4988. + if (led_cdev->flags & LED_INVERT_TRIGGER)
  4989. + led_set_brightness(led_cdev,
  4990. + led_cdev->max_brightness - brightness);
  4991. + else
  4992. + led_set_brightness(led_cdev, brightness);
  4993. + }
  4994. read_unlock(&trig->leddev_list_lock);
  4995. }
  4996. EXPORT_SYMBOL_GPL(led_trigger_event);
  4997. @@ -388,10 +457,13 @@
  4998.  
  4999. read_lock(&trig->leddev_list_lock);
  5000. list_for_each_entry(led_cdev, &trig->led_cdevs, trig_list) {
  5001. - if (oneshot)
  5002. + bool trigger_inverted =
  5003. + !!(led_cdev->flags & LED_INVERT_TRIGGER);
  5004. + if (oneshot) {
  5005. + /* use logical xnor to determine inversion parameter */
  5006. led_blink_set_oneshot(led_cdev, delay_on, delay_off,
  5007. - invert);
  5008. - else
  5009. + (!!invert) == trigger_inverted);
  5010. + } else
  5011. led_blink_set(led_cdev, delay_on, delay_off);
  5012. }
  5013. read_unlock(&trig->leddev_list_lock);
  5014. diff -uNr '--exclude=.git' linux-5.6-rc7/drivers/mfd/rk808.c linux-pinebook-pro_v5.6/drivers/mfd/rk808.c
  5015. --- linux-5.6-rc7/drivers/mfd/rk808.c 2020-03-22 18:31:56.000000000 -0700
  5016. +++ linux-pinebook-pro_v5.6/drivers/mfd/rk808.c 2020-03-23 07:26:35.000000000 -0700
  5017. @@ -514,15 +514,26 @@
  5018. struct rk808 *rk808 = i2c_get_clientdata(rk808_i2c_client);
  5019. int ret;
  5020.  
  5021. - if (system_state == SYSTEM_POWER_OFF &&
  5022. - (rk808->variant == RK809_ID || rk808->variant == RK817_ID)) {
  5023. - ret = regmap_update_bits(rk808->regmap,
  5024. - RK817_SYS_CFG(3),
  5025. - RK817_SLPPIN_FUNC_MSK,
  5026. - SLPPIN_DN_FUN);
  5027. - if (ret) {
  5028. - dev_warn(&rk808_i2c_client->dev,
  5029. - "Cannot switch to power down function\n");
  5030. + if (system_state == SYSTEM_POWER_OFF) {
  5031. + switch(rk808->variant) {
  5032. + case RK809_ID:
  5033. + case RK817_ID:
  5034. + ret = regmap_update_bits(rk808->regmap,
  5035. + RK817_SYS_CFG(3),
  5036. + RK817_SLPPIN_FUNC_MSK,
  5037. + SLPPIN_DN_FUN);
  5038. + if (ret) {
  5039. + dev_warn(&rk808_i2c_client->dev,
  5040. + "Cannot switch to power down function\n");
  5041. + }
  5042. + break;
  5043. + case RK808_ID:
  5044. + if(rk808->use_syscore_powerdown) {
  5045. + rk808_device_shutdown();
  5046. + }
  5047. + break;
  5048. + default:
  5049. + break;
  5050. }
  5051. }
  5052. }
  5053. @@ -605,6 +616,7 @@
  5054. cells = rk808s;
  5055. nr_cells = ARRAY_SIZE(rk808s);
  5056. rk808->pm_pwroff_fn = rk808_device_shutdown;
  5057. + register_syscore_ops(&rk808_syscore_ops);
  5058. break;
  5059. case RK818_ID:
  5060. rk808->regmap_cfg = &rk818_regmap_config;
  5061. @@ -676,9 +688,13 @@
  5062.  
  5063. pm_off = of_property_read_bool(np,
  5064. "rockchip,system-power-controller");
  5065. - if (pm_off && !pm_power_off) {
  5066. - rk808_i2c_client = client;
  5067. - pm_power_off = rk808->pm_pwroff_fn;
  5068. + if (pm_off) {
  5069. + if (pm_power_off) {
  5070. + rk808->use_syscore_powerdown = true;
  5071. + } else {
  5072. + rk808_i2c_client = client;
  5073. + pm_power_off = rk808->pm_pwroff_fn;
  5074. + }
  5075. }
  5076.  
  5077. if (pm_off && !pm_power_off_prepare) {
  5078. diff -uNr '--exclude=.git' linux-5.6-rc7/drivers/mmc/core/pwrseq_simple.c linux-pinebook-pro_v5.6/drivers/mmc/core/pwrseq_simple.c
  5079. --- linux-5.6-rc7/drivers/mmc/core/pwrseq_simple.c 2020-03-22 18:31:56.000000000 -0700
  5080. +++ linux-pinebook-pro_v5.6/drivers/mmc/core/pwrseq_simple.c 2020-03-23 07:26:35.000000000 -0700
  5081. @@ -80,10 +80,8 @@
  5082. msleep(pwrseq->post_power_on_delay_ms);
  5083. }
  5084.  
  5085. -static void mmc_pwrseq_simple_power_off(struct mmc_host *host)
  5086. +static void __mmc_pwrseq_simple_power_off(struct mmc_pwrseq_simple *pwrseq)
  5087. {
  5088. - struct mmc_pwrseq_simple *pwrseq = to_pwrseq_simple(host->pwrseq);
  5089. -
  5090. mmc_pwrseq_simple_set_gpios_value(pwrseq, 1);
  5091.  
  5092. if (pwrseq->power_off_delay_us)
  5093. @@ -96,6 +94,12 @@
  5094. }
  5095. }
  5096.  
  5097. +static void mmc_pwrseq_simple_power_off(struct mmc_host *host)
  5098. +{
  5099. + struct mmc_pwrseq_simple *pwrseq = to_pwrseq_simple(host->pwrseq);
  5100. + __mmc_pwrseq_simple_power_off(pwrseq);
  5101. +}
  5102. +
  5103. static const struct mmc_pwrseq_ops mmc_pwrseq_simple_ops = {
  5104. .pre_power_on = mmc_pwrseq_simple_pre_power_on,
  5105. .post_power_on = mmc_pwrseq_simple_post_power_on,
  5106. @@ -151,9 +155,18 @@
  5107. return 0;
  5108. }
  5109.  
  5110. +static void mmc_pwrseq_simple_shutdown(struct platform_device *pdev)
  5111. +{
  5112. + struct mmc_pwrseq_simple *pwrseq = platform_get_drvdata(pdev);
  5113. +
  5114. + dev_info(&pdev->dev, "Turning off mmc\n");
  5115. + __mmc_pwrseq_simple_power_off(pwrseq);
  5116. +}
  5117. +
  5118. static struct platform_driver mmc_pwrseq_simple_driver = {
  5119. .probe = mmc_pwrseq_simple_probe,
  5120. .remove = mmc_pwrseq_simple_remove,
  5121. + .shutdown = mmc_pwrseq_simple_shutdown,
  5122. .driver = {
  5123. .name = "pwrseq_simple",
  5124. .of_match_table = mmc_pwrseq_simple_of_match,
  5125. diff -uNr '--exclude=.git' linux-5.6-rc7/drivers/phy/rockchip/phy-rockchip-typec.c linux-pinebook-pro_v5.6/drivers/phy/rockchip/phy-rockchip-typec.c
  5126. --- linux-5.6-rc7/drivers/phy/rockchip/phy-rockchip-typec.c 2020-03-22 18:31:56.000000000 -0700
  5127. +++ linux-pinebook-pro_v5.6/drivers/phy/rockchip/phy-rockchip-typec.c 2020-03-23 07:26:36.000000000 -0700
  5128. @@ -40,6 +40,7 @@
  5129. #include <linux/clk-provider.h>
  5130. #include <linux/delay.h>
  5131. #include <linux/extcon.h>
  5132. +#include <linux/extcon-provider.h>
  5133. #include <linux/io.h>
  5134. #include <linux/iopoll.h>
  5135. #include <linux/kernel.h>
  5136. @@ -1160,6 +1161,22 @@
  5137. dev_err(dev, "Invalid or missing extcon\n");
  5138. return PTR_ERR(tcphy->extcon);
  5139. }
  5140. + } else {
  5141. + extcon_set_property_capability(tcphy->extcon, EXTCON_USB,
  5142. + EXTCON_PROP_USB_SS);
  5143. + extcon_set_property_capability(tcphy->extcon, EXTCON_USB_HOST,
  5144. + EXTCON_PROP_USB_SS);
  5145. + extcon_set_property_capability(tcphy->extcon, EXTCON_DISP_DP,
  5146. + EXTCON_PROP_USB_SS);
  5147. + extcon_set_property_capability(tcphy->extcon, EXTCON_USB,
  5148. + EXTCON_PROP_USB_TYPEC_POLARITY);
  5149. + extcon_set_property_capability(tcphy->extcon, EXTCON_USB_HOST,
  5150. + EXTCON_PROP_USB_TYPEC_POLARITY);
  5151. + extcon_set_property_capability(tcphy->extcon, EXTCON_DISP_DP,
  5152. + EXTCON_PROP_USB_TYPEC_POLARITY);
  5153. + extcon_sync(tcphy->extcon, EXTCON_USB);
  5154. + extcon_sync(tcphy->extcon, EXTCON_USB_HOST);
  5155. + extcon_sync(tcphy->extcon, EXTCON_DISP_DP);
  5156. }
  5157.  
  5158. pm_runtime_enable(dev);
  5159. diff -uNr '--exclude=.git' linux-5.6-rc7/drivers/power/supply/cw2015_battery.c linux-pinebook-pro_v5.6/drivers/power/supply/cw2015_battery.c
  5160. --- linux-5.6-rc7/drivers/power/supply/cw2015_battery.c 1969-12-31 16:00:00.000000000 -0800
  5161. +++ linux-pinebook-pro_v5.6/drivers/power/supply/cw2015_battery.c 2020-03-23 07:26:36.000000000 -0700
  5162. @@ -0,0 +1,749 @@
  5163. +// SPDX-License-Identifier: GPL-2.0
  5164. +/*
  5165. + * Fuel gauge driver for CellWise 2013 / 2015
  5166. + *
  5167. + * Copyright (C) 2012, RockChip
  5168. + * Copyright (C) 2020, Tobias Schramm
  5169. + *
  5170. + * Authors: xuhuicong <xhc@rock-chips.com>
  5171. + * Authors: Tobias Schramm <t.schramm@manjaro.org>
  5172. + */
  5173. +
  5174. +#include <linux/bits.h>
  5175. +#include <linux/delay.h>
  5176. +#include <linux/i2c.h>
  5177. +#include <linux/gfp.h>
  5178. +#include <linux/gpio/consumer.h>
  5179. +#include <linux/kernel.h>
  5180. +#include <linux/module.h>
  5181. +#include <linux/power_supply.h>
  5182. +#include <linux/property.h>
  5183. +#include <linux/regmap.h>
  5184. +#include <linux/time.h>
  5185. +#include <linux/workqueue.h>
  5186. +
  5187. +#define CW2015_SIZE_BATINFO 64
  5188. +
  5189. +#define CW2015_RESET_TRIES 5
  5190. +
  5191. +#define CW2015_REG_VERSION 0x00
  5192. +#define CW2015_REG_VCELL 0x02
  5193. +#define CW2015_REG_SOC 0x04
  5194. +#define CW2015_REG_RRT_ALERT 0x06
  5195. +#define CW2015_REG_CONFIG 0x08
  5196. +#define CW2015_REG_MODE 0x0A
  5197. +#define CW2015_REG_BATINFO 0x10
  5198. +
  5199. +#define CW2015_MODE_SLEEP_MASK GENMASK(7, 6)
  5200. +#define CW2015_MODE_SLEEP (0x03 << 6)
  5201. +#define CW2015_MODE_NORMAL (0x00 << 6)
  5202. +#define CW2015_MODE_QUICK_START (0x03 << 4)
  5203. +#define CW2015_MODE_RESTART (0x0f << 0)
  5204. +
  5205. +#define CW2015_CONFIG_UPDATE_FLG (0x01 << 1)
  5206. +#define CW2015_ATHD(x) ((x) << 3)
  5207. +#define CW2015_MASK_ATHD GENMASK(7, 3)
  5208. +#define CW2015_MASK_SOC GENMASK(12, 0)
  5209. +
  5210. +/* reset gauge of no valid state of charge could be polled for 40s */
  5211. +#define CW2015_BAT_SOC_ERROR_MS (40 * MSEC_PER_SEC)
  5212. +/* reset gauge if state of charge stuck for half an hour during charging */
  5213. +#define CW2015_BAT_CHARGING_STUCK_MS (1800 * MSEC_PER_SEC)
  5214. +
  5215. +/* poll interval from CellWise GPL Android driver example */
  5216. +#define CW2015_DEFAULT_POLL_INTERVAL_MS 8000
  5217. +
  5218. +#define CW2015_AVERAGING_SAMPLES 3
  5219. +
  5220. +struct cw_battery {
  5221. + struct device *dev;
  5222. + struct workqueue_struct *battery_workqueue;
  5223. + struct delayed_work battery_delay_work;
  5224. + struct regmap *regmap;
  5225. + struct power_supply *rk_bat;
  5226. + struct power_supply_battery_info battery;
  5227. + u8 *bat_profile;
  5228. +
  5229. + bool charger_attached;
  5230. + bool battery_changed;
  5231. +
  5232. + int soc;
  5233. + int voltage_mv;
  5234. + int status;
  5235. + int time_to_empty;
  5236. + int charge_count;
  5237. +
  5238. + u32 poll_interval_ms;
  5239. + u8 alert_level;
  5240. +
  5241. + unsigned int read_errors;
  5242. + unsigned int charge_stuck_cnt;
  5243. +};
  5244. +
  5245. +static int cw_read_word(struct cw_battery *cw_bat, u8 reg, u16 *val)
  5246. +{
  5247. + __be16 value;
  5248. + int ret;
  5249. +
  5250. + ret = regmap_bulk_read(cw_bat->regmap, reg, &value, sizeof(value));
  5251. + if (ret)
  5252. + return ret;
  5253. +
  5254. + *val = be16_to_cpu(value);
  5255. + return 0;
  5256. +}
  5257. +
  5258. +int cw_update_profile(struct cw_battery *cw_bat)
  5259. +{
  5260. + int ret;
  5261. + unsigned int reg_val;
  5262. + u8 reset_val;
  5263. +
  5264. + /* make sure gauge is not in sleep mode */
  5265. + ret = regmap_read(cw_bat->regmap, CW2015_REG_MODE, &reg_val);
  5266. + if (ret)
  5267. + return ret;
  5268. +
  5269. + reset_val = reg_val;
  5270. + if ((reg_val & CW2015_MODE_SLEEP_MASK) == CW2015_MODE_SLEEP) {
  5271. + dev_err(cw_bat->dev,
  5272. + "Gauge is in sleep mode, can't update battery info\n");
  5273. + return -EINVAL;
  5274. + }
  5275. +
  5276. + /* write new battery info */
  5277. + ret = regmap_raw_write(cw_bat->regmap, CW2015_REG_BATINFO,
  5278. + cw_bat->bat_profile,
  5279. + CW2015_SIZE_BATINFO);
  5280. + if (ret)
  5281. + return ret;
  5282. +
  5283. + /* set config update flag */
  5284. + reg_val |= CW2015_CONFIG_UPDATE_FLG;
  5285. + reg_val &= ~CW2015_MASK_ATHD;
  5286. + reg_val |= CW2015_ATHD(cw_bat->alert_level);
  5287. + ret = regmap_write(cw_bat->regmap, CW2015_REG_CONFIG, reg_val);
  5288. + if (ret)
  5289. + return ret;
  5290. +
  5291. + /* reset gauge to apply new battery profile */
  5292. + reset_val &= ~CW2015_MODE_RESTART;
  5293. + reg_val = reset_val | CW2015_MODE_RESTART;
  5294. + ret = regmap_write(cw_bat->regmap, CW2015_REG_MODE, reg_val);
  5295. + if (ret)
  5296. + return ret;
  5297. +
  5298. + /* wait for gauge to reset */
  5299. + msleep(20);
  5300. +
  5301. + /* clear reset flag */
  5302. + ret = regmap_write(cw_bat->regmap, CW2015_REG_MODE, reset_val);
  5303. + if (ret)
  5304. + return ret;
  5305. +
  5306. + /* wait for gauge to become ready */
  5307. + ret = regmap_read_poll_timeout(cw_bat->regmap, CW2015_REG_SOC,
  5308. + reg_val, reg_val <= 100,
  5309. + 10 * USEC_PER_MSEC, 10 * USEC_PER_SEC);
  5310. + if (ret)
  5311. + dev_err(cw_bat->dev,
  5312. + "Gauge did not become ready after profile upload\n");
  5313. + else
  5314. + dev_dbg(cw_bat->dev, "Battery profile updated\n");
  5315. +
  5316. + return ret;
  5317. +}
  5318. +
  5319. +static int cw_init(struct cw_battery *cw_bat)
  5320. +{
  5321. + int ret;
  5322. + unsigned int reg_val = CW2015_MODE_SLEEP;
  5323. +
  5324. + if ((reg_val & CW2015_MODE_SLEEP_MASK) == CW2015_MODE_SLEEP) {
  5325. + reg_val = CW2015_MODE_NORMAL;
  5326. + ret = regmap_write(cw_bat->regmap, CW2015_REG_MODE, reg_val);
  5327. + if (ret)
  5328. + return ret;
  5329. + }
  5330. +
  5331. + ret = regmap_read(cw_bat->regmap, CW2015_REG_CONFIG, &reg_val);
  5332. + if (ret)
  5333. + return ret;
  5334. +
  5335. + if ((reg_val & CW2015_MASK_ATHD) != CW2015_ATHD(cw_bat->alert_level)) {
  5336. + dev_dbg(cw_bat->dev, "Setting new alert level\n");
  5337. + reg_val &= ~CW2015_MASK_ATHD;
  5338. + reg_val |= ~CW2015_ATHD(cw_bat->alert_level);
  5339. + ret = regmap_write(cw_bat->regmap, CW2015_REG_CONFIG, reg_val);
  5340. + if (ret)
  5341. + return ret;
  5342. + }
  5343. +
  5344. + ret = regmap_read(cw_bat->regmap, CW2015_REG_CONFIG, &reg_val);
  5345. + if (ret)
  5346. + return ret;
  5347. +
  5348. + if (!(reg_val & CW2015_CONFIG_UPDATE_FLG)) {
  5349. + dev_dbg(cw_bat->dev,
  5350. + "Battery profile not present, uploading battery profile\n");
  5351. + if (cw_bat->bat_profile) {
  5352. + ret = cw_update_profile(cw_bat);
  5353. + if (ret) {
  5354. + dev_err(cw_bat->dev,
  5355. + "Failed to upload battery profile\n");
  5356. + return ret;
  5357. + }
  5358. + } else {
  5359. + dev_warn(cw_bat->dev,
  5360. + "No profile specified, continuing without profile\n");
  5361. + }
  5362. + } else if (cw_bat->bat_profile) {
  5363. + u8 bat_info[CW2015_SIZE_BATINFO];
  5364. +
  5365. + ret = regmap_raw_read(cw_bat->regmap, CW2015_REG_BATINFO,
  5366. + bat_info, CW2015_SIZE_BATINFO);
  5367. + if (ret) {
  5368. + dev_err(cw_bat->dev,
  5369. + "Failed to read stored battery profile\n");
  5370. + return ret;
  5371. + }
  5372. +
  5373. + if (memcmp(bat_info, cw_bat->bat_profile, CW2015_SIZE_BATINFO)) {
  5374. + dev_warn(cw_bat->dev, "Replacing stored battery profile\n");
  5375. + ret = cw_update_profile(cw_bat);
  5376. + if (ret)
  5377. + return ret;
  5378. + }
  5379. + } else {
  5380. + dev_warn(cw_bat->dev,
  5381. + "Can't check current battery profile, no profile provided\n");
  5382. + }
  5383. +
  5384. + dev_dbg(cw_bat->dev, "Battery profile configured\n");
  5385. + return 0;
  5386. +}
  5387. +
  5388. +static int cw_power_on_reset(struct cw_battery *cw_bat)
  5389. +{
  5390. + int ret;
  5391. + unsigned char reset_val;
  5392. +
  5393. + reset_val = CW2015_MODE_SLEEP;
  5394. + ret = regmap_write(cw_bat->regmap, CW2015_REG_MODE, reset_val);
  5395. + if (ret)
  5396. + return ret;
  5397. +
  5398. + /* wait for gauge to enter sleep */
  5399. + msleep(20);
  5400. +
  5401. + reset_val = CW2015_MODE_NORMAL;
  5402. + ret = regmap_write(cw_bat->regmap, CW2015_REG_MODE, reset_val);
  5403. + if (ret)
  5404. + return ret;
  5405. +
  5406. + ret = cw_init(cw_bat);
  5407. + if (ret)
  5408. + return ret;
  5409. + return 0;
  5410. +}
  5411. +
  5412. +#define HYSTERESIS(current, previous, up, down) \
  5413. + (((current) < (previous) + (up)) && ((current) > (previous) - (down)))
  5414. +
  5415. +static int cw_get_soc(struct cw_battery *cw_bat)
  5416. +{
  5417. + unsigned int soc;
  5418. + int ret;
  5419. +
  5420. + ret = regmap_read(cw_bat->regmap, CW2015_REG_SOC, &soc);
  5421. + if (ret)
  5422. + return ret;
  5423. +
  5424. + if (soc > 100) {
  5425. + int max_error_cycles =
  5426. + CW2015_BAT_SOC_ERROR_MS / cw_bat->poll_interval_ms;
  5427. +
  5428. + dev_err(cw_bat->dev, "Invalid SoC %d%%\n", soc);
  5429. + cw_bat->read_errors++;
  5430. + if (cw_bat->read_errors > max_error_cycles) {
  5431. + dev_warn(cw_bat->dev,
  5432. + "Too many invalid SoC reports, resetting gauge\n");
  5433. + cw_power_on_reset(cw_bat);
  5434. + cw_bat->read_errors = 0;
  5435. + }
  5436. + return cw_bat->soc;
  5437. + }
  5438. + cw_bat->read_errors = 0;
  5439. +
  5440. + /* Reset gauge if stuck while charging */
  5441. + if (cw_bat->status == POWER_SUPPLY_STATUS_CHARGING && soc == cw_bat->soc) {
  5442. + int max_stuck_cycles =
  5443. + CW2015_BAT_CHARGING_STUCK_MS / cw_bat->poll_interval_ms;
  5444. +
  5445. + cw_bat->charge_stuck_cnt++;
  5446. + if (cw_bat->charge_stuck_cnt > max_stuck_cycles) {
  5447. + dev_warn(cw_bat->dev,
  5448. + "SoC stuck @%u%%, resetting gauge\n", soc);
  5449. + cw_power_on_reset(cw_bat);
  5450. + cw_bat->charge_stuck_cnt = 0;
  5451. + }
  5452. + } else {
  5453. + cw_bat->charge_stuck_cnt = 0;
  5454. + }
  5455. +
  5456. + /* Ignore voltage dips during charge */
  5457. + if (cw_bat->charger_attached && HYSTERESIS(soc, cw_bat->soc, 0, 3))
  5458. + soc = cw_bat->soc;
  5459. +
  5460. + /* Ignore voltage spikes during discharge */
  5461. + if (!cw_bat->charger_attached && HYSTERESIS(soc, cw_bat->soc, 3, 0))
  5462. + soc = cw_bat->soc;
  5463. +
  5464. + return soc;
  5465. +}
  5466. +
  5467. +static int cw_get_voltage(struct cw_battery *cw_bat)
  5468. +{
  5469. + int ret, i, voltage_mv;
  5470. + u16 reg_val;
  5471. + u32 avg = 0;
  5472. +
  5473. + for (i = 0; i < CW2015_AVERAGING_SAMPLES; i++) {
  5474. + ret = cw_read_word(cw_bat, CW2015_REG_VCELL, &reg_val);
  5475. + if (ret)
  5476. + return ret;
  5477. +
  5478. + avg += reg_val;
  5479. + }
  5480. + avg /= CW2015_AVERAGING_SAMPLES;
  5481. +
  5482. + /*
  5483. + * 305 uV per ADC step
  5484. + * Use 312 / 1024 as efficient approximation of 305 / 1000
  5485. + * Negligible error of 0.1%
  5486. + */
  5487. + voltage_mv = avg * 312 / 1024;
  5488. +
  5489. + dev_dbg(cw_bat->dev, "Read voltage: %d mV, raw=0x%04x\n",
  5490. + voltage_mv, reg_val);
  5491. + return voltage_mv;
  5492. +}
  5493. +
  5494. +static int cw_get_time_to_empty(struct cw_battery *cw_bat)
  5495. +{
  5496. + int ret;
  5497. + u16 value16;
  5498. +
  5499. + ret = cw_read_word(cw_bat, CW2015_REG_RRT_ALERT, &value16);
  5500. + if (ret)
  5501. + return ret;
  5502. +
  5503. + return value16 & CW2015_MASK_SOC;
  5504. +}
  5505. +
  5506. +static void cw_update_charge_status(struct cw_battery *cw_bat)
  5507. +{
  5508. + int ret;
  5509. +
  5510. + ret = power_supply_am_i_supplied(cw_bat->rk_bat);
  5511. + if (ret < 0) {
  5512. + dev_warn(cw_bat->dev, "Failed to get supply state: %d\n", ret);
  5513. + } else {
  5514. + bool charger_attached;
  5515. +
  5516. + charger_attached = !!ret;
  5517. + if (cw_bat->charger_attached != charger_attached) {
  5518. + cw_bat->battery_changed = true;
  5519. + if (charger_attached)
  5520. + cw_bat->charge_count++;
  5521. + }
  5522. + cw_bat->charger_attached = charger_attached;
  5523. + }
  5524. +}
  5525. +
  5526. +static void cw_update_soc(struct cw_battery *cw_bat)
  5527. +{
  5528. + int soc;
  5529. +
  5530. + soc = cw_get_soc(cw_bat);
  5531. + if (soc < 0)
  5532. + dev_err(cw_bat->dev, "Failed to get SoC from gauge: %d\n", soc);
  5533. + else if (cw_bat->soc != soc) {
  5534. + cw_bat->soc = soc;
  5535. + cw_bat->battery_changed = true;
  5536. + }
  5537. +}
  5538. +
  5539. +static void cw_update_voltage(struct cw_battery *cw_bat)
  5540. +{
  5541. + int voltage_mv;
  5542. +
  5543. + voltage_mv = cw_get_voltage(cw_bat);
  5544. + if (voltage_mv < 0)
  5545. + dev_err(cw_bat->dev, "Failed to get voltage from gauge: %d\n",
  5546. + voltage_mv);
  5547. + else
  5548. + cw_bat->voltage_mv = voltage_mv;
  5549. +}
  5550. +
  5551. +static void cw_update_status(struct cw_battery *cw_bat)
  5552. +{
  5553. + int status = POWER_SUPPLY_STATUS_DISCHARGING;
  5554. +
  5555. + if (cw_bat->charger_attached) {
  5556. + if (cw_bat->soc >= 100)
  5557. + status = POWER_SUPPLY_STATUS_FULL;
  5558. + else
  5559. + status = POWER_SUPPLY_STATUS_CHARGING;
  5560. + }
  5561. +
  5562. + if (cw_bat->status != status)
  5563. + cw_bat->battery_changed = true;
  5564. + cw_bat->status = status;
  5565. +}
  5566. +
  5567. +static void cw_update_time_to_empty(struct cw_battery *cw_bat)
  5568. +{
  5569. + int time_to_empty;
  5570. +
  5571. + time_to_empty = cw_get_time_to_empty(cw_bat);
  5572. + if (time_to_empty < 0)
  5573. + dev_err(cw_bat->dev, "Failed to get time to empty from gauge: %d\n",
  5574. + time_to_empty);
  5575. + else if (cw_bat->time_to_empty != time_to_empty) {
  5576. + cw_bat->time_to_empty = time_to_empty;
  5577. + cw_bat->battery_changed = true;
  5578. + }
  5579. +}
  5580. +
  5581. +static void cw_bat_work(struct work_struct *work)
  5582. +{
  5583. + struct delayed_work *delay_work;
  5584. + struct cw_battery *cw_bat;
  5585. + int ret;
  5586. + unsigned int reg_val;
  5587. +
  5588. + delay_work = to_delayed_work(work);
  5589. + cw_bat = container_of(delay_work, struct cw_battery, battery_delay_work);
  5590. + ret = regmap_read(cw_bat->regmap, CW2015_REG_MODE, &reg_val);
  5591. + if (ret) {
  5592. + dev_err(cw_bat->dev, "Failed to read mode from gauge: %d\n", ret);
  5593. + } else {
  5594. + if ((reg_val & CW2015_MODE_SLEEP_MASK) == CW2015_MODE_SLEEP) {
  5595. + int i;
  5596. +
  5597. + for (i = 0; i < CW2015_RESET_TRIES; i++) {
  5598. + if (!cw_power_on_reset(cw_bat))
  5599. + break;
  5600. + }
  5601. + }
  5602. + cw_update_soc(cw_bat);
  5603. + cw_update_voltage(cw_bat);
  5604. + cw_update_charge_status(cw_bat);
  5605. + cw_update_status(cw_bat);
  5606. + cw_update_time_to_empty(cw_bat);
  5607. + }
  5608. + dev_dbg(cw_bat->dev, "charger_attached = %d\n", cw_bat->charger_attached);
  5609. + dev_dbg(cw_bat->dev, "status = %d\n", cw_bat->status);
  5610. + dev_dbg(cw_bat->dev, "soc = %d%%\n", cw_bat->soc);
  5611. + dev_dbg(cw_bat->dev, "voltage = %dmV\n", cw_bat->voltage_mv);
  5612. +
  5613. + if (cw_bat->battery_changed)
  5614. + power_supply_changed(cw_bat->rk_bat);
  5615. + cw_bat->battery_changed = false;
  5616. +
  5617. + queue_delayed_work(cw_bat->battery_workqueue,
  5618. + &cw_bat->battery_delay_work,
  5619. + msecs_to_jiffies(cw_bat->poll_interval_ms));
  5620. +}
  5621. +
  5622. +static bool cw_battery_valid_time_to_empty(struct cw_battery *cw_bat)
  5623. +{
  5624. + return cw_bat->time_to_empty > 0 &&
  5625. + cw_bat->time_to_empty < CW2015_MASK_SOC &&
  5626. + cw_bat->status == POWER_SUPPLY_STATUS_DISCHARGING;
  5627. +}
  5628. +
  5629. +static int cw_battery_get_property(struct power_supply *psy,
  5630. + enum power_supply_property psp,
  5631. + union power_supply_propval *val)
  5632. +{
  5633. + struct cw_battery *cw_bat;
  5634. +
  5635. + cw_bat = power_supply_get_drvdata(psy);
  5636. + switch (psp) {
  5637. + case POWER_SUPPLY_PROP_CAPACITY:
  5638. + val->intval = cw_bat->soc;
  5639. + break;
  5640. +
  5641. + case POWER_SUPPLY_PROP_STATUS:
  5642. + val->intval = cw_bat->status;
  5643. + break;
  5644. +
  5645. + case POWER_SUPPLY_PROP_PRESENT:
  5646. + val->intval = !!cw_bat->voltage_mv;
  5647. + break;
  5648. +
  5649. + case POWER_SUPPLY_PROP_VOLTAGE_NOW:
  5650. + val->intval = cw_bat->voltage_mv * 1000;
  5651. + break;
  5652. +
  5653. + case POWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW:
  5654. + if (cw_battery_valid_time_to_empty(cw_bat))
  5655. + val->intval = cw_bat->time_to_empty;
  5656. + else
  5657. + val->intval = 0;
  5658. + break;
  5659. +
  5660. + case POWER_SUPPLY_PROP_TECHNOLOGY:
  5661. + val->intval = POWER_SUPPLY_TECHNOLOGY_LION;
  5662. + break;
  5663. +
  5664. + case POWER_SUPPLY_PROP_CHARGE_COUNTER:
  5665. + val->intval = cw_bat->charge_count;
  5666. + break;
  5667. +
  5668. + case POWER_SUPPLY_PROP_CHARGE_FULL:
  5669. + case POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN:
  5670. + if (cw_bat->battery.charge_full_design_uah > 0)
  5671. + val->intval = cw_bat->battery.charge_full_design_uah;
  5672. + else
  5673. + val->intval = 0;
  5674. + break;
  5675. +
  5676. + case POWER_SUPPLY_PROP_CURRENT_NOW:
  5677. + if (cw_battery_valid_time_to_empty(cw_bat) &&
  5678. + cw_bat->battery.charge_full_design_uah > 0) {
  5679. + /* calculate remaining capacity */
  5680. + val->intval = cw_bat->battery.charge_full_design_uah;
  5681. + val->intval = val->intval * cw_bat->soc / 100;
  5682. +
  5683. + /* estimate current based on time to empty */
  5684. + val->intval = 60 * val->intval / cw_bat->time_to_empty;
  5685. + } else {
  5686. + val->intval = 0;
  5687. + }
  5688. +
  5689. + break;
  5690. +
  5691. + default:
  5692. + break;
  5693. + }
  5694. + return 0;
  5695. +}
  5696. +
  5697. +static enum power_supply_property cw_battery_properties[] = {
  5698. + POWER_SUPPLY_PROP_CAPACITY,
  5699. + POWER_SUPPLY_PROP_STATUS,
  5700. + POWER_SUPPLY_PROP_PRESENT,
  5701. + POWER_SUPPLY_PROP_VOLTAGE_NOW,
  5702. + POWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW,
  5703. + POWER_SUPPLY_PROP_TECHNOLOGY,
  5704. + POWER_SUPPLY_PROP_CHARGE_COUNTER,
  5705. + POWER_SUPPLY_PROP_CHARGE_FULL,
  5706. + POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN,
  5707. + POWER_SUPPLY_PROP_CURRENT_NOW,
  5708. +};
  5709. +
  5710. +static const struct power_supply_desc cw2015_bat_desc = {
  5711. + .name = "cw2015-battery",
  5712. + .type = POWER_SUPPLY_TYPE_BATTERY,
  5713. + .properties = cw_battery_properties,
  5714. + .num_properties = ARRAY_SIZE(cw_battery_properties),
  5715. + .get_property = cw_battery_get_property,
  5716. +};
  5717. +
  5718. +static int cw2015_parse_properties(struct cw_battery *cw_bat)
  5719. +{
  5720. + struct device *dev = cw_bat->dev;
  5721. + int length;
  5722. + int ret;
  5723. +
  5724. + length = device_property_count_u8(dev, "cellwise,battery-profile");
  5725. + if (length < 0) {
  5726. + dev_warn(cw_bat->dev,
  5727. + "No battery-profile found, using current flash contents\n");
  5728. + } else if (length != CW2015_SIZE_BATINFO) {
  5729. + dev_err(cw_bat->dev, "battery-profile must be %d bytes\n",
  5730. + CW2015_SIZE_BATINFO);
  5731. + return -EINVAL;
  5732. + } else {
  5733. + cw_bat->bat_profile = devm_kzalloc(dev, length, GFP_KERNEL);
  5734. + if (!cw_bat->bat_profile)
  5735. + return -ENOMEM;
  5736. +
  5737. + ret = device_property_read_u8_array(dev,
  5738. + "cellwise,battery-profile",
  5739. + cw_bat->bat_profile,
  5740. + length);
  5741. + if (ret)
  5742. + return ret;
  5743. + }
  5744. +
  5745. + ret = device_property_read_u32(dev, "cellwise,monitor-interval-ms",
  5746. + &cw_bat->poll_interval_ms);
  5747. + if (ret) {
  5748. + dev_dbg(cw_bat->dev, "Using default poll interval\n");
  5749. + cw_bat->poll_interval_ms = CW2015_DEFAULT_POLL_INTERVAL_MS;
  5750. + }
  5751. +
  5752. + return 0;
  5753. +}
  5754. +
  5755. +static const struct regmap_range regmap_ranges_rd_yes[] = {
  5756. + regmap_reg_range(CW2015_REG_VERSION, CW2015_REG_VERSION),
  5757. + regmap_reg_range(CW2015_REG_VCELL, CW2015_REG_CONFIG),
  5758. + regmap_reg_range(CW2015_REG_MODE, CW2015_REG_MODE),
  5759. + regmap_reg_range(CW2015_REG_BATINFO,
  5760. + CW2015_REG_BATINFO + CW2015_SIZE_BATINFO - 1),
  5761. +};
  5762. +
  5763. +static const struct regmap_access_table regmap_rd_table = {
  5764. + .yes_ranges = regmap_ranges_rd_yes,
  5765. + .n_yes_ranges = 4,
  5766. +};
  5767. +
  5768. +static const struct regmap_range regmap_ranges_wr_yes[] = {
  5769. + regmap_reg_range(CW2015_REG_RRT_ALERT, CW2015_REG_CONFIG),
  5770. + regmap_reg_range(CW2015_REG_MODE, CW2015_REG_MODE),
  5771. + regmap_reg_range(CW2015_REG_BATINFO,
  5772. + CW2015_REG_BATINFO + CW2015_SIZE_BATINFO - 1),
  5773. +};
  5774. +
  5775. +static const struct regmap_access_table regmap_wr_table = {
  5776. + .yes_ranges = regmap_ranges_wr_yes,
  5777. + .n_yes_ranges = 3,
  5778. +};
  5779. +
  5780. +static const struct regmap_range regmap_ranges_vol_yes[] = {
  5781. + regmap_reg_range(CW2015_REG_VCELL, CW2015_REG_SOC + 1),
  5782. +};
  5783. +
  5784. +static const struct regmap_access_table regmap_vol_table = {
  5785. + .yes_ranges = regmap_ranges_vol_yes,
  5786. + .n_yes_ranges = 1,
  5787. +};
  5788. +
  5789. +static const struct regmap_config cw2015_regmap_config = {
  5790. + .reg_bits = 8,
  5791. + .val_bits = 8,
  5792. + .rd_table = &regmap_rd_table,
  5793. + .wr_table = &regmap_wr_table,
  5794. + .volatile_table = &regmap_vol_table,
  5795. + .max_register = CW2015_REG_BATINFO + CW2015_SIZE_BATINFO - 1,
  5796. +};
  5797. +
  5798. +static int cw_bat_probe(struct i2c_client *client)
  5799. +{
  5800. + int ret;
  5801. + struct cw_battery *cw_bat;
  5802. + struct power_supply_config psy_cfg = { 0 };
  5803. +
  5804. + cw_bat = devm_kzalloc(&client->dev, sizeof(*cw_bat), GFP_KERNEL);
  5805. + if (!cw_bat)
  5806. + return -ENOMEM;
  5807. +
  5808. + i2c_set_clientdata(client, cw_bat);
  5809. + cw_bat->dev = &client->dev;
  5810. + cw_bat->soc = 1;
  5811. +
  5812. + ret = cw2015_parse_properties(cw_bat);
  5813. + if (ret) {
  5814. + dev_err(cw_bat->dev, "Failed to parse cw2015 properties\n");
  5815. + return ret;
  5816. + }
  5817. +
  5818. + cw_bat->regmap = devm_regmap_init_i2c(client, &cw2015_regmap_config);
  5819. + if (IS_ERR(cw_bat->regmap)) {
  5820. + dev_err(cw_bat->dev, "Failed to allocate regmap: %ld\n",
  5821. + PTR_ERR(cw_bat->regmap));
  5822. + return PTR_ERR(cw_bat->regmap);
  5823. + }
  5824. +
  5825. + ret = cw_init(cw_bat);
  5826. + if (ret) {
  5827. + dev_err(cw_bat->dev, "Init failed: %d\n", ret);
  5828. + return ret;
  5829. + }
  5830. +
  5831. + psy_cfg.drv_data = cw_bat;
  5832. + psy_cfg.fwnode = dev_fwnode(cw_bat->dev);
  5833. +
  5834. + cw_bat->rk_bat = devm_power_supply_register(&client->dev,
  5835. + &cw2015_bat_desc,
  5836. + &psy_cfg);
  5837. + if (IS_ERR(cw_bat->rk_bat)) {
  5838. + dev_err(cw_bat->dev, "Failed to register power supply\n");
  5839. + return PTR_ERR(cw_bat->rk_bat);
  5840. + }
  5841. +
  5842. + ret = power_supply_get_battery_info(cw_bat->rk_bat, &cw_bat->battery);
  5843. + if (ret) {
  5844. + dev_warn(cw_bat->dev,
  5845. + "No monitored battery, some properties will be missing\n");
  5846. + }
  5847. +
  5848. + cw_bat->battery_workqueue = create_singlethread_workqueue("rk_battery");
  5849. + INIT_DELAYED_WORK(&cw_bat->battery_delay_work, cw_bat_work);
  5850. + queue_delayed_work(cw_bat->battery_workqueue,
  5851. + &cw_bat->battery_delay_work, msecs_to_jiffies(10));
  5852. + return 0;
  5853. +}
  5854. +
  5855. +static int __maybe_unused cw_bat_suspend(struct device *dev)
  5856. +{
  5857. + struct i2c_client *client = to_i2c_client(dev);
  5858. + struct cw_battery *cw_bat = i2c_get_clientdata(client);
  5859. +
  5860. + cancel_delayed_work_sync(&cw_bat->battery_delay_work);
  5861. + return 0;
  5862. +}
  5863. +
  5864. +static int __maybe_unused cw_bat_resume(struct device *dev)
  5865. +{
  5866. + struct i2c_client *client = to_i2c_client(dev);
  5867. + struct cw_battery *cw_bat = i2c_get_clientdata(client);
  5868. +
  5869. + queue_delayed_work(cw_bat->battery_workqueue,
  5870. + &cw_bat->battery_delay_work, 0);
  5871. + return 0;
  5872. +}
  5873. +
  5874. +SIMPLE_DEV_PM_OPS(cw_bat_pm_ops, cw_bat_suspend, cw_bat_resume);
  5875. +
  5876. +static int cw_bat_remove(struct i2c_client *client)
  5877. +{
  5878. + struct cw_battery *cw_bat = i2c_get_clientdata(client);
  5879. +
  5880. + cancel_delayed_work_sync(&cw_bat->battery_delay_work);
  5881. + power_supply_put_battery_info(cw_bat->rk_bat, &cw_bat->battery);
  5882. + return 0;
  5883. +}
  5884. +
  5885. +static const struct i2c_device_id cw_bat_id_table[] = {
  5886. + { "cw2015", 0 },
  5887. + { }
  5888. +};
  5889. +
  5890. +static const struct of_device_id cw2015_of_match[] = {
  5891. + { .compatible = "cellwise,cw2015" },
  5892. + { }
  5893. +};
  5894. +MODULE_DEVICE_TABLE(of, cw2015_of_match);
  5895. +
  5896. +static struct i2c_driver cw_bat_driver = {
  5897. + .driver = {
  5898. + .name = "cw2015",
  5899. + .pm = &cw_bat_pm_ops,
  5900. + },
  5901. + .probe_new = cw_bat_probe,
  5902. + .remove = cw_bat_remove,
  5903. + .id_table = cw_bat_id_table,
  5904. +};
  5905. +
  5906. +module_i2c_driver(cw_bat_driver);
  5907. +
  5908. +MODULE_AUTHOR("xhc<xhc@rock-chips.com>");
  5909. +MODULE_AUTHOR("Tobias Schramm <t.schramm@manjaro.org>");
  5910. +MODULE_DESCRIPTION("cw2015/cw2013 battery driver");
  5911. +MODULE_LICENSE("GPL");
  5912. diff -uNr '--exclude=.git' linux-5.6-rc7/drivers/power/supply/Kconfig linux-pinebook-pro_v5.6/drivers/power/supply/Kconfig
  5913. --- linux-5.6-rc7/drivers/power/supply/Kconfig 2020-03-22 18:31:56.000000000 -0700
  5914. +++ linux-pinebook-pro_v5.6/drivers/power/supply/Kconfig 2020-03-23 07:26:36.000000000 -0700
  5915. @@ -116,6 +116,17 @@
  5916. Say Y here to enable support for battery on Motorola
  5917. phones and tablets such as droid 4.
  5918.  
  5919. +config BATTERY_CW2015
  5920. + tristate "CW2015 Battery driver"
  5921. + depends on I2C
  5922. + select REGMAP_I2C
  5923. + help
  5924. + Say Y here to enable support for the cellwise cw2015
  5925. + battery fuel gauge (used in the Pinebook Pro & others)
  5926. +
  5927. + This driver can also be built as a module. If so, the module will be
  5928. + called cw2015_battery.
  5929. +
  5930. config BATTERY_DS2760
  5931. tristate "DS2760 battery driver (HP iPAQ & others)"
  5932. depends on W1
  5933. diff -uNr '--exclude=.git' linux-5.6-rc7/drivers/power/supply/Makefile linux-pinebook-pro_v5.6/drivers/power/supply/Makefile
  5934. --- linux-5.6-rc7/drivers/power/supply/Makefile 2020-03-22 18:31:56.000000000 -0700
  5935. +++ linux-pinebook-pro_v5.6/drivers/power/supply/Makefile 2020-03-23 07:26:36.000000000 -0700
  5936. @@ -24,6 +24,7 @@
  5937. obj-$(CONFIG_BATTERY_AXP20X) += axp20x_battery.o
  5938. obj-$(CONFIG_CHARGER_AXP20X) += axp20x_ac_power.o
  5939. obj-$(CONFIG_BATTERY_CPCAP) += cpcap-battery.o
  5940. +obj-$(CONFIG_BATTERY_CW2015) += cw2015_battery.o
  5941. obj-$(CONFIG_BATTERY_DS2760) += ds2760_battery.o
  5942. obj-$(CONFIG_BATTERY_DS2780) += ds2780_battery.o
  5943. obj-$(CONFIG_BATTERY_DS2781) += ds2781_battery.o
  5944. diff -uNr '--exclude=.git' linux-5.6-rc7/drivers/regulator/core.c linux-pinebook-pro_v5.6/drivers/regulator/core.c
  5945. --- linux-5.6-rc7/drivers/regulator/core.c 2020-03-22 18:31:56.000000000 -0700
  5946. +++ linux-pinebook-pro_v5.6/drivers/regulator/core.c 2020-03-23 07:26:36.000000000 -0700
  5947. @@ -5271,6 +5271,14 @@
  5948. EXPORT_SYMBOL_GPL(regulator_unregister);
  5949.  
  5950. #ifdef CONFIG_SUSPEND
  5951. +static inline int can_enable(struct regulator_dev *rdev) {
  5952. + return rdev->ena_pin || rdev->desc->ops->enable;
  5953. +}
  5954. +
  5955. +static inline int can_disable(struct regulator_dev *rdev) {
  5956. + return rdev->ena_pin || rdev->desc->ops->disable;
  5957. +}
  5958. +
  5959. /**
  5960. * regulator_suspend - prepare regulators for system wide suspend
  5961. * @dev: ``&struct device`` pointer that is passed to _regulator_suspend()
  5962. @@ -5281,10 +5289,33 @@
  5963. {
  5964. struct regulator_dev *rdev = dev_to_rdev(dev);
  5965. suspend_state_t state = pm_suspend_target_state;
  5966. + struct regulator_state *rstate;
  5967. int ret;
  5968.  
  5969. regulator_lock(rdev);
  5970. ret = suspend_set_state(rdev, state);
  5971. + if (ret) {
  5972. + goto out;
  5973. + }
  5974. +
  5975. + rstate = regulator_get_suspend_state(rdev, state);
  5976. + if (rstate == NULL)
  5977. + goto out;
  5978. +
  5979. + if (rstate->enabled == ENABLE_IN_SUSPEND && can_enable(rdev)) {
  5980. + if (!rdev->desc->ops->set_suspend_enable) {
  5981. + rdev->resume_state = _regulator_is_enabled(rdev);
  5982. + rdev_info(rdev, "Entering suspend %d, enabling forcibly, was %s\n", state, rdev->resume_state ? "on" : "off");
  5983. + ret = _regulator_do_enable(rdev);
  5984. + }
  5985. + } else if (rstate->enabled == DISABLE_IN_SUSPEND && can_disable(rdev)) {
  5986. + if (!rdev->desc->ops->set_suspend_disable) {
  5987. + rdev->resume_state = _regulator_is_enabled(rdev);
  5988. + rdev_info(rdev, "Entering suspend %d, disabling forcibly, was %s\n", state, rdev->resume_state ? "on" : "off");
  5989. + ret = _regulator_do_disable(rdev);
  5990. + }
  5991. + }
  5992. +out:
  5993. regulator_unlock(rdev);
  5994.  
  5995. return ret;
  5996. @@ -5303,10 +5334,19 @@
  5997.  
  5998. regulator_lock(rdev);
  5999.  
  6000. - if (rdev->desc->ops->resume &&
  6001. - (rstate->enabled == ENABLE_IN_SUSPEND ||
  6002. - rstate->enabled == DISABLE_IN_SUSPEND))
  6003. - ret = rdev->desc->ops->resume(rdev);
  6004. + if (rstate->enabled == ENABLE_IN_SUSPEND || rstate->enabled == DISABLE_IN_SUSPEND) {
  6005. + if (rdev->desc->ops->resume) {
  6006. + ret = rdev->desc->ops->resume(rdev);
  6007. + } else if ((rstate->enabled == ENABLE_IN_SUSPEND && !rdev->desc->ops->set_suspend_enable) ||
  6008. + (rstate->enabled == DISABLE_IN_SUSPEND && !rdev->desc->ops->set_suspend_disable)) {
  6009. + rdev_info(rdev, "Resuming, restoring state to %s\n", rdev->resume_state ? "on" : "off");
  6010. + if (rdev->resume_state && can_enable(rdev)) {
  6011. + ret = _regulator_do_enable(rdev);
  6012. + } else if (!rdev->resume_state && can_disable(rdev)) {
  6013. + ret = _regulator_do_disable(rdev);
  6014. + }
  6015. + }
  6016. + }
  6017.  
  6018. regulator_unlock(rdev);
  6019.  
  6020. diff -uNr '--exclude=.git' linux-5.6-rc7/drivers/soc/rockchip/Kconfig linux-pinebook-pro_v5.6/drivers/soc/rockchip/Kconfig
  6021. --- linux-5.6-rc7/drivers/soc/rockchip/Kconfig 2020-03-22 18:31:56.000000000 -0700
  6022. +++ linux-pinebook-pro_v5.6/drivers/soc/rockchip/Kconfig 2020-03-23 07:26:36.000000000 -0700
  6023. @@ -26,4 +26,10 @@
  6024.  
  6025. If unsure, say N.
  6026.  
  6027. +config ROCKCHIP_SUSPEND_MODE
  6028. + bool "Rockchip suspend mode config"
  6029. + depends on ROCKCHIP_SIP
  6030. + help
  6031. + Say Y here if you want to set the suspend mode to the ATF.
  6032. +
  6033. endif
  6034. diff -uNr '--exclude=.git' linux-5.6-rc7/drivers/soc/rockchip/Makefile linux-pinebook-pro_v5.6/drivers/soc/rockchip/Makefile
  6035. --- linux-5.6-rc7/drivers/soc/rockchip/Makefile 2020-03-22 18:31:56.000000000 -0700
  6036. +++ linux-pinebook-pro_v5.6/drivers/soc/rockchip/Makefile 2020-03-23 07:26:36.000000000 -0700
  6037. @@ -4,3 +4,4 @@
  6038. #
  6039. obj-$(CONFIG_ROCKCHIP_GRF) += grf.o
  6040. obj-$(CONFIG_ROCKCHIP_PM_DOMAINS) += pm_domains.o
  6041. +obj-$(CONFIG_ROCKCHIP_SUSPEND_MODE) += rockchip_pm_config.o
  6042. diff -uNr '--exclude=.git' linux-5.6-rc7/drivers/soc/rockchip/rockchip_pm_config.c linux-pinebook-pro_v5.6/drivers/soc/rockchip/rockchip_pm_config.c
  6043. --- linux-5.6-rc7/drivers/soc/rockchip/rockchip_pm_config.c 1969-12-31 16:00:00.000000000 -0800
  6044. +++ linux-pinebook-pro_v5.6/drivers/soc/rockchip/rockchip_pm_config.c 2020-03-23 07:26:36.000000000 -0700
  6045. @@ -0,0 +1,212 @@
  6046. +/*
  6047. + * Rockchip Generic power configuration support.
  6048. + *
  6049. + * Copyright (c) 2017 ROCKCHIP, Co. Ltd.
  6050. + *
  6051. + * This program is free software; you can redistribute it and/or modify
  6052. + * it under the terms of the GNU General Public License version 2 as
  6053. + * published by the Free Software Foundation.
  6054. + */
  6055. +
  6056. +#include <linux/arm-smccc.h>
  6057. +#include <linux/bitops.h>
  6058. +#include <linux/cpu.h>
  6059. +#include <linux/of_gpio.h>
  6060. +#include <linux/platform_device.h>
  6061. +#include <linux/regulator/machine.h>
  6062. +#include <linux/rockchip/rockchip_sip.h>
  6063. +#include <linux/suspend.h>
  6064. +#include <dt-bindings/input/input.h>
  6065. +
  6066. +#define PM_INVALID_GPIO 0xffff
  6067. +
  6068. +static const struct of_device_id pm_match_table[] = {
  6069. + { .compatible = "rockchip,pm-rk3399",},
  6070. + { },
  6071. +};
  6072. +
  6073. +#define MAX_PWRKEY_NUMS 20
  6074. +#define MAX_NUM_KEYS 60
  6075. +
  6076. +struct rkxx_remote_key_table {
  6077. + int scancode;
  6078. + int keycode;
  6079. +};
  6080. +
  6081. +static int parse_ir_pwrkeys(unsigned int *pwrkey, int size, int *nkey)
  6082. +{
  6083. + struct device_node *node;
  6084. + struct device_node *child_node;
  6085. + struct rkxx_remote_key_table key_table[MAX_NUM_KEYS];
  6086. + int i;
  6087. + int len = 0, nbuttons;
  6088. + int num = 0;
  6089. + u32 usercode, scancode;
  6090. +
  6091. + for_each_node_by_name(node, "pwm") {
  6092. + for_each_child_of_node(node, child_node) {
  6093. + if (of_property_read_u32(child_node,
  6094. + "rockchip,usercode",
  6095. + &usercode))
  6096. + break;
  6097. +
  6098. + if (of_get_property(child_node,
  6099. + "rockchip,key_table",
  6100. + &len) == NULL ||
  6101. + len <= 0)
  6102. + break;
  6103. +
  6104. + len = len < sizeof(key_table) ? len : sizeof(key_table);
  6105. + len /= sizeof(u32);
  6106. + if (of_property_read_u32_array(child_node,
  6107. + "rockchip,key_table",
  6108. + (u32 *)key_table,
  6109. + len))
  6110. + break;
  6111. +
  6112. + nbuttons = len / 2;
  6113. + for (i = 0; i < nbuttons && num < size; ++i) {
  6114. + if (key_table[i].keycode == KEY_POWER) {
  6115. + scancode = key_table[i].scancode;
  6116. + pr_debug("usercode=%x, key=%x\n",
  6117. + usercode, scancode);
  6118. + pwrkey[num] = (usercode & 0xffff) << 16;
  6119. + pwrkey[num] |= (scancode & 0xff) << 8;
  6120. + ++num;
  6121. + }
  6122. + }
  6123. + }
  6124. + }
  6125. +
  6126. + *nkey = num;
  6127. +
  6128. + return num ? 0 : -1;
  6129. +}
  6130. +
  6131. +static void rockchip_pm_virt_pwroff_prepare(void)
  6132. +{
  6133. + int error;
  6134. + int i, nkey;
  6135. + u32 power_key[MAX_PWRKEY_NUMS];
  6136. +
  6137. + if ((parse_ir_pwrkeys(power_key, ARRAY_SIZE(power_key), &nkey))) {
  6138. + pr_err("Parse ir powerkey code failed!\n");
  6139. + return;
  6140. + }
  6141. +
  6142. + for (i = 0; i < nkey; ++i)
  6143. + sip_smc_set_suspend_mode(VIRTUAL_POWEROFF, 1, power_key[i]);
  6144. +
  6145. + regulator_suspend_prepare(PM_SUSPEND_MEM);
  6146. +
  6147. + error = disable_nonboot_cpus();
  6148. + if (error) {
  6149. + pr_err("Disable nonboot cpus failed!\n");
  6150. + return;
  6151. + }
  6152. +
  6153. + sip_smc_set_suspend_mode(VIRTUAL_POWEROFF, 0, 1);
  6154. + sip_smc_virtual_poweroff();
  6155. +}
  6156. +
  6157. +static int __init pm_config_init(struct platform_device *pdev)
  6158. +{
  6159. + const struct of_device_id *match_id;
  6160. + struct device_node *node;
  6161. + u32 mode_config = 0;
  6162. + u32 wakeup_config = 0;
  6163. + u32 pwm_regulator_config = 0;
  6164. + int gpio_temp[10];
  6165. + u32 sleep_debug_en = 0;
  6166. + u32 apios_suspend = 0;
  6167. + u32 virtual_poweroff_en = 0;
  6168. + enum of_gpio_flags flags;
  6169. + int i = 0;
  6170. + int length;
  6171. +
  6172. + match_id = of_match_node(pm_match_table, pdev->dev.of_node);
  6173. + if (!match_id)
  6174. + return -ENODEV;
  6175. +
  6176. + node = of_find_node_by_name(NULL, "rockchip-suspend");
  6177. +
  6178. + if (IS_ERR_OR_NULL(node)) {
  6179. + dev_err(&pdev->dev, "%s dev node err\n", __func__);
  6180. + return -ENODEV;
  6181. + }
  6182. +
  6183. + if (of_property_read_u32_array(node,
  6184. + "rockchip,sleep-mode-config",
  6185. + &mode_config, 1))
  6186. + dev_warn(&pdev->dev, "not set sleep mode config\n");
  6187. + else
  6188. + sip_smc_set_suspend_mode(SUSPEND_MODE_CONFIG, mode_config, 0);
  6189. +
  6190. + if (of_property_read_u32_array(node,
  6191. + "rockchip,wakeup-config",
  6192. + &wakeup_config, 1))
  6193. + dev_warn(&pdev->dev, "not set wakeup-config\n");
  6194. + else
  6195. + sip_smc_set_suspend_mode(WKUP_SOURCE_CONFIG, wakeup_config, 0);
  6196. +
  6197. + if (of_property_read_u32_array(node,
  6198. + "rockchip,pwm-regulator-config",
  6199. + &pwm_regulator_config, 1))
  6200. + dev_warn(&pdev->dev, "not set pwm-regulator-config\n");
  6201. + else
  6202. + sip_smc_set_suspend_mode(PWM_REGULATOR_CONFIG,
  6203. + pwm_regulator_config,
  6204. + 0);
  6205. +
  6206. + length = of_gpio_named_count(node, "rockchip,power-ctrl");
  6207. +
  6208. + if (length > 0 && length < 10) {
  6209. + for (i = 0; i < length; i++) {
  6210. + gpio_temp[i] = of_get_named_gpio_flags(node,
  6211. + "rockchip,power-ctrl",
  6212. + i,
  6213. + &flags);
  6214. + if (!gpio_is_valid(gpio_temp[i]))
  6215. + break;
  6216. + sip_smc_set_suspend_mode(GPIO_POWER_CONFIG,
  6217. + i,
  6218. + gpio_temp[i]);
  6219. + }
  6220. + }
  6221. + sip_smc_set_suspend_mode(GPIO_POWER_CONFIG, i, PM_INVALID_GPIO);
  6222. +
  6223. + if (!of_property_read_u32_array(node,
  6224. + "rockchip,sleep-debug-en",
  6225. + &sleep_debug_en, 1))
  6226. + sip_smc_set_suspend_mode(SUSPEND_DEBUG_ENABLE,
  6227. + sleep_debug_en,
  6228. + 0);
  6229. +
  6230. + if (!of_property_read_u32_array(node,
  6231. + "rockchip,apios-suspend",
  6232. + &apios_suspend, 1))
  6233. + sip_smc_set_suspend_mode(APIOS_SUSPEND_CONFIG,
  6234. + apios_suspend,
  6235. + 0);
  6236. +
  6237. + if (!of_property_read_u32_array(node,
  6238. + "rockchip,virtual-poweroff",
  6239. + &virtual_poweroff_en, 1) &&
  6240. + virtual_poweroff_en)
  6241. + pm_power_off_prepare = rockchip_pm_virt_pwroff_prepare;
  6242. +
  6243. + return 0;
  6244. +}
  6245. +
  6246. +static struct platform_driver pm_driver = {
  6247. + .driver = {
  6248. + .name = "rockchip-pm",
  6249. + .of_match_table = pm_match_table,
  6250. + },
  6251. +};
  6252. +
  6253. +static int __init rockchip_pm_drv_register(void)
  6254. +{
  6255. + return platform_driver_probe(&pm_driver, pm_config_init);
  6256. +}
  6257. +subsys_initcall(rockchip_pm_drv_register);
  6258. diff -uNr '--exclude=.git' linux-5.6-rc7/drivers/tty/serdev/core.c linux-pinebook-pro_v5.6/drivers/tty/serdev/core.c
  6259. --- linux-5.6-rc7/drivers/tty/serdev/core.c 2020-03-22 18:31:56.000000000 -0700
  6260. +++ linux-pinebook-pro_v5.6/drivers/tty/serdev/core.c 2020-03-23 07:26:36.000000000 -0700
  6261. @@ -432,11 +432,22 @@
  6262. return 0;
  6263. }
  6264.  
  6265. +static void serdev_drv_shutdown(struct device *dev)
  6266. +{
  6267. + const struct serdev_device_driver *sdrv;
  6268. + if (dev->driver) {
  6269. + sdrv = to_serdev_device_driver(dev->driver);
  6270. + if (sdrv->shutdown)
  6271. + sdrv->shutdown(to_serdev_device(dev));
  6272. + }
  6273. +}
  6274. +
  6275. static struct bus_type serdev_bus_type = {
  6276. .name = "serial",
  6277. .match = serdev_device_match,
  6278. .probe = serdev_drv_probe,
  6279. .remove = serdev_drv_remove,
  6280. + .shutdown = serdev_drv_shutdown,
  6281. };
  6282.  
  6283. /**
  6284. diff -uNr '--exclude=.git' linux-5.6-rc7/drivers/usb/typec/altmodes/displayport.c linux-pinebook-pro_v5.6/drivers/usb/typec/altmodes/displayport.c
  6285. --- linux-5.6-rc7/drivers/usb/typec/altmodes/displayport.c 2020-03-22 18:31:56.000000000 -0700
  6286. +++ linux-pinebook-pro_v5.6/drivers/usb/typec/altmodes/displayport.c 2020-03-23 07:26:36.000000000 -0700
  6287. @@ -9,6 +9,8 @@
  6288. */
  6289.  
  6290. #include <linux/delay.h>
  6291. +#include <linux/extcon.h>
  6292. +#include <linux/extcon-provider.h>
  6293. #include <linux/mutex.h>
  6294. #include <linux/module.h>
  6295. #include <linux/usb/pd_vdo.h>
  6296. @@ -134,15 +136,53 @@
  6297. return ret;
  6298. }
  6299.  
  6300. +static void dp_altmode_update_extcon(struct dp_altmode *dp, bool disconnect) {
  6301. + const struct device *dev = &dp->port->dev;
  6302. + struct extcon_dev* edev = NULL;
  6303. +
  6304. + while (dev) {
  6305. + edev = extcon_find_edev_by_node(dev->of_node);
  6306. + if(!IS_ERR(edev)) {
  6307. + break;
  6308. + }
  6309. + dev = dev->parent;
  6310. + }
  6311. +
  6312. + if (IS_ERR_OR_NULL(edev)) {
  6313. + return;
  6314. + }
  6315. +
  6316. + if (disconnect || !dp->data.conf) {
  6317. + extcon_set_state_sync(edev, EXTCON_DISP_DP, false);
  6318. + } else {
  6319. + union extcon_property_value extcon_true = { .intval = true };
  6320. + extcon_set_state(edev, EXTCON_DISP_DP, true);
  6321. + if (DP_CONF_GET_PIN_ASSIGN(dp->data.conf) & DP_PIN_ASSIGN_MULTI_FUNC_MASK) {
  6322. + extcon_set_state_sync(edev, EXTCON_USB_HOST, true);
  6323. + extcon_set_property(edev, EXTCON_DISP_DP, EXTCON_PROP_USB_SS,
  6324. + extcon_true);
  6325. + } else {
  6326. + extcon_set_state_sync(edev, EXTCON_USB_HOST, false);
  6327. + }
  6328. + extcon_sync(edev, EXTCON_DISP_DP);
  6329. + extcon_set_state_sync(edev, EXTCON_USB, false);
  6330. + }
  6331. +
  6332. +}
  6333. +
  6334. static int dp_altmode_configured(struct dp_altmode *dp)
  6335. {
  6336. int ret;
  6337.  
  6338. sysfs_notify(&dp->alt->dev.kobj, "displayport", "configuration");
  6339.  
  6340. - if (!dp->data.conf)
  6341. + if (!dp->data.conf) {
  6342. + dp_altmode_update_extcon(dp, true);
  6343. return typec_altmode_notify(dp->alt, TYPEC_STATE_USB,
  6344. &dp->data);
  6345. + }
  6346. +
  6347. + dp_altmode_update_extcon(dp, false);
  6348.  
  6349. ret = dp_altmode_notify(dp);
  6350. if (ret)
  6351. @@ -169,9 +209,11 @@
  6352. if (ret) {
  6353. if (DP_CONF_GET_PIN_ASSIGN(dp->data.conf))
  6354. dp_altmode_notify(dp);
  6355. - else
  6356. + else {
  6357. + dp_altmode_update_extcon(dp, true);
  6358. typec_altmode_notify(dp->alt, TYPEC_STATE_USB,
  6359. &dp->data);
  6360. + }
  6361. }
  6362.  
  6363. return ret;
  6364. @@ -210,6 +252,8 @@
  6365. case DP_STATE_EXIT:
  6366. if (typec_altmode_exit(dp->alt))
  6367. dev_err(&dp->alt->dev, "Exit Mode Failed!\n");
  6368. + else
  6369. + dp_altmode_update_extcon(dp, true);
  6370. break;
  6371. default:
  6372. break;
  6373. @@ -520,8 +564,13 @@
  6374. if (!(DP_CAP_DFP_D_PIN_ASSIGN(port->vdo) &
  6375. DP_CAP_UFP_D_PIN_ASSIGN(alt->vdo)) &&
  6376. !(DP_CAP_UFP_D_PIN_ASSIGN(port->vdo) &
  6377. - DP_CAP_DFP_D_PIN_ASSIGN(alt->vdo)))
  6378. + DP_CAP_DFP_D_PIN_ASSIGN(alt->vdo))) {
  6379. + dev_err(&alt->dev, "No compatible pin configuration found:"\
  6380. + "%04lx -> %04lx, %04lx <- %04lx",
  6381. + DP_CAP_DFP_D_PIN_ASSIGN(port->vdo), DP_CAP_UFP_D_PIN_ASSIGN(alt->vdo),
  6382. + DP_CAP_UFP_D_PIN_ASSIGN(port->vdo), DP_CAP_DFP_D_PIN_ASSIGN(alt->vdo));
  6383. return -ENODEV;
  6384. + }
  6385.  
  6386. ret = sysfs_create_group(&alt->dev.kobj, &dp_altmode_group);
  6387. if (ret)
  6388. diff -uNr '--exclude=.git' linux-5.6-rc7/drivers/usb/typec/bus.c linux-pinebook-pro_v5.6/drivers/usb/typec/bus.c
  6389. --- linux-5.6-rc7/drivers/usb/typec/bus.c 2020-03-22 18:31:56.000000000 -0700
  6390. +++ linux-pinebook-pro_v5.6/drivers/usb/typec/bus.c 2020-03-23 07:26:36.000000000 -0700
  6391. @@ -164,8 +164,14 @@
  6392. */
  6393. void typec_altmode_attention(struct typec_altmode *adev, u32 vdo)
  6394. {
  6395. - struct typec_altmode *pdev = &to_altmode(adev)->partner->adev;
  6396. + struct typec_altmode *pdev;
  6397. + WARN_ONCE(!adev, "typec bus attention: adev is NULL!");
  6398. + WARN_ONCE(!to_altmode(adev)->partner, "typec bus attention: partner is NULL!");
  6399. + if(!adev || !to_altmode(adev)->partner) {
  6400. + return;
  6401. + }
  6402.  
  6403. + pdev = &to_altmode(adev)->partner->adev;
  6404. if (pdev->ops && pdev->ops->attention)
  6405. pdev->ops->attention(pdev, vdo);
  6406. }
  6407. diff -uNr '--exclude=.git' linux-5.6-rc7/drivers/usb/typec/tcpm/tcpm.c linux-pinebook-pro_v5.6/drivers/usb/typec/tcpm/tcpm.c
  6408. --- linux-5.6-rc7/drivers/usb/typec/tcpm/tcpm.c 2020-03-22 18:31:56.000000000 -0700
  6409. +++ linux-pinebook-pro_v5.6/drivers/usb/typec/tcpm/tcpm.c 2020-03-23 07:26:36.000000000 -0700
  6410. @@ -8,6 +8,7 @@
  6411. #include <linux/completion.h>
  6412. #include <linux/debugfs.h>
  6413. #include <linux/device.h>
  6414. +#include <linux/extcon-provider.h>
  6415. #include <linux/jiffies.h>
  6416. #include <linux/kernel.h>
  6417. #include <linux/module.h>
  6418. @@ -322,6 +323,12 @@
  6419. /* port belongs to a self powered device */
  6420. bool self_powered;
  6421.  
  6422. +
  6423. +#ifdef CONFIG_EXTCON
  6424. + struct extcon_dev *extcon;
  6425. + unsigned int *extcon_cables;
  6426. +#endif
  6427. +
  6428. #ifdef CONFIG_DEBUG_FS
  6429. struct dentry *dentry;
  6430. struct mutex logbuffer_lock; /* log buffer access lock */
  6431. @@ -599,6 +606,35 @@
  6432.  
  6433. #endif
  6434.  
  6435. +static void tcpm_update_extcon_data(struct tcpm_port *port, bool attached) {
  6436. +#ifdef CONFIG_EXTCON
  6437. + unsigned int *capability = port->extcon_cables;
  6438. + if (port->data_role == TYPEC_HOST) {
  6439. + extcon_set_state(port->extcon, EXTCON_USB, false);
  6440. + extcon_set_state(port->extcon, EXTCON_USB_HOST, attached);
  6441. + } else {
  6442. + extcon_set_state(port->extcon, EXTCON_USB, true);
  6443. + extcon_set_state(port->extcon, EXTCON_USB_HOST, attached);
  6444. + }
  6445. + while (*capability != EXTCON_NONE) {
  6446. + if (attached) {
  6447. + union extcon_property_value val;
  6448. + val.intval = (port->polarity == TYPEC_POLARITY_CC2);
  6449. + extcon_set_property(port->extcon, *capability,
  6450. + EXTCON_PROP_USB_TYPEC_POLARITY, val);
  6451. + } else {
  6452. + extcon_set_state(port->extcon, *capability, false);
  6453. + }
  6454. + extcon_sync(port->extcon, *capability);
  6455. + capability++;
  6456. + }
  6457. + tcpm_log(port, "Extcon update (%s): %s, %s",
  6458. + attached ? "attached" : "detached",
  6459. + port->data_role == TYPEC_HOST ? "host" : "device",
  6460. + port->polarity == TYPEC_POLARITY_CC1 ? "normal" : "flipped");
  6461. +#endif
  6462. +}
  6463. +
  6464. static int tcpm_pd_transmit(struct tcpm_port *port,
  6465. enum tcpm_transmit_type type,
  6466. const struct pd_message *msg)
  6467. @@ -788,10 +824,11 @@
  6468. else
  6469. orientation = TYPEC_ORIENTATION_REVERSE;
  6470.  
  6471. - if (data == TYPEC_HOST)
  6472. + if (data == TYPEC_HOST) {
  6473. usb_role = USB_ROLE_HOST;
  6474. - else
  6475. + } else {
  6476. usb_role = USB_ROLE_DEVICE;
  6477. + }
  6478.  
  6479. ret = tcpm_mux_set(port, TYPEC_STATE_USB, usb_role, orientation);
  6480. if (ret < 0)
  6481. @@ -806,6 +843,8 @@
  6482. typec_set_data_role(port->typec_port, data);
  6483. typec_set_pwr_role(port->typec_port, role);
  6484.  
  6485. + tcpm_update_extcon_data(port, attached);
  6486. +
  6487. return 0;
  6488. }
  6489.  
  6490. @@ -1016,7 +1055,7 @@
  6491. paltmode->mode = i;
  6492. paltmode->vdo = le32_to_cpu(payload[i]);
  6493.  
  6494. - tcpm_log(port, " Alternate mode %d: SVID 0x%04x, VDO %d: 0x%08x",
  6495. + tcpm_log(port, "Alternate mode %d: SVID 0x%04x, VDO %d: 0x%08x",
  6496. pmdata->altmodes, paltmode->svid,
  6497. paltmode->mode, paltmode->vdo);
  6498.  
  6499. @@ -1036,6 +1075,9 @@
  6500. if (!altmode)
  6501. tcpm_log(port, "Failed to register partner SVID 0x%04x",
  6502. modep->altmode_desc[i].svid);
  6503. + else
  6504. + tcpm_log(port, "Registered altmode 0x%04x", modep->altmode_desc[i].svid);
  6505. +
  6506. port->partner_altmode[i] = altmode;
  6507. }
  6508. }
  6509. @@ -1139,9 +1181,11 @@
  6510. modep->svid_index++;
  6511. if (modep->svid_index < modep->nsvids) {
  6512. u16 svid = modep->svids[modep->svid_index];
  6513. + tcpm_log(port, "More modes available, sending discover");
  6514. response[0] = VDO(svid, 1, CMD_DISCOVER_MODES);
  6515. rlen = 1;
  6516. } else {
  6517. + tcpm_log(port, "Got all patner modes, registering");
  6518. tcpm_register_partner_altmodes(port);
  6519. }
  6520. break;
  6521. @@ -2664,6 +2708,7 @@
  6522. static void tcpm_typec_disconnect(struct tcpm_port *port)
  6523. {
  6524. if (port->connected) {
  6525. + tcpm_update_extcon_data(port, false);
  6526. typec_unregister_partner(port->partner);
  6527. port->partner = NULL;
  6528. port->connected = false;
  6529. @@ -2721,6 +2766,8 @@
  6530. port->hard_reset_count = 0;
  6531.  
  6532. tcpm_reset_port(port);
  6533. +
  6534. + tcpm_update_extcon_data(port, false);
  6535. }
  6536.  
  6537. static void tcpm_src_detach(struct tcpm_port *port)
  6538. @@ -4363,6 +4410,64 @@
  6539. }
  6540. EXPORT_SYMBOL_GPL(tcpm_tcpc_reset);
  6541.  
  6542. +unsigned int default_supported_cables[] = {
  6543. + EXTCON_NONE
  6544. +};
  6545. +
  6546. +static int tcpm_fw_get_caps_late(struct tcpm_port *port,
  6547. + struct fwnode_handle *fwnode)
  6548. +{
  6549. + int ret, i;
  6550. + ret = fwnode_property_count_u32(fwnode, "typec-altmodes");
  6551. + if (ret > 0) {
  6552. + u32 *props;
  6553. + if (ret % 4) {
  6554. + dev_err(port->dev, "Length of typec altmode array must be divisible by 4");
  6555. + return -EINVAL;
  6556. + }
  6557. +
  6558. + props = devm_kzalloc(port->dev, sizeof(u32) * ret, GFP_KERNEL);
  6559. + if (!props) {
  6560. + dev_err(port->dev, "Failed to allocate memory for altmode properties");
  6561. + return -ENOMEM;
  6562. + }
  6563. +
  6564. + if(fwnode_property_read_u32_array(fwnode, "typec-altmodes", props, ret) < 0) {
  6565. + dev_err(port->dev, "Failed to read altmodes from port");
  6566. + return -EINVAL;
  6567. + }
  6568. +
  6569. + i = 0;
  6570. + while (ret > 0 && i < ARRAY_SIZE(port->port_altmode)) {
  6571. + struct typec_altmode *alt;
  6572. + struct typec_altmode_desc alt_desc = {
  6573. + .svid = props[i * 4],
  6574. + .mode = props[i * 4 + 1],
  6575. + .vdo = props[i * 4 + 2],
  6576. + .roles = props[i * 4 + 3],
  6577. + };
  6578. +
  6579. +
  6580. + tcpm_log(port, "Adding altmode SVID: 0x%04x, mode: %d, vdo: %u, role: %d",
  6581. + alt_desc.svid, alt_desc.mode, alt_desc.vdo, alt_desc.roles);
  6582. + alt = typec_port_register_altmode(port->typec_port,
  6583. + &alt_desc);
  6584. + if (IS_ERR(alt)) {
  6585. + tcpm_log(port,
  6586. + "%s: failed to register port alternate mode 0x%x",
  6587. + dev_name(port->dev), alt_desc.svid);
  6588. + break;
  6589. + }
  6590. + typec_altmode_set_drvdata(alt, port);
  6591. + alt->ops = &tcpm_altmode_ops;
  6592. + port->port_altmode[i] = alt;
  6593. + i++;
  6594. + ret -= 4;
  6595. + }
  6596. + }
  6597. + return 0;
  6598. +}
  6599. +
  6600. static int tcpm_fw_get_caps(struct tcpm_port *port,
  6601. struct fwnode_handle *fwnode)
  6602. {
  6603. @@ -4373,6 +4478,23 @@
  6604. if (!fwnode)
  6605. return -EINVAL;
  6606.  
  6607. +#ifdef CONFIG_EXTCON
  6608. + ret = fwnode_property_count_u32(fwnode, "extcon-cables");
  6609. + if (ret > 0) {
  6610. + port->extcon_cables = devm_kzalloc(port->dev, sizeof(u32) * ret, GFP_KERNEL);
  6611. + if (!port->extcon_cables) {
  6612. + dev_err(port->dev, "Failed to allocate memory for extcon cable types. "\
  6613. + "Using default tyes");
  6614. + goto extcon_default;
  6615. + }
  6616. + fwnode_property_read_u32_array(fwnode, "extcon-cables", port->extcon_cables, ret);
  6617. + } else {
  6618. +extcon_default:
  6619. + dev_info(port->dev, "No cable types defined, using default cables");
  6620. + port->extcon_cables = default_supported_cables;
  6621. + }
  6622. +#endif
  6623. +
  6624. /* USB data support is optional */
  6625. ret = fwnode_property_read_string(fwnode, "data-role", &cap_str);
  6626. if (ret == 0) {
  6627. @@ -4705,6 +4827,17 @@
  6628. goto out_destroy_wq;
  6629.  
  6630. port->try_role = port->typec_caps.prefer_role;
  6631. +#ifdef CONFIG_EXTCON
  6632. + port->extcon = devm_extcon_dev_allocate(dev, port->extcon_cables);
  6633. + if (IS_ERR(port->extcon)) {
  6634. + dev_err(dev, "Failed to allocate extcon device: %ld", PTR_ERR(port->extcon));
  6635. + goto out_destroy_wq;
  6636. + }
  6637. + if((err = devm_extcon_dev_register(dev, port->extcon))) {
  6638. + dev_err(dev, "Failed to register extcon device: %d", err);
  6639. + goto out_destroy_wq;
  6640. + }
  6641. +#endif
  6642.  
  6643. port->typec_caps.fwnode = tcpc->fwnode;
  6644. port->typec_caps.revision = 0x0120; /* Type-C spec release 1.2 */
  6645. @@ -4731,6 +4864,12 @@
  6646. goto out_role_sw_put;
  6647. }
  6648.  
  6649. + err = tcpm_fw_get_caps_late(port, tcpc->fwnode);
  6650. + if (err < 0) {
  6651. + dev_err(dev, "Failed to get altmodes from fwnode");
  6652. + goto out_destroy_wq;
  6653. + }
  6654. +
  6655. mutex_lock(&port->lock);
  6656. tcpm_init(port);
  6657. mutex_unlock(&port->lock);
  6658. diff -uNr '--exclude=.git' linux-5.6-rc7/include/dt-bindings/suspend/rockchip-rk3399.h linux-pinebook-pro_v5.6/include/dt-bindings/suspend/rockchip-rk3399.h
  6659. --- linux-5.6-rc7/include/dt-bindings/suspend/rockchip-rk3399.h 1969-12-31 16:00:00.000000000 -0800
  6660. +++ linux-pinebook-pro_v5.6/include/dt-bindings/suspend/rockchip-rk3399.h 2020-03-23 07:26:37.000000000 -0700
  6661. @@ -0,0 +1,60 @@
  6662. +/*
  6663. + * Header providing constants for Rockchip suspend bindings.
  6664. + *
  6665. + * Copyright (C) 2017, Fuzhou Rockchip Electronics Co., Ltd
  6666. + * Author: Tony.Xie
  6667. + *
  6668. + * This program is free software; you can redistribute it and/or modify
  6669. + * it under the terms of the GNU General Public License as published by
  6670. + * the Free Software Foundation; either version 2 of the License, or
  6671. + * (at your option) any later version.
  6672. + *
  6673. + * This program is distributed in the hope that it will be useful,
  6674. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  6675. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  6676. + * GNU General Public License for more details.
  6677. + */
  6678. +
  6679. +#ifndef __DT_BINDINGS_SUSPEND_ROCKCHIP_RK3399_H__
  6680. +#define __DT_BINDINGS_SUSPEND_ROCKCHIP_RK3399_H__
  6681. +
  6682. +/* the suspend mode */
  6683. +#define RKPM_SLP_WFI (1 << 0)
  6684. +#define RKPM_SLP_ARMPD (1 << 1)
  6685. +#define RKPM_SLP_PERILPPD (1 << 2)
  6686. +#define RKPM_SLP_DDR_RET (1 << 3)
  6687. +#define RKPM_SLP_PLLPD (1 << 4)
  6688. +#define RKPM_SLP_OSC_DIS (1 << 5)
  6689. +#define RKPM_SLP_CENTER_PD (1 << 6)
  6690. +#define RKPM_SLP_AP_PWROFF (1 << 7)
  6691. +
  6692. +/* the wake up source */
  6693. +#define RKPM_CLUSTER_L_WKUP_EN (1 << 0)
  6694. +#define RKPM_CLUSTER_B_WKUPB_EN (1 << 1)
  6695. +#define RKPM_GPIO_WKUP_EN (1 << 2)
  6696. +#define RKPM_SDIO_WKUP_EN (1 << 3)
  6697. +#define RKPM_SDMMC_WKUP_EN (1 << 4)
  6698. +#define RKPM_TIMER_WKUP_EN (1 << 6)
  6699. +#define RKPM_USB_WKUP_EN (1 << 7)
  6700. +#define RKPM_SFT_WKUP_EN (1 << 8)
  6701. +#define RKPM_WDT_M0_WKUP_EN (1 << 9)
  6702. +#define RKPM_TIME_OUT_WKUP_EN (1 << 10)
  6703. +#define RKPM_PWM_WKUP_EN (1 << 11)
  6704. +#define RKPM_PCIE_WKUP_EN (1 << 13)
  6705. +
  6706. +/* the pwm regulator */
  6707. +#define PWM0_REGULATOR_EN (1 << 0)
  6708. +#define PWM1_REGULATOR_EN (1 << 1)
  6709. +#define PWM2_REGULATOR_EN (1 << 2)
  6710. +#define PWM3A_REGULATOR_EN (1 << 3)
  6711. +#define PWM3B_REGULATOR_EN (1 << 4)
  6712. +
  6713. +/* the APIO voltage domain */
  6714. +#define RKPM_APIO0_SUSPEND (1 << 0)
  6715. +#define RKPM_APIO1_SUSPEND (1 << 1)
  6716. +#define RKPM_APIO2_SUSPEND (1 << 2)
  6717. +#define RKPM_APIO3_SUSPEND (1 << 3)
  6718. +#define RKPM_APIO4_SUSPEND (1 << 4)
  6719. +#define RKPM_APIO5_SUSPEND (1 << 5)
  6720. +
  6721. +#endif
  6722. diff -uNr '--exclude=.git' linux-5.6-rc7/include/linux/leds.h linux-pinebook-pro_v5.6/include/linux/leds.h
  6723. --- linux-5.6-rc7/include/linux/leds.h 2020-03-22 18:31:56.000000000 -0700
  6724. +++ linux-pinebook-pro_v5.6/include/linux/leds.h 2020-03-23 07:26:37.000000000 -0700
  6725. @@ -74,6 +74,7 @@
  6726. #define LED_BRIGHT_HW_CHANGED BIT(21)
  6727. #define LED_RETAIN_AT_SHUTDOWN BIT(22)
  6728. #define LED_INIT_DEFAULT_TRIGGER BIT(23)
  6729. +#define LED_INVERT_TRIGGER BIT(24)
  6730.  
  6731. /* set_brightness_work / blink_timer flags, atomic, private. */
  6732. unsigned long work_flags;
  6733. diff -uNr '--exclude=.git' linux-5.6-rc7/include/linux/mfd/rk808.h linux-pinebook-pro_v5.6/include/linux/mfd/rk808.h
  6734. --- linux-5.6-rc7/include/linux/mfd/rk808.h 2020-03-22 18:31:56.000000000 -0700
  6735. +++ linux-pinebook-pro_v5.6/include/linux/mfd/rk808.h 2020-03-23 07:26:37.000000000 -0700
  6736. @@ -622,5 +622,6 @@
  6737. const struct regmap_irq_chip *regmap_irq_chip;
  6738. void (*pm_pwroff_fn)(void);
  6739. void (*pm_pwroff_prep_fn)(void);
  6740. + bool use_syscore_powerdown;
  6741. };
  6742. #endif /* __LINUX_REGULATOR_RK808_H */
  6743. diff -uNr '--exclude=.git' linux-5.6-rc7/include/linux/regulator/driver.h linux-pinebook-pro_v5.6/include/linux/regulator/driver.h
  6744. --- linux-5.6-rc7/include/linux/regulator/driver.h 2020-03-22 18:31:56.000000000 -0700
  6745. +++ linux-pinebook-pro_v5.6/include/linux/regulator/driver.h 2020-03-23 07:26:37.000000000 -0700
  6746. @@ -482,6 +482,9 @@
  6747.  
  6748. /* time when this regulator was disabled last time */
  6749. unsigned long last_off_jiffy;
  6750. +
  6751. + /* state when resuming */
  6752. + int resume_state;
  6753. };
  6754.  
  6755. struct regulator_dev *
  6756. diff -uNr '--exclude=.git' linux-5.6-rc7/include/linux/rockchip/rockchip_sip.h linux-pinebook-pro_v5.6/include/linux/rockchip/rockchip_sip.h
  6757. --- linux-5.6-rc7/include/linux/rockchip/rockchip_sip.h 1969-12-31 16:00:00.000000000 -0800
  6758. +++ linux-pinebook-pro_v5.6/include/linux/rockchip/rockchip_sip.h 2020-03-23 07:26:37.000000000 -0700
  6759. @@ -0,0 +1,149 @@
  6760. +/* Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
  6761. + *
  6762. + * This program is free software; you can redistribute it and/or modify
  6763. + * it under the terms of the GNU General Public License version 2 and
  6764. + * only version 2 as published by the Free Software Foundation.
  6765. + *
  6766. + * This program is distributed in the hope that it will be useful,
  6767. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  6768. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  6769. + * GNU General Public License for more details.
  6770. + */
  6771. +#ifndef __ROCKCHIP_SIP_H
  6772. +#define __ROCKCHIP_SIP_H
  6773. +
  6774. +#include <linux/arm-smccc.h>
  6775. +#include <linux/io.h>
  6776. +
  6777. +/* SMC function IDs for SiP Service queries, compatible with kernel-3.10 */
  6778. +#define SIP_ATF_VERSION 0x82000001
  6779. +#define SIP_ACCESS_REG 0x82000002
  6780. +#define SIP_SUSPEND_MODE 0x82000003
  6781. +#define SIP_PENDING_CPUS 0x82000004
  6782. +#define SIP_UARTDBG_CFG 0x82000005
  6783. +#define SIP_UARTDBG_CFG64 0xc2000005
  6784. +#define SIP_MCU_EL3FIQ_CFG 0x82000006
  6785. +#define SIP_ACCESS_CHIP_STATE64 0xc2000006
  6786. +#define SIP_SECURE_MEM_CONFIG 0x82000007
  6787. +#define SIP_ACCESS_CHIP_EXTRA_STATE64 0xc2000007
  6788. +#define SIP_DDR_CFG 0x82000008
  6789. +#define SIP_SHARE_MEM 0x82000009
  6790. +#define SIP_SIP_VERSION 0x8200000a
  6791. +#define SIP_REMOTECTL_CFG 0x8200000b
  6792. +
  6793. +/* Trust firmware version */
  6794. +#define ATF_VER_MAJOR(ver) (((ver) >> 16) & 0xffff)
  6795. +#define ATF_VER_MINOR(ver) (((ver) >> 0) & 0xffff)
  6796. +
  6797. +/* SIP_ACCESS_REG: read or write */
  6798. +#define SECURE_REG_RD 0x0
  6799. +#define SECURE_REG_WR 0x1
  6800. +
  6801. +/* Fiq debugger share memory: 8KB enough */
  6802. +#define FIQ_UARTDBG_PAGE_NUMS 2
  6803. +#define FIQ_UARTDBG_SHARE_MEM_SIZE ((FIQ_UARTDBG_PAGE_NUMS) * 4096)
  6804. +
  6805. +/* Error return code */
  6806. +#define IS_SIP_ERROR(x) (!!(x))
  6807. +
  6808. +#define SIP_RET_SUCCESS 0
  6809. +#define SIP_RET_SMC_UNKNOWN -1
  6810. +#define SIP_RET_NOT_SUPPORTED -2
  6811. +#define SIP_RET_INVALID_PARAMS -3
  6812. +#define SIP_RET_INVALID_ADDRESS -4
  6813. +#define SIP_RET_DENIED -5
  6814. +
  6815. +/* SIP_UARTDBG_CFG64 call types */
  6816. +#define UARTDBG_CFG_INIT 0xf0
  6817. +#define UARTDBG_CFG_OSHDL_TO_OS 0xf1
  6818. +#define UARTDBG_CFG_OSHDL_CPUSW 0xf3
  6819. +#define UARTDBG_CFG_OSHDL_DEBUG_ENABLE 0xf4
  6820. +#define UARTDBG_CFG_OSHDL_DEBUG_DISABLE 0xf5
  6821. +#define UARTDBG_CFG_PRINT_PORT 0xf7
  6822. +#define UARTDBG_CFG_FIQ_ENABEL 0xf8
  6823. +#define UARTDBG_CFG_FIQ_DISABEL 0xf9
  6824. +
  6825. +/* SIP_SUSPEND_MODE32 call types */
  6826. +#define SUSPEND_MODE_CONFIG 0x01
  6827. +#define WKUP_SOURCE_CONFIG 0x02
  6828. +#define PWM_REGULATOR_CONFIG 0x03
  6829. +#define GPIO_POWER_CONFIG 0x04
  6830. +#define SUSPEND_DEBUG_ENABLE 0x05
  6831. +#define APIOS_SUSPEND_CONFIG 0x06
  6832. +#define VIRTUAL_POWEROFF 0x07
  6833. +
  6834. +/* SIP_REMOTECTL_CFG call types */
  6835. +#define REMOTECTL_SET_IRQ 0xf0
  6836. +#define REMOTECTL_SET_PWM_CH 0xf1
  6837. +#define REMOTECTL_SET_PWRKEY 0xf2
  6838. +#define REMOTECTL_GET_WAKEUP_STATE 0xf3
  6839. +#define REMOTECTL_ENABLE 0xf4
  6840. +/* wakeup state */
  6841. +#define REMOTECTL_PWRKEY_WAKEUP 0xdeadbeaf
  6842. +
  6843. +/* Share mem page types */
  6844. +typedef enum {
  6845. + SHARE_PAGE_TYPE_INVALID = 0,
  6846. + SHARE_PAGE_TYPE_UARTDBG,
  6847. + SHARE_PAGE_TYPE_MAX,
  6848. +} share_page_type_t;
  6849. +
  6850. +/*
  6851. + * Rules: struct arm_smccc_res contains result and data, details:
  6852. + *
  6853. + * a0: error code(0: success, !0: error);
  6854. + * a1~a3: data
  6855. + */
  6856. +struct arm_smccc_res sip_smc_get_atf_version(void);
  6857. +struct arm_smccc_res sip_smc_get_sip_version(void);
  6858. +struct arm_smccc_res sip_smc_ddr_cfg(u32 arg0, u32 arg1, u32 arg2);
  6859. +struct arm_smccc_res sip_smc_request_share_mem(u32 page_num,
  6860. + share_page_type_t page_type);
  6861. +struct arm_smccc_res sip_smc_mcu_el3fiq(u32 arg0, u32 arg1, u32 arg2);
  6862. +
  6863. +int sip_smc_set_suspend_mode(u32 ctrl, u32 config1, u32 config2);
  6864. +int sip_smc_virtual_poweroff(void);
  6865. +/***************************fiq debugger **************************************/
  6866. +void sip_fiq_debugger_enable_fiq(bool enable, uint32_t tgt_cpu);
  6867. +void sip_fiq_debugger_enable_debug(bool enable);
  6868. +int sip_fiq_debugger_uart_irq_tf_init(u32 irq_id, void *callback_fn);
  6869. +int sip_fiq_debugger_set_print_port(u32 port_phyaddr, u32 baudrate);
  6870. +int sip_fiq_debugger_request_share_memory(void);
  6871. +int sip_fiq_debugger_get_target_cpu(void);
  6872. +int sip_fiq_debugger_switch_cpu(u32 cpu);
  6873. +int sip_fiq_debugger_is_enabled(void);
  6874. +
  6875. +/* optee cpu_context */
  6876. +struct sm_nsec_ctx {
  6877. + u32 usr_sp;
  6878. + u32 usr_lr;
  6879. + u32 irq_spsr;
  6880. + u32 irq_sp;
  6881. + u32 irq_lr;
  6882. + u32 svc_spsr;
  6883. + u32 svc_sp;
  6884. + u32 svc_lr;
  6885. + u32 abt_spsr;
  6886. + u32 abt_sp;
  6887. + u32 abt_lr;
  6888. + u32 und_spsr;
  6889. + u32 und_sp;
  6890. + u32 und_lr;
  6891. + u32 mon_lr;
  6892. + u32 mon_spsr;
  6893. + u32 r4;
  6894. + u32 r5;
  6895. + u32 r6;
  6896. + u32 r7;
  6897. + u32 r8;
  6898. + u32 r9;
  6899. + u32 r10;
  6900. + u32 r11;
  6901. + u32 r12;
  6902. + u32 r0;
  6903. + u32 r1;
  6904. + u32 r2;
  6905. + u32 r3;
  6906. +};
  6907. +
  6908. +#endif
  6909. diff -uNr '--exclude=.git' linux-5.6-rc7/include/linux/serdev.h linux-pinebook-pro_v5.6/include/linux/serdev.h
  6910. --- linux-5.6-rc7/include/linux/serdev.h 2020-03-22 18:31:56.000000000 -0700
  6911. +++ linux-pinebook-pro_v5.6/include/linux/serdev.h 2020-03-23 07:26:37.000000000 -0700
  6912. @@ -63,6 +63,7 @@
  6913. struct device_driver driver;
  6914. int (*probe)(struct serdev_device *);
  6915. void (*remove)(struct serdev_device *);
  6916. + void (*shutdown)(struct serdev_device *);
  6917. };
  6918.  
  6919. static inline struct serdev_device_driver *to_serdev_device_driver(struct device_driver *d)
  6920. diff -uNr '--exclude=.git' linux-5.6-rc7/MAINTAINERS linux-pinebook-pro_v5.6/MAINTAINERS
  6921. --- linux-5.6-rc7/MAINTAINERS 2020-03-22 18:31:56.000000000 -0700
  6922. +++ linux-pinebook-pro_v5.6/MAINTAINERS 2020-03-23 07:26:32.000000000 -0700
  6923. @@ -3885,6 +3885,12 @@
  6924. F: arch/powerpc/oprofile/*cell*
  6925. F: arch/powerpc/platforms/cell/
  6926.  
  6927. +CELLWISE CW2015 BATTERY DRIVER
  6928. +M: Tobias Schrammm <t.schramm@manjaro.org>
  6929. +S: Maintained
  6930. +F: Documentation/devicetree/bindings/power/supply/cw2015_battery.yaml
  6931. +F: drivers/power/supply/cw2015_battery.c
  6932. +
  6933. CEPH COMMON CODE (LIBCEPH)
  6934. M: Ilya Dryomov <idryomov@gmail.com>
  6935. M: Jeff Layton <jlayton@kernel.org>
  6936. diff -uNr '--exclude=.git' linux-5.6-rc7/net/rfkill/rfkill-gpio.c linux-pinebook-pro_v5.6/net/rfkill/rfkill-gpio.c
  6937. --- linux-5.6-rc7/net/rfkill/rfkill-gpio.c 2020-03-22 18:31:56.000000000 -0700
  6938. +++ linux-pinebook-pro_v5.6/net/rfkill/rfkill-gpio.c 2020-03-23 07:26:37.000000000 -0700
  6939. @@ -148,6 +148,14 @@
  6940. return 0;
  6941. }
  6942.  
  6943. +#ifdef CONFIG_OF
  6944. +static const struct of_device_id rfkill_of_match[] = {
  6945. + { .compatible = "rfkill,gpio", },
  6946. + { },
  6947. +};
  6948. +MODULE_DEVICE_TABLE(of, rfkill_of_match);
  6949. +#endif
  6950. +
  6951. #ifdef CONFIG_ACPI
  6952. static const struct acpi_device_id rfkill_acpi_match[] = {
  6953. { "BCM4752", RFKILL_TYPE_GPS },
  6954. @@ -162,6 +170,9 @@
  6955. .remove = rfkill_gpio_remove,
  6956. .driver = {
  6957. .name = "rfkill_gpio",
  6958. +#ifdef CONFIG_OF
  6959. + .of_match_table = rfkill_of_match,
  6960. +#endif
  6961. .acpi_match_table = ACPI_PTR(rfkill_acpi_match),
  6962. },
  6963. };
  6964. diff -uNr '--exclude=.git' linux-5.6-rc7/sound/soc/codecs/es8316.c linux-pinebook-pro_v5.6/sound/soc/codecs/es8316.c
  6965. --- linux-5.6-rc7/sound/soc/codecs/es8316.c 2020-03-22 18:31:56.000000000 -0700
  6966. +++ linux-pinebook-pro_v5.6/sound/soc/codecs/es8316.c 2020-03-23 07:26:38.000000000 -0700
  6967. @@ -687,7 +687,7 @@
  6968. snd_soc_component_update_bits(component, ES8316_GPIO_DEBOUNCE,
  6969. ES8316_GPIO_ENABLE_INTERRUPT, 0);
  6970.  
  6971. - if (es8316->jack->status & SND_JACK_MICROPHONE) {
  6972. + if (es8316->jack && (es8316->jack->status & SND_JACK_MICROPHONE)) {
  6973. es8316_disable_micbias_for_mic_gnd_short_detect(component);
  6974. snd_soc_jack_report(es8316->jack, 0, SND_JACK_BTN_0);
  6975. }
  6976. diff -uNr '--exclude=.git' linux-5.6-rc7/sound/soc/soc-jack.c linux-pinebook-pro_v5.6/sound/soc/soc-jack.c
  6977. --- linux-5.6-rc7/sound/soc/soc-jack.c 2020-03-22 18:31:56.000000000 -0700
  6978. +++ linux-pinebook-pro_v5.6/sound/soc/soc-jack.c 2020-03-23 07:26:38.000000000 -0700
  6979. @@ -254,8 +254,6 @@
  6980. int report;
  6981.  
  6982. enable = gpiod_get_value_cansleep(gpio->desc);
  6983. - if (gpio->invert)
  6984. - enable = !enable;
  6985.  
  6986. if (enable)
  6987. report = gpio->report;
  6988. @@ -384,6 +382,9 @@
  6989. goto undo;
  6990. }
  6991. } else {
  6992. + int flags = GPIOF_IN;
  6993. + if (gpios[i].invert)
  6994. + flags |= GPIOF_ACTIVE_LOW;
  6995. /* legacy GPIO number */
  6996. if (!gpio_is_valid(gpios[i].gpio)) {
  6997. dev_err(jack->card->dev,
  6998. @@ -393,7 +394,7 @@
  6999. goto undo;
  7000. }
  7001.  
  7002. - ret = gpio_request_one(gpios[i].gpio, GPIOF_IN,
  7003. + ret = gpio_request_one(gpios[i].gpio, flags,
  7004. gpios[i].name);
  7005. if (ret)
  7006. goto undo;
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