module zad2(
    input CLOCK_50,
    input [0:0] KEY,
    output [0:6] HEX0, HEX1, HEX2,
    output [0:0] LEDR);

    wire unitsToDozens, dozensToHundreds, terminator;
    wire clockTakt;
    wire [3:0] unitsHex, dozensHex, hundredsHex;

    assign enable = ~((unitsHex==4'b1001)&(dozensHex==4'b1001)&(hundredsHex==4'b1001));

    counter_to_make_delay delay(CLOCK_50, KEY[0], clockTakt);

    counter_modulo_10 units(clockTakt,KEY[0],enable,unitsHex, unitsToDozens);
    counter_modulo_10 dozens(unitsToDozens,KEY[0],1,dozensHex, dozensToHundreds);
    counter_modulo_10 hundreds(dozensToHundreds,KEY[0],1,hundredsHex, terminator);

    decoder_hex_10 ex1(unitsHex, HEX0);
    decoder_hex_10 ex2(dozensHex, HEX1);
    decoder_hex_10 ex3(hundredsHex, HEX3);

endmodule

module counter_to_make_delay(
    input clk, aclr,
    output reg clockTact);

    reg [25:0] i;

    always@(posedge clk, negedge aclr)
        if(!aclr)
            begin
                i<=0;
                clockTact<=0;
            end
        else
            begin
                if(i==3)
                    begin
                        i<=0;
                        clockTact<=1;
                    end
                else
                    begin
                        i<=i+1;
                        clockTact<=0;
                    end
            end

endmodule

module counter_modulo_10
    #(parameter k=10)
    (input clk, aclr, enable,
    output reg [N-1:0] Q,
    output reg rollover);

    localparam N=clogb2(k-1);
    function integer clogb2(input [31:0] v);
    for(clogb2=0;v>0;clogb2=clogb2+1)
        v=v>>1;
    endfunction

    always@(posedge clk, negedge aclr)
        if(!aclr)
            Q<=0;
        else
            if(enable==1)
                begin
                    if(Q==(k-1))
                        begin
                            rollover<=1;
                            Q<=0;
                        end
                    else
                        begin
                            rollover<=0;
                            Q<=Q+1;
                        end
                end

endmodule

module decoder_hex_10(
    input [3:0] x,
    output reg [0:6] h);

    always@(*)
        case(x)
            4'b0000: h=7'b0000001;
            4'b0001: h=7'b1001111;
            4'b0010: h=7'b0010010;
            4'b0011: h=7'b0000110;
            4'b0100: h=7'b1001100;
            4'b0101: h=7'b0100100;
            4'b0110: h=7'b0100000;
            4'b0111: h=7'b0001111;
            4'b1000: h=7'b0000000;
            4'b1001: h=7'b0000100;

        endcase

endmodule