library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_unsigned.all;

entity BCD_Excess is
	port ( B : in std_logic_vector(3 downto 0);
		    E : out std_logic_vector(3 downto 0) );
end BCD_Excess;

architecture Wspolbiezne of BCD_Excess is
begin

--	E(3) <= not ( (not B(3) and not B(2))
--							or (not B(3) and not B(1) and not B(0)) );
--	E(2) <=  (not B(2) and B(0)) or (not B(2) and B(1))
--							or (B(2) and not B(1) and not B(0));
--   E(1) <= (not B(1) and not B(0)) or (B(1) and B(0) );
--   E(0) <= not B(0);


	--E <= B+3;
process(B)
		begin
--			case B is
--				when "0000" => E <= "0011";
--				when "0001" => E <= "0100";
--				when "0010" => E <= "0101";
--				when "0011" => E <= "0110";
--				when "0100" => E <= "0111";
--				when "0101" => E <= "1000";
--				when "0110" => E <= "1001";
--				when "0111" => E <= "1010";
--				when "1000" => E <= "1011";
--				when "1001" => E <= "1100";
--				when others => E <= "----";
--			end case;

if B < 10 then
	E <= B + 3;
else
   E <= "0000";
end if ;


		end process;
end Wspolbiezne;