`timescale 1ns/1ps

module lab1_test;

    logic F, F_test;
    logic [3:0] inputs;
    logic a,b;
    logic [1:0] sel;

    initial begin
        inputs=0;

        repeat (2**4)
        begin
            #1 $strobe("value: %b F = %b F_test=%b equal:%b | a:%b b:%b sel[0]:%b sel[1]:%b", inputs, F, F_test, (F==F_test), a, b, sel[0], sel[1]);
            #9 inputs = inputs+1;
        end
    end

    assign a = inputs[1];
    assign b = inputs[0];
    assign sel = inputs[3:2];

    lab1 uut_inst(sel, a, b, F);

    always_comb
    begin
        F_test = (sel[1] & ~a & ~b) | (sel[1] & a & b) | (sel[0] & ~a & b) | (~sel[0] & ~b) | (~sel[0] & a);
    end

endmodule