module test(
	input wire d,
	output reg q,
	input wire clk,
	input wire rst
);

	always @(posedge clk or posedge rst)
	begin
		if (rst)
			q <= 1'b0;
		else
			case (d)
				1'b0: q<= 1'b0;
				1'b1: q<= 1'b1;
				default: q <= 1'b0;
			endcase
	end

endmodule