LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
PACKAGE Panican_Fall2019_CSC343_AdderSubtractor IS
  COMPONENT ssd_decoder IS
	 GENERIC (n : INTEGER := 4);
	 PORT
	 (
	 	 is_signed  : IN STD_LOGIC;
	 	 bit_num    : IN STD_LOGIC_VECTOR (n - 1 DOWNTO 0);
	   ssd_out    : OUT STD_LOGIC_VECTOR (55 DOWNTO 0)
	 );
  END COMPONENT;
	COMPONENT one_full_adder IS
		PORT (
			a, b, cin : IN STD_LOGIC;
			sum, carry : OUT STD_LOGIC
		);
	END COMPONENT;
	COMPONENT n_full_adder IS
		GENERIC (n : INTEGER := 2);
		PORT (
			a, b : IN STD_LOGIC_VECTOR (n - 1 DOWNTO 0);
			cin : IN STD_LOGIC;
			s : OUT STD_LOGIC_VECTOR (n - 1 DOWNTO 0);
			cout : OUT STD_LOGIC
		);
	END COMPONENT;
	COMPONENT n_full_subtractor IS
		GENERIC (n : INTEGER := 4);
		PORT (
			a, b : IN std_logic_vector (n - 1 DOWNTO 0);
			cin : IN std_logic;
			sum : OUT std_logic_vector (n - 1 DOWNTO 0);
			cout, negative, overflow, zero, SLT, SLTU : OUT std_logic
		);
	END COMPONENT;
	COMPONENT sign_extend IS
		GENERIC (n : INTEGER := 2);
		PORT (
			a : IN std_logic_vector(n - 1 DOWNTO 0);
			start_switch : IN std_logic;
			a_out : OUT std_logic_vector((n * 2) - 1 DOWNTO 0)
		);
	END COMPONENT;
	COMPONENT add_subtract_immediate IS
		GENERIC (n : INTEGER := 4);
		PORT (
			a : IN std_logic_vector(n - 1 DOWNTO 0);
			b : IN std_logic_vector(n/2 - 1 DOWNTO 0);
			cin : IN std_logic;
			cout, overflow, zero, negative : OUT std_logic;
			result : OUT std_logic_vector(n - 1 DOWNTO 0)
		);
	END COMPONENT;
	COMPONENT four_full_adder IS
		PORT (
			a, b : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
			cin : IN STD_LOGIC;
			s : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
			cout : OUT STD_LOGIC
		);
	END COMPONENT;
	COMPONENT n_bitwise_and IS
		GENERIC (n : INTEGER := 4);
		PORT (
			a, b : IN std_logic_vector(n - 1 DOWNTO 0);
			result : OUT std_logic_vector(n - 1 DOWNTO 0)
		);
	END COMPONENT;
	COMPONENT n_bitwise_nor IS
		GENERIC (n : INTEGER := 4);
		PORT (
			a, b : IN std_logic_vector(n - 1 DOWNTO 0);
			result : OUT std_logic_vector(n - 1 DOWNTO 0)
		);
	END COMPONENT;
	COMPONENT n_bitwise_xor IS
		GENERIC (n : INTEGER := 4);
		PORT (
			a, b : IN std_logic_vector(n - 1 DOWNTO 0);
			result : OUT std_logic_vector(n - 1 DOWNTO 0)
		);
	END COMPONENT;
	COMPONENT n_bitwise_or IS
		GENERIC (n : INTEGER := 4);
		PORT (
			a, b : IN std_logic_vector(n - 1 DOWNTO 0);
			result : OUT std_logic_vector(n - 1 DOWNTO 0)
		);
	END COMPONENT;
	COMPONENT n_bitwise_shift_left IS
		GENERIC (n : INTEGER := 4);
		PORT (
			a : IN std_logic_vector(n - 1 DOWNTO 0);
			result : OUT std_logic_vector(n - 1 DOWNTO 0)
		);
	END COMPONENT;
	COMPONENT n_bitwise_shift_right IS
		GENERIC (n : INTEGER := 4);
		PORT (
			a : IN std_logic_vector(n - 1 DOWNTO 0);
			result : OUT std_logic_vector(n - 1 DOWNTO 0)
		);
	END COMPONENT;
END PACKAGE Panican_Fall2019_CSC343_AdderSubtractor;