LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE STD.textio.ALL;
USE ieee.std_logic_textio.ALL;

ENTITY example_file_io_tb IS

END example_file_io_tb;
ARCHITECTURE behave OF example_file_io_tb IS

  -----------------------------------------------------------------------------
  -- Declare the Component Under Test
  -----------------------------------------------------------------------------
  COMPONENT ripple_carry_adder IS
    GENERIC (
      g_WIDTH : NATURAL);
    PORT (
      i_add_term1 : IN STD_LOGIC_VECTOR(g_WIDTH - 1 DOWNTO 0);
      i_add_term2 : IN STD_LOGIC_VECTOR(g_WIDTH - 1 DOWNTO 0);
      o_result : OUT STD_LOGIC_VECTOR(g_WIDTH DOWNTO 0)
    );
  END COMPONENT;

  -----------------------------------------------------------------------------
  -- Testbench Internal Signals
  -----------------------------------------------------------------------------
  FILE file_VECTORS : text;
  FILE file_RESULTS : text;
  CONSTANT c_width : NATURAL := 4;
  SIGNAL r_ADD_TERM1 : STD_LOGIC_VECTOR(c_width - 1 DOWNTO 0) := (OTHERS => '0');
  SIGNAL r_ADD_TERM2 : STD_LOGIC_VECTOR(c_width - 1 DOWNTO 0) := (OTHERS => '0');
  SIGNAL w_SUM : STD_LOGIC_VECTOR(c_width DOWNTO 0);

BEGIN

  -----------------------------------------------------------------------------
  -- Instantiate and Map UUT
  -----------------------------------------------------------------------------
  MODULE_RIPPLE_CARRY_ADDER_INST : ripple_carry_adder
  GENERIC MAP(
    g_WIDTH => c_WIDTH)
  PORT MAP(
    i_add_term1 => r_ADD_TERM1,
    i_add_term2 => r_ADD_TERM2,
    o_result => w_SUM
  );

  PROCESS
    VARIABLE v_ILINE : line;
    VARIABLE v_OLINE : line;
    VARIABLE v_ADD_TERM1 : STD_LOGIC_VECTOR(c_WIDTH - 1 DOWNTO 0);
    VARIABLE v_ADD_TERM2 : STD_LOGIC_VECTOR(c_WIDTH - 1 DOWNTO 0);
    VARIABLE v_SPACE : CHARACTER;

  BEGIN
    file_open(file_VECTORS, "D:\UNI\ITCE211\Codes\textio2\input_vectors.txt", read_mode);
    file_open(file_RESULTS, "D:\UNI\ITCE211\Codes\textio2\output_results.txt", write_mode);

    WHILE NOT endfile(file_VECTORS) LOOP
      readline(file_VECTORS, v_ILINE);
      read(v_ILINE, v_ADD_TERM1);
      read(v_ILINE, v_SPACE); -- read in the space character
      read(v_ILINE, v_ADD_TERM2);

      -- Pass the variable to a signal to allow the ripple-carry to use it
      r_ADD_TERM1 <= v_ADD_TERM1;
      r_ADD_TERM2 <= v_ADD_TERM2;

      WAIT FOR 60 ns;

      write(v_OLINE, w_SUM, right, c_WIDTH);
      writeline(file_RESULTS, v_OLINE);
    END LOOP;

    file_close(file_VECTORS);
    file_close(file_RESULTS);

    WAIT;
  END PROCESS;

END behave;