SDRAM connection

`ifdef HAVE_SDRAM
sdrc_top #(.SDR_DW(16), .SDR_BW(2)) sdr_ctrl
(
	.cfg_sdr_width	( 2'b01 ),
	.cfg_colbits	( 2'b00 ),

// WB bus
	.wb_rst_i		( wb_rst ),
	.wb_clk_i		( wb_clk ),

	.wb_stb_i		( wb_ss_stb_i ),
	.wb_ack_o		( wb_ss_ack_o ),
	.wb_addr_i		( wb_ss_adr_i ),
	.wb_we_i			( wb_ss_we_i  ),
	.wb_dat_i		( wb_ss_dat_i ),
	.wb_sel_i		( wb_ss_sel_i ),
	.wb_dat_o		( wb_ss_dat_o ),
	.wb_cyc_i		( wb_ss_cyc_i ),
	.wb_cti_i      ( ),

/* Interface to SDRAMs */
	.sdram_clk		( sdram_clk ),
	.sdram_resetn	( sdram_resetn ),
	.sdr_cs_n		( DRAM_CS_N ),
	.sdr_cke			( DRAM_CKE ),
	.sdr_ras_n		( DRAM_RAS_N ),
	.sdr_cas_n		( DRAM_CAS_N ),
	.sdr_we_n		( DRAM_WE_N ),
	.sdr_dqm			( {DRAM_UDQM,DRAM_LDQM} ),
	.sdr_ba			( {DRAM_BA_1,DRAM_BA_0} ),
	.sdr_addr		( DRAM_ADDR[11:0] ),
	.sdr_dq			( DRAM_DQ[15:0] ),

	/* Parameters */
	.sdr_init_done       (	sdram_init_done	),
	.cfg_req_depth       ( 2'b11 ),	        //how many req. buffer should hold
	.cfg_sdr_en          ( 1'b1 ),
	.cfg_sdr_mode_reg		( 12'h033 ),
	.cfg_sdr_tras_d      ( 4'h1 ),
	.cfg_sdr_trp_d       ( 4'h1 ),
	.cfg_sdr_trcd_d      ( 4'h1 ),
	.cfg_sdr_cas         ( 3'h3 ),
	.cfg_sdr_trcar_d		( 4'h2 ),
	.cfg_sdr_twr_d       ( 4'h2 ),
	.cfg_sdr_rfsh        ( 12'h002 ),
	.cfg_sdr_rfmax			( 3'h6 )
);
`endif