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SDRAM connection

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Feb 27th, 2012
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  1. `ifdef HAVE_SDRAM
  2. sdrc_top #(.SDR_DW(16), .SDR_BW(2)) sdr_ctrl
  3. (
  4. .cfg_sdr_width ( 2'b01 ),
  5. .cfg_colbits ( 2'b00 ),
  6.  
  7. // WB bus
  8. .wb_rst_i ( wb_rst ),
  9. .wb_clk_i ( wb_clk ),
  10.  
  11. .wb_stb_i ( wb_ss_stb_i ),
  12. .wb_ack_o ( wb_ss_ack_o ),
  13. .wb_addr_i ( wb_ss_adr_i ),
  14. .wb_we_i ( wb_ss_we_i ),
  15. .wb_dat_i ( wb_ss_dat_i ),
  16. .wb_sel_i ( wb_ss_sel_i ),
  17. .wb_dat_o ( wb_ss_dat_o ),
  18. .wb_cyc_i ( wb_ss_cyc_i ),
  19. .wb_cti_i ( ),
  20.  
  21. /* Interface to SDRAMs */
  22. .sdram_clk ( sdram_clk ),
  23. .sdram_resetn ( sdram_resetn ),
  24. .sdr_cs_n ( DRAM_CS_N ),
  25. .sdr_cke ( DRAM_CKE ),
  26. .sdr_ras_n ( DRAM_RAS_N ),
  27. .sdr_cas_n ( DRAM_CAS_N ),
  28. .sdr_we_n ( DRAM_WE_N ),
  29. .sdr_dqm ( {DRAM_UDQM,DRAM_LDQM} ),
  30. .sdr_ba ( {DRAM_BA_1,DRAM_BA_0} ),
  31. .sdr_addr ( DRAM_ADDR[11:0] ),
  32. .sdr_dq ( DRAM_DQ[15:0] ),
  33.  
  34. /* Parameters */
  35. .sdr_init_done ( sdram_init_done ),
  36. .cfg_req_depth ( 2'b11 ), //how many req. buffer should hold
  37. .cfg_sdr_en ( 1'b1 ),
  38. .cfg_sdr_mode_reg ( 12'h033 ),
  39. .cfg_sdr_tras_d ( 4'h1 ),
  40. .cfg_sdr_trp_d ( 4'h1 ),
  41. .cfg_sdr_trcd_d ( 4'h1 ),
  42. .cfg_sdr_cas ( 3'h3 ),
  43. .cfg_sdr_trcar_d ( 4'h2 ),
  44. .cfg_sdr_twr_d ( 4'h2 ),
  45. .cfg_sdr_rfsh ( 12'h002 ),
  46. .cfg_sdr_rfmax ( 3'h6 )
  47. );
  48. `endif
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