library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity KursinisCalc is
        Port(
            --CLOCKAS--
            CLOCK_50 : in STD_LOGIC;
            --LEDAI--
            LEDG : out STD_LOGIC_VECTOR (9 DOWNTO 0);
            --SWITCHAI--
            SW : in STD_LOGIC_VECTOR(9 DOWNTO 0);
            --7SEG DISP--
            HEX0_D : out STD_LOGIC_VECTOR(7 DOWNTO 0) :="01000000";
            HEX1_D : out STD_LOGIC_VECTOR(7 DOWNTO 0) :="01000000";
            HEX2_D : out STD_LOGIC_VECTOR(7 DOWNTO 0) :="01000000";
            HEX3_D : out STD_LOGIC_VECTOR(7 DOWNTO 0) :="01000000"
        );
end entity;

architecture main of KursinisCalc is
  signal NUMHEX: STD_LOGIC_VECTOR (3 DOWNTO 0);
  signal NUMD: STD_LOGIC_VECTOR (7 DOWNTO 0);

  component to_7seg is
    Port ( A : in  STD_LOGIC_VECTOR (3 downto 0);
          seg7 : out  STD_LOGIC_VECTOR (7 downto 0)
             );
end component;

    signal cnt: integer RANGE 0 TO 50000000 :=0;
    signal SK1: integer RANGE 0 TO 10 :=5;
    signal SK2: integer RANGE 0 TO 10 :=5;
    signal REZ: integer RANGE 0 TO 3300 :=0;
    signal dbnc, flag: STD_LOGIC;
    signal REZBIN: STD_LOGIC_VECTOR(15 DOWNTO 0);
    signal HEX: STD_LOGIC_VECTOR(3 DOWNTO 0);

    alias SW1 is SW(9 DOWNTO 6);
    alias SW2 is SW(3 DOWNTO 0);
    alias LEDG2 is LEDG(3 DOWNTO 0);
    alias LEDG1 is LEDG(9 DOWNTO 6);
    alias clk is CLOCK_50;
begin

G1: to_7seg port map (NUMHEX, NUMD);
    process(clk)
        begin
        if (rising_edge(clk)) then
            if(SW1 /= "0000" and SW1 <= "1010") then
                SK1 <= to_integer(unsigned(SW1));
            end if;
            if(SW2 /= "0000" and SW2 <= "1010") then
                SK2 <= to_integer(unsigned(SW2));
            end if;
            LEDG1 <= SW1;
            LEDG2 <= SW2;
            REZ <= 3*SK1*SK1+300*SK2;
            REZBIN <= STD_LOGIC_VECTOR(to_unsigned(REZ,16));
            NUMHEX <= REZBIN(3 DOWNTO 0);
            HEX0_D <= NUMD;
            NUMHEX <= REZBIN(7 DOWNTO 4);
            HEX1_D <= NUMD;
            NUMHEX <= REZBIN(11 DOWNTO 8);
            HEX2_D <= NUMD;
            NUMHEX <= REZBIN(15 DOWNTO 12);
            HEX3_D <= NUMD;
        end if;
    end process;

end main;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity to_7seg is
    Port ( A : in  STD_LOGIC_VECTOR (3 downto 0);
          seg7 : out  STD_LOGIC_VECTOR (6 downto 0)
             );
end to_7seg;

architecture Behavioral of to_7seg is

begin

--'a' corresponds to MSB of seg7 and 'g' corresponds to LSB of seg7.
process (A)
BEGIN
    case A is
        when "0000"=> seg7 <="0000001";  -- '0'
        when "0001"=> seg7 <="1001111";  -- '1'
        when "0010"=> seg7 <="0010010";  -- '2'
        when "0011"=> seg7 <="0000110";  -- '3'
        when "0100"=> seg7 <="1001100";  -- '4'
        when "0101"=> seg7 <="0100100";  -- '5'
        when "0110"=> seg7 <="0100000";  -- '6'
        when "0111"=> seg7 <="0001111";  -- '7'
        when "1000"=> seg7 <="0000000";  -- '8'
        when "1001"=> seg7 <="0000100";  -- '9'
        when "1010"=> seg7 <="0001000";  -- 'A'
        when "1011"=> seg7 <="1100000";  -- 'b'
        when "1100"=> seg7 <="0110001";  -- 'C'
        when "1101"=> seg7 <="1000010";  -- 'd'
        when "1110"=> seg7 <="0110000";  -- 'E'
        when "1111"=> seg7 <="0111000";  -- 'F'
        when others =>  NULL;
    end case;
end process;

end Behavioral;