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  1. /dts-v1/;
  2.  
  3. / {
  4. #address-cells = <0x01>;
  5. #size-cells = <0x01>;
  6. compatible = "cudy,c200p\0mediatek,mt7621-soc";
  7. model = "Cudy C200P";
  8.  
  9. aliases {
  10. serial0 = "/palmbus@1e000000/uartlite@c00";
  11. led-boot = "/leds/internet_blue";
  12. led-failsafe = "/leds/internet_blue";
  13. led-running = "/leds/internet_blue";
  14. led-upgrade = "/leds/internet_blue";
  15. label-mac-device = "/ethernet@1e100000/mac@0";
  16. };
  17.  
  18. cpus {
  19. #address-cells = <0x01>;
  20. #size-cells = <0x00>;
  21.  
  22. cpu@0 {
  23. device_type = "cpu";
  24. compatible = "mips,mips1004Kc";
  25. reg = <0x00>;
  26. };
  27.  
  28. cpu@1 {
  29. device_type = "cpu";
  30. compatible = "mips,mips1004Kc";
  31. reg = <0x01>;
  32. };
  33. };
  34.  
  35. cpuintc {
  36. #address-cells = <0x00>;
  37. #interrupt-cells = <0x01>;
  38. interrupt-controller;
  39. compatible = "mti,cpu-interrupt-controller";
  40. };
  41.  
  42. chosen {
  43. bootargs = "console=ttyS0,115200";
  44. };
  45.  
  46. sysclock {
  47. #clock-cells = <0x00>;
  48. compatible = "fixed-clock";
  49. clock-frequency = <0x2faf080>;
  50. phandle = <0x04>;
  51. };
  52.  
  53. palmbus@1e000000 {
  54. compatible = "palmbus";
  55. reg = <0x1e000000 0x100000>;
  56. ranges = <0x00 0x1e000000 0xfffff>;
  57. #address-cells = <0x01>;
  58. #size-cells = <0x01>;
  59.  
  60. syscon@0 {
  61. compatible = "mediatek,mt7621-sysc\0syscon";
  62. #clock-cells = <0x01>;
  63. ralink,memctl = <0x01>;
  64. clock-output-names = "xtal\0cpu\0bus\050m\0125m\0150m\0250m\0270m";
  65. reg = <0x00 0x100>;
  66. phandle = <0x0a>;
  67. };
  68.  
  69. wdt@100 {
  70. compatible = "mediatek,mt7621-wdt";
  71. reg = <0x100 0x100>;
  72. };
  73.  
  74. gpio@600 {
  75. #gpio-cells = <0x02>;
  76. #interrupt-cells = <0x02>;
  77. compatible = "mediatek,mt7621-gpio";
  78. gpio-controller;
  79. gpio-ranges = <0x02 0x00 0x00 0x5f>;
  80. interrupt-controller;
  81. reg = <0x600 0x100>;
  82. interrupt-parent = <0x03>;
  83. interrupts = <0x00 0x0c 0x04>;
  84. phandle = <0x16>;
  85. };
  86.  
  87. i2c@900 {
  88. compatible = "mediatek,mt7621-i2c";
  89. reg = <0x900 0x100>;
  90. clocks = <0x04>;
  91. resets = <0x05 0x10>;
  92. reset-names = "i2c";
  93. #address-cells = <0x01>;
  94. #size-cells = <0x00>;
  95. status = "disabled";
  96. pinctrl-names = "default";
  97. pinctrl-0 = <0x06>;
  98. };
  99.  
  100. i2s@a00 {
  101. compatible = "mediatek,mt7621-i2s";
  102. reg = <0xa00 0x100>;
  103. clocks = <0x04>;
  104. resets = <0x05 0x11>;
  105. reset-names = "i2s";
  106. interrupt-parent = <0x03>;
  107. interrupts = <0x00 0x10 0x04>;
  108. txdma-req = <0x02>;
  109. rxdma-req = <0x03>;
  110. dmas = <0x07 0x04 0x07 0x06>;
  111. dma-names = "tx\0rx";
  112. status = "disabled";
  113. };
  114.  
  115. systick@500 {
  116. compatible = "ralink,mt7621-systick\0ralink,cevt-systick";
  117. reg = <0x500 0x10>;
  118. resets = <0x05 0x1c>;
  119. reset-names = "intc";
  120. interrupt-parent = <0x03>;
  121. interrupts = <0x00 0x05 0x04>;
  122. };
  123.  
  124. syscon@5000 {
  125. compatible = "mediatek,mt7621-memc\0syscon";
  126. reg = <0x5000 0x1000>;
  127. phandle = <0x01>;
  128. };
  129.  
  130. uartlite@c00 {
  131. compatible = "ns16550a";
  132. reg = <0xc00 0x100>;
  133. clock-frequency = <0x2faf080>;
  134. interrupt-parent = <0x03>;
  135. interrupts = <0x00 0x1a 0x04>;
  136. reg-shift = <0x02>;
  137. reg-io-width = <0x04>;
  138. no-loopback-test;
  139. };
  140.  
  141. uartlite2@d00 {
  142. compatible = "ns16550a";
  143. reg = <0xd00 0x100>;
  144. clock-frequency = <0x2faf080>;
  145. interrupt-parent = <0x03>;
  146. interrupts = <0x00 0x1b 0x04>;
  147. reg-shift = <0x02>;
  148. reg-io-width = <0x04>;
  149. pinctrl-names = "default";
  150. pinctrl-0 = <0x08>;
  151. status = "disabled";
  152. };
  153.  
  154. uartlite3@e00 {
  155. compatible = "ns16550a";
  156. reg = <0xe00 0x100>;
  157. clock-frequency = <0x2faf080>;
  158. interrupt-parent = <0x03>;
  159. interrupts = <0x00 0x1c 0x04>;
  160. reg-shift = <0x02>;
  161. reg-io-width = <0x04>;
  162. pinctrl-names = "default";
  163. pinctrl-0 = <0x09>;
  164. status = "disabled";
  165. };
  166.  
  167. spi@b00 {
  168. status = "okay";
  169. compatible = "ralink,mt7621-spi";
  170. reg = <0xb00 0x100>;
  171. clocks = <0x0a 0x02>;
  172. resets = <0x05 0x12>;
  173. reset-names = "spi";
  174. #address-cells = <0x01>;
  175. #size-cells = <0x00>;
  176. pinctrl-names = "default";
  177. pinctrl-0 = <0x0b>;
  178.  
  179. flash@0 {
  180. compatible = "jedec,spi-nor";
  181. reg = <0x00>;
  182. spi-max-frequency = <0x2faf080>;
  183.  
  184. partitions {
  185. compatible = "fixed-partitions";
  186. #address-cells = <0x01>;
  187. #size-cells = <0x01>;
  188.  
  189. partition@0 {
  190. label = "u-boot";
  191. reg = <0x00 0x30000>;
  192. read-only;
  193. };
  194.  
  195. partition@30000 {
  196. label = "u-boot-env";
  197. reg = <0x30000 0x10000>;
  198. read-only;
  199. };
  200.  
  201. partition@40000 {
  202. label = "factory";
  203. reg = <0x40000 0x10000>;
  204. read-only;
  205. };
  206.  
  207. partition@50000 {
  208. compatible = "denx,uimage";
  209. label = "firmware";
  210. reg = <0x50000 0xf80000>;
  211. };
  212.  
  213. partition@fd0000 {
  214. label = "debug";
  215. reg = <0xfd0000 0x10000>;
  216. read-only;
  217. };
  218.  
  219. partition@fe0000 {
  220. label = "backup";
  221. reg = <0xfe0000 0x10000>;
  222. read-only;
  223. };
  224.  
  225. partition@ff0000 {
  226. label = "bdinfo";
  227. reg = <0xff0000 0x10000>;
  228. read-only;
  229. compatible = "nvmem-cells";
  230. #address-cells = <0x01>;
  231. #size-cells = <0x01>;
  232.  
  233. macaddr@de00 {
  234. reg = <0xde00 0x06>;
  235. phandle = <0x12>;
  236. };
  237. };
  238. };
  239. };
  240. };
  241.  
  242. gdma@2800 {
  243. compatible = "ralink,rt3883-gdma";
  244. reg = <0x2800 0x800>;
  245. resets = <0x05 0x0e>;
  246. reset-names = "dma";
  247. interrupt-parent = <0x03>;
  248. interrupts = <0x00 0x0d 0x04>;
  249. #dma-cells = <0x01>;
  250. #dma-channels = <0x10>;
  251. #dma-requests = <0x10>;
  252. status = "disabled";
  253. phandle = <0x07>;
  254. };
  255.  
  256. hsdma@7000 {
  257. compatible = "mediatek,mt7621-hsdma";
  258. reg = <0x7000 0x1000>;
  259. resets = <0x05 0x05>;
  260. reset-names = "hsdma";
  261. interrupt-parent = <0x03>;
  262. interrupts = <0x00 0x0b 0x04>;
  263. #dma-cells = <0x01>;
  264. #dma-channels = <0x01>;
  265. #dma-requests = <0x01>;
  266. status = "disabled";
  267. };
  268. };
  269.  
  270. pinctrl {
  271. compatible = "ralink,rt2880-pinmux";
  272. pinctrl-names = "default";
  273. pinctrl-0 = <0x0c>;
  274. phandle = <0x02>;
  275.  
  276. pinctrl0 {
  277. phandle = <0x0c>;
  278.  
  279. gpio {
  280. groups = "i2c\0jtag\0uart2\0uart3\0wdt";
  281. function = "gpio";
  282. };
  283. };
  284.  
  285. i2c_pins {
  286. phandle = <0x06>;
  287.  
  288. i2c_pins {
  289. groups = "i2c";
  290. function = "i2c";
  291. };
  292. };
  293.  
  294. spi_pins {
  295. phandle = <0x0b>;
  296.  
  297. spi_pins {
  298. groups = "spi";
  299. function = "spi";
  300. };
  301. };
  302.  
  303. uart1 {
  304.  
  305. uart1 {
  306. groups = "uart1";
  307. function = "uart1";
  308. };
  309. };
  310.  
  311. uart2 {
  312. phandle = <0x08>;
  313.  
  314. uart2 {
  315. groups = "uart2";
  316. function = "uart2";
  317. };
  318. };
  319.  
  320. uart3 {
  321. phandle = <0x09>;
  322.  
  323. uart3 {
  324. groups = "uart3";
  325. function = "uart3";
  326. };
  327. };
  328.  
  329. rgmii1 {
  330. phandle = <0x10>;
  331.  
  332. rgmii1 {
  333. groups = "rgmii1";
  334. function = "rgmii1";
  335. };
  336. };
  337.  
  338. rgmii2 {
  339. phandle = <0x11>;
  340.  
  341. rgmii2 {
  342. groups = "rgmii2";
  343. function = "rgmii2";
  344. };
  345. };
  346.  
  347. mdio {
  348. phandle = <0x0f>;
  349.  
  350. mdio {
  351. groups = "mdio";
  352. function = "mdio";
  353. };
  354. };
  355.  
  356. pcie {
  357. phandle = <0x15>;
  358.  
  359. pcie {
  360. groups = "pcie";
  361. function = "gpio";
  362. };
  363. };
  364.  
  365. nand {
  366.  
  367. spi-nand {
  368. groups = "spi";
  369. function = "nand1";
  370. };
  371.  
  372. sdhci-nand {
  373. groups = "sdhci";
  374. function = "nand2";
  375. };
  376. };
  377.  
  378. sdhci {
  379. phandle = <0x0d>;
  380.  
  381. sdhci {
  382. groups = "sdhci";
  383. function = "sdhci";
  384. };
  385. };
  386. };
  387.  
  388. rstctrl {
  389. compatible = "ralink,rt2880-reset";
  390. #reset-cells = <0x01>;
  391. phandle = <0x05>;
  392. };
  393.  
  394. clkctrl {
  395. compatible = "ralink,rt2880-clock";
  396. #clock-cells = <0x01>;
  397. };
  398.  
  399. sdhci@1e130000 {
  400. status = "disabled";
  401. compatible = "ralink,mt7620-sdhci";
  402. reg = <0x1e130000 0x4000>;
  403. interrupt-parent = <0x03>;
  404. interrupts = <0x00 0x14 0x04>;
  405. pinctrl-names = "default";
  406. pinctrl-0 = <0x0d>;
  407. };
  408.  
  409. xhci@1e1c0000 {
  410. #address-cells = <0x01>;
  411. #size-cells = <0x00>;
  412. compatible = "mediatek,mt8173-xhci";
  413. reg = <0x1e1c0000 0x1000 0x1e1d0700 0x100>;
  414. reg-names = "mac\0ippc";
  415. clocks = <0x04>;
  416. clock-names = "sys_ck";
  417. interrupt-parent = <0x03>;
  418. interrupts = <0x00 0x16 0x04>;
  419.  
  420. port@1 {
  421. reg = <0x01>;
  422. #trigger-source-cells = <0x00>;
  423. };
  424.  
  425. port@2 {
  426. reg = <0x02>;
  427. #trigger-source-cells = <0x00>;
  428. };
  429. };
  430.  
  431. interrupt-controller@1fbc0000 {
  432. compatible = "mti,gic";
  433. reg = <0x1fbc0000 0x2000>;
  434. interrupt-controller;
  435. #interrupt-cells = <0x03>;
  436. mti,reserved-cpu-vectors = <0x07>;
  437. phandle = <0x03>;
  438.  
  439. timer {
  440. compatible = "mti,gic-timer";
  441. interrupts = <0x01 0x01 0x00>;
  442. clocks = <0x0a 0x01>;
  443. };
  444. };
  445.  
  446. nficlock {
  447. #clock-cells = <0x00>;
  448. compatible = "fixed-clock";
  449. clock-frequency = <0x7735940>;
  450. phandle = <0x0e>;
  451. };
  452.  
  453. cpc@1fbf0000 {
  454. compatible = "mti,mips-cpc";
  455. reg = <0x1fbf0000 0x8000>;
  456. };
  457.  
  458. mc@1fbf8000 {
  459. compatible = "mti,mips-cdmm";
  460. reg = <0x1fbf8000 0x8000>;
  461. };
  462.  
  463. nand@1e003000 {
  464. status = "disabled";
  465. compatible = "mediatek,mt7621-nfc";
  466. reg = <0x1e003000 0x800 0x1e003800 0x800>;
  467. reg-names = "nfi\0ecc";
  468. clocks = <0x0e>;
  469. clock-names = "nfi_clk";
  470. };
  471.  
  472. ethernet@1e100000 {
  473. compatible = "mediatek,mt7621-eth";
  474. reg = <0x1e100000 0x10000>;
  475. clocks = <0x0a 0x09 0x0a 0x16>;
  476. clock-names = "fe\0ethif";
  477. #address-cells = <0x01>;
  478. #size-cells = <0x00>;
  479. resets = <0x05 0x06 0x05 0x17>;
  480. reset-names = "fe\0eth";
  481. interrupt-parent = <0x03>;
  482. interrupts = <0x00 0x03 0x04>;
  483. mediatek,ethsys = <0x0a>;
  484. pinctrl-names = "default";
  485. pinctrl-0 = <0x0f 0x10 0x11>;
  486.  
  487. mac@0 {
  488. compatible = "mediatek,eth-mac";
  489. reg = <0x00>;
  490. phy-mode = "rgmii";
  491. nvmem-cells = <0x12>;
  492. nvmem-cell-names = "mac-address";
  493. phandle = <0x14>;
  494.  
  495. fixed-link {
  496. speed = <0x3e8>;
  497. full-duplex;
  498. pause;
  499. };
  500. };
  501.  
  502. mac@1 {
  503. compatible = "mediatek,eth-mac";
  504. reg = <0x01>;
  505. status = "okay";
  506. phy-mode = "rgmii";
  507. label = "wan";
  508. phy-handle = <0x13>;
  509. nvmem-cells = <0x12>;
  510. nvmem-cell-names = "mac-address";
  511. mac-address-increment = <0x01>;
  512. };
  513.  
  514. mdio-bus {
  515. #address-cells = <0x01>;
  516. #size-cells = <0x00>;
  517.  
  518. switch@1f {
  519. compatible = "mediatek,mt7621";
  520. reg = <0x1f>;
  521. mediatek,mcm;
  522. resets = <0x05 0x02>;
  523. reset-names = "mcm";
  524. interrupt-controller;
  525. #interrupt-cells = <0x01>;
  526. interrupts = <0x00 0x17 0x04>;
  527.  
  528. ports {
  529. #address-cells = <0x01>;
  530. #size-cells = <0x00>;
  531.  
  532. port@0 {
  533. status = "okay";
  534. reg = <0x00>;
  535. label = "lan1";
  536. };
  537.  
  538. port@1 {
  539. status = "okay";
  540. reg = <0x01>;
  541. label = "lan2";
  542. };
  543.  
  544. port@2 {
  545. status = "okay";
  546. reg = <0x02>;
  547. label = "lan3";
  548. };
  549.  
  550. port@3 {
  551. status = "okay";
  552. reg = <0x03>;
  553. label = "lan4";
  554. };
  555.  
  556. port@4 {
  557. status = "disabled";
  558. reg = <0x04>;
  559. label = "lan4";
  560. };
  561.  
  562. port@6 {
  563. reg = <0x06>;
  564. ethernet = <0x14>;
  565. phy-mode = "rgmii";
  566.  
  567. fixed-link {
  568. speed = <0x3e8>;
  569. full-duplex;
  570. pause;
  571. };
  572. };
  573. };
  574. };
  575.  
  576. ethernet-phy@4 {
  577. reg = <0x04>;
  578. phandle = <0x13>;
  579. };
  580. };
  581. };
  582.  
  583. pcie@1e140000 {
  584. compatible = "mediatek,mt7621-pci";
  585. reg = <0x1e140000 0x100 0x1e142000 0x100 0x1e143000 0x100 0x1e144000 0x100>;
  586. #address-cells = <0x03>;
  587. #size-cells = <0x02>;
  588. pinctrl-names = "default";
  589. pinctrl-0 = <0x15>;
  590. device_type = "pci";
  591. ranges = <0x2000000 0x00 0x60000000 0x60000000 0x00 0x10000000 0x1000000 0x00 0x00 0x1e160000 0x00 0x10000>;
  592. status = "disabled";
  593. #interrupt-cells = <0x01>;
  594. interrupt-map-mask = <0xf800 0x00 0x00 0x00>;
  595. interrupt-map = <0x00 0x00 0x00 0x00 0x03 0x00 0x04 0x04 0x800 0x00 0x00 0x00 0x03 0x00 0x18 0x04 0x1000 0x00 0x00 0x00 0x03 0x00 0x19 0x04>;
  596. reset-gpios = <0x16 0x13 0x01>;
  597.  
  598. pcie@0,0 {
  599. reg = <0x00 0x00 0x00 0x00 0x00>;
  600. #address-cells = <0x03>;
  601. #size-cells = <0x02>;
  602. device_type = "pci";
  603. ranges;
  604. #interrupt-cells = <0x01>;
  605. interrupt-map-mask = <0x00 0x00 0x00 0x00>;
  606. interrupt-map = <0x00 0x00 0x00 0x00 0x03 0x00 0x04 0x04>;
  607. resets = <0x05 0x18>;
  608. clocks = <0x0a 0x17>;
  609. phys = <0x17 0x01>;
  610. phy-names = "pcie-phy0";
  611. };
  612.  
  613. pcie@1,0 {
  614. reg = <0x800 0x00 0x00 0x00 0x00>;
  615. #address-cells = <0x03>;
  616. #size-cells = <0x02>;
  617. device_type = "pci";
  618. ranges;
  619. #interrupt-cells = <0x01>;
  620. interrupt-map-mask = <0x00 0x00 0x00 0x00>;
  621. interrupt-map = <0x00 0x00 0x00 0x00 0x03 0x00 0x18 0x04>;
  622. resets = <0x05 0x19>;
  623. clocks = <0x0a 0x18>;
  624. phys = <0x17 0x01>;
  625. phy-names = "pcie-phy1";
  626. };
  627.  
  628. pcie@2,0 {
  629. reg = <0x1000 0x00 0x00 0x00 0x00>;
  630. #address-cells = <0x03>;
  631. #size-cells = <0x02>;
  632. device_type = "pci";
  633. ranges;
  634. #interrupt-cells = <0x01>;
  635. interrupt-map-mask = <0x00 0x00 0x00 0x00>;
  636. interrupt-map = <0x00 0x00 0x00 0x00 0x03 0x00 0x19 0x04>;
  637. resets = <0x05 0x1a>;
  638. clocks = <0x0a 0x19>;
  639. phys = <0x18 0x00>;
  640. phy-names = "pcie-phy2";
  641. };
  642. };
  643.  
  644. pcie-phy@1e149000 {
  645. compatible = "mediatek,mt7621-pci-phy";
  646. reg = <0x1e149000 0x700>;
  647. clocks = <0x0a 0x00>;
  648. #phy-cells = <0x01>;
  649. phandle = <0x17>;
  650. };
  651.  
  652. pcie-phy@1e14a000 {
  653. compatible = "mediatek,mt7621-pci-phy";
  654. reg = <0x1e14a000 0x700>;
  655. clocks = <0x0a 0x00>;
  656. #phy-cells = <0x01>;
  657. phandle = <0x18>;
  658. };
  659.  
  660. keys {
  661. compatible = "gpio-keys";
  662.  
  663. reset {
  664. label = "reset";
  665. gpios = <0x16 0x10 0x01>;
  666. linux,code = <0x198>;
  667. };
  668. };
  669.  
  670. leds {
  671. compatible = "gpio-leds";
  672.  
  673. internet_blue {
  674. label = "blue:internet";
  675. gpios = <0x16 0x0f 0x01>;
  676. };
  677. };
  678.  
  679. hwdog {
  680. compatible = "gpio-leds";
  681.  
  682. hwdog_blue {
  683. label = "blue:hwdog";
  684. gpios = <0x16 0x0a 0x01>;
  685. };
  686. };
  687. };
  688.  
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