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  1. /*
  2. * Copyright 2018 Kristian Evensen <kristian.evensen@gmail.com>
  3. *
  4. * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  5. */
  6.  
  7. /dts-v1/;
  8. #include <dt-bindings/input/input.h>
  9. #include "mt7623.dtsi"
  10. #include "mt6323.dtsi"
  11.  
  12. / {
  13. model = "AsiaRF MT7623-N01";
  14. compatible = "asiaRF,mt7623-n01","mediatek,mt7623";
  15.  
  16. aliases {
  17. serial2 = &uart2;
  18. };
  19.  
  20. chosen {
  21. // bootargs = "root=/dev/mmcblk0p2 rootfstype=squashfs,f2fs";
  22. bootargs = "earlyprintk console=ttyS0,115200 block2mtd.block2mtd=/dev/mmcblk0,65536,eMMC,5 mtdparts=eMMC:256k(mbr)ro,512k(uboot),256k(Config),256k(Factory),16M(firmware),2048M(usrdata),-(bmtpool) rootfstype=squashfs,jffs2";
  23. stdout-path = "serial2:115200n8";
  24. };
  25.  
  26. cpus {
  27. cpu@0 {
  28. proc-supply = <&mt6323_vproc_reg>;
  29. };
  30.  
  31. cpu@1 {
  32. proc-supply = <&mt6323_vproc_reg>;
  33. };
  34.  
  35. cpu@2 {
  36. proc-supply = <&mt6323_vproc_reg>;
  37. };
  38.  
  39. cpu@3 {
  40. proc-supply = <&mt6323_vproc_reg>;
  41. };
  42. };
  43.  
  44. reg_1p8v: regulator-1p8v {
  45. compatible = "regulator-fixed";
  46. regulator-name = "fixed-1.8V";
  47. regulator-min-microvolt = <1800000>;
  48. regulator-max-microvolt = <1800000>;
  49. regulator-boot-on;
  50. regulator-always-on;
  51. };
  52.  
  53. reg_3p3v: regulator-3p3v {
  54. compatible = "regulator-fixed";
  55. regulator-name = "fixed-3.3V";
  56. regulator-min-microvolt = <3300000>;
  57. regulator-max-microvolt = <3300000>;
  58. regulator-boot-on;
  59. regulator-always-on;
  60. };
  61.  
  62. reg_5v: regulator-5v {
  63. compatible = "regulator-fixed";
  64. regulator-name = "fixed-5V";
  65. regulator-min-microvolt = <5000000>;
  66. regulator-max-microvolt = <5000000>;
  67. regulator-boot-on;
  68. regulator-always-on;
  69. };
  70.  
  71. gpio-keys {
  72. compatible = "gpio-keys";
  73. pinctrl-names = "default";
  74. pinctrl-0 = <&key_pins_a>;
  75.  
  76. factory {
  77. label = "factory";
  78. linux,code = <KEY_RESTART>;
  79. gpios = <&pio 256 GPIO_ACTIVE_LOW>;
  80. };
  81. };
  82.  
  83. leds {
  84. compatible = "gpio-leds";
  85. pinctrl-names = "default";
  86. pinctrl-0 = <&led_pins_unielec>;
  87.  
  88. led3 {
  89. label = "u7623-01:green:led3";
  90. gpios = <&pio 14 GPIO_ACTIVE_LOW>;
  91. default-state = "off";
  92. };
  93.  
  94. led4 {
  95. label = "u7623-01:green:led4";
  96. gpios = <&pio 15 GPIO_ACTIVE_LOW>;
  97. default-state = "off";
  98. };
  99. };
  100.  
  101. memory@80000000 {
  102. device_type = "memory";
  103. reg = <0 0x80000000 0 0x40000000>;
  104. };
  105.  
  106. //dsa: dsa@0 {
  107. mt7530: switch@0 {
  108. compatible = "mediatek,mt7530";
  109.  
  110. #address-cells = <1>;
  111. #size-cells = <0>;
  112. reg = <0>;
  113.  
  114. pinctrl-names = "default";
  115. dsa,mii-bus = <&mdio>;
  116. // dsa,ethernet = <&eth>;
  117.  
  118. core-supply = <&mt6323_vpa_reg>;
  119. io-supply = <&mt6323_vemc3v3_reg>;
  120.  
  121. /* mt7623n standalone switch reset */
  122. reset-gpios = <&pio 33 0>;
  123. status = "okay";
  124.  
  125. //mt7530: switch@0 {
  126. // #address-cells = <1>;
  127. // #size-cells = <0>;
  128. // reg = <31 0>;
  129.  
  130. ports {
  131. #address-cells = <1>;
  132. #size-cells = <0>;
  133. reg = <0>;
  134.  
  135. port@0 {
  136. reg = <0>;
  137. label = "lan0";
  138. cpu = <&cpu_port0>;
  139. };
  140.  
  141. port@1 {
  142. reg = <1>;
  143. label = "lan1";
  144. cpu = <&cpu_port0>;
  145. };
  146.  
  147. port@2 {
  148. reg = <2>;
  149. label = "lan2";
  150. cpu = <&cpu_port0>;
  151. };
  152.  
  153. port@3 {
  154. reg = <3>;
  155. label = "lan3";
  156. cpu = <&cpu_port0>;
  157. };
  158.  
  159. port@4 {
  160. reg = <4>;
  161. label = "wan";
  162. cpu = <&cpu_port0>;
  163. };
  164.  
  165. // cpu_port1: port@5 {
  166. // reg = <5>;
  167. // label = "cpu";
  168. // ethernet = <&gmac1>;
  169. // phy-mode = "trgmii";
  170.  
  171. // fixed-link {
  172. // speed = <1000>;
  173. // full-duplex;
  174. // };
  175. // };
  176.  
  177. cpu_port0: port@6 {
  178. reg = <6>;
  179. label = "cpu";
  180. ethernet = <&gmac0>;
  181. phy-mode = "trgmii";
  182.  
  183. fixed-link {
  184. speed = <1000>;
  185. full-duplex;
  186. };
  187. };
  188. };
  189. //};
  190. };
  191.  
  192. };
  193.  
  194. &eth {
  195. mac-address = [00 00 00 00 00 00];
  196. status = "okay";
  197. pinctrl-names = "default";
  198. pinctrl-0 = <&ephy_default>;
  199. gmac0: mac@0 {
  200. compatible = "mediatek,eth-mac";
  201. reg = <0>;
  202. phy-mode = "trgmii";
  203.  
  204. fixed-link {
  205. speed = <1000>;
  206. full-duplex;
  207. pause;
  208. };
  209. };
  210.  
  211. gmac1: mac@1 {
  212. compatible = "mediatek,eth-mac";
  213. reg = <1>;
  214. //phy-mode = "trgmii";
  215. phy-handle = <&phy5>;
  216. //phy-mode = "rgmii";
  217.  
  218. //fixed-link {
  219. // speed = <1000>;
  220. // full-duplex;
  221. // pause;
  222. //};
  223. };
  224.  
  225. mdio: mdio-bus {
  226. #address-cells = <1>;
  227. #size-cells = <0>;
  228.  
  229. phy5: ethernet-phy@5 {
  230. reg = <5>;
  231. phy-mode = "rgmii-rxid";
  232. };
  233.  
  234. phy1f: ethernet-phy@1f {
  235. reg = <0x1f>;
  236. phy-mode = "rgmii";
  237. };
  238. };
  239.  
  240. };
  241.  
  242. //&hnat {
  243. // mtketh-wan = "eth1";
  244. // mtketh-max-gmac = <2>;
  245. // status = "okay";
  246. //};
  247.  
  248. //hnat@1b000000 {
  249. // compatible = "mediatek,mtk-hnat_v1";
  250. // reg = <0 0x1b100000 0 0x3000>;
  251. // resets = <&ethsys 0>;
  252. // reset-names = "mtketh";
  253.  
  254. // mtketh-wan = "eth1";
  255. // mtketh-max-gmac = <2>;
  256. // status = "okay";
  257. //};
  258.  
  259. &crypto {
  260. status = "okay";
  261. };
  262.  
  263. &mmc0 {
  264. pinctrl-names = "default", "state_uhs";
  265. pinctrl-0 = <&mmc0_pins_default>;
  266. pinctrl-1 = <&mmc0_pins_uhs>;
  267. status = "okay";
  268. bus-width = <8>;
  269. max-frequency = <50000000>;
  270. cap-mmc-highspeed;
  271. vmmc-supply = <&reg_3p3v>;
  272. vqmmc-supply = <&reg_1p8v>;
  273. non-removable;
  274. };
  275.  
  276. //&mmc1 {
  277. // pinctrl-names = "default", "state_uhs";
  278. // pinctrl-0 = <&mmc1_pins_default>;
  279. // pinctrl-1 = <&mmc1_pins_uhs>;
  280. // status = "disabled";
  281. // bus-width = <4>;
  282. // max-frequency = <50000000>;
  283. // cap-sd-highspeed;
  284. // cd-gpios = <&pio 261 GPIO_ACTIVE_LOW>;
  285. // vmmc-supply = <&mt6323_vmch_reg>;
  286. // vqmmc-supply = <&mt6323_vio18_reg>;
  287. //};
  288.  
  289. &pio {
  290. key_pins_a: keys-alt {
  291. pins-keys {
  292. pinmux = <MT7623_PIN_256_GPIO256_FUNC_GPIO256>,
  293. <MT7623_PIN_257_GPIO257_FUNC_GPIO257>;
  294. input-enable;
  295. };
  296. };
  297.  
  298. led_pins_unielec: leds-unielec {
  299. pins-leds {
  300. pinmux = <MT7623_PIN_14_GPIO14_FUNC_GPIO14>,
  301. <MT7623_PIN_15_GPIO15_FUNC_GPIO15>;
  302. };
  303. };
  304.  
  305. mmc0_pins_default: mmc0default {
  306. pins_cmd_dat {
  307. pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
  308. <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
  309. <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
  310. <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
  311. <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
  312. <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
  313. <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
  314. <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
  315. <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
  316. input-enable;
  317. bias-pull-up;
  318. };
  319.  
  320. pins_clk {
  321. pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
  322. bias-pull-down;
  323. };
  324.  
  325. pins_rst {
  326. pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
  327. bias-pull-up;
  328. };
  329. };
  330.  
  331. mmc0_pins_uhs: mmc0 {
  332. pins_cmd_dat {
  333. pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
  334. <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
  335. <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
  336. <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
  337. <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
  338. <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
  339. <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
  340. <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
  341. <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
  342. input-enable;
  343. drive-strength = <MTK_DRIVE_2mA>;
  344. bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
  345. };
  346.  
  347. pins_clk {
  348. pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
  349. drive-strength = <MTK_DRIVE_2mA>;
  350. bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
  351. };
  352.  
  353. pins_rst {
  354. pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
  355. bias-pull-up;
  356. };
  357. };
  358.  
  359. ephy_default: ephy_default {
  360. pins_eth {
  361. pinmux = <MT7623_PIN_275_G2_MDC_FUNC_MDC>,
  362. <MT7623_PIN_276_G2_MDIO_FUNC_MDIO>,
  363. <MT7623_PIN_262_G2_TXEN_FUNC_G2_TXEN>,
  364. <MT7623_PIN_263_G2_TXD3_FUNC_G2_TXD3>,
  365. <MT7623_PIN_264_G2_TXD2_FUNC_G2_TXD2>,
  366. <MT7623_PIN_265_G2_TXD1_FUNC_G2_TXD1>,
  367. <MT7623_PIN_266_G2_TXD0_FUNC_G2_TXD0>,
  368. <MT7623_PIN_267_G2_TXCLK_FUNC_G2_TXC>,
  369. <MT7623_PIN_268_G2_RXCLK_FUNC_G2_RXC>,
  370. <MT7623_PIN_269_G2_RXD0_FUNC_G2_RXD0>,
  371. <MT7623_PIN_270_G2_RXD1_FUNC_G2_RXD1>,
  372. <MT7623_PIN_271_G2_RXD2_FUNC_G2_RXD2>,
  373. <MT7623_PIN_272_G2_RXD3_FUNC_G2_RXD3>,
  374. <MT7623_PIN_274_G2_RXDV_FUNC_G2_RXDV>;
  375. };
  376. };
  377.  
  378. pwm_pins_a: pwm@0 {
  379. pins_pwm {
  380. pinmux = <MT7623_PIN_203_PWM0_FUNC_PWM0>,
  381. <MT7623_PIN_204_PWM1_FUNC_PWM1>,
  382. <MT7623_PIN_205_PWM2_FUNC_PWM2>,
  383. <MT7623_PIN_206_PWM3_FUNC_PWM3>,
  384. <MT7623_PIN_207_PWM4_FUNC_PWM4>;
  385. };
  386. };
  387.  
  388. // uart0_pins_a: uart@0 {
  389. // pins_dat {
  390. // pinmux = <MT7623_PIN_79_URXD0_FUNC_URXD0>,
  391. // <MT7623_PIN_80_UTXD0_FUNC_UTXD0>;
  392. // };
  393. // };
  394.  
  395. // uart1_pins_a: uart@1 {
  396. // pins_dat {
  397. // pinmux = <MT7623_PIN_81_URXD1_FUNC_URXD1>,
  398. // <MT7623_PIN_82_UTXD1_FUNC_UTXD1>;
  399. // };
  400. // };
  401.  
  402. uart2_pins_b: uart@2 {
  403. pins_dat {
  404. pinmux = <MT7623_PIN_200_URXD2_FUNC_URXD2>,
  405. <MT7623_PIN_201_UTXD2_FUNC_UTXD2>;
  406. };
  407. };
  408.  
  409. pcie_default: pcie_pin_default {
  410. pins_cmd_dat {
  411. pinmux =
  412. // <MT7623_PIN_28_EINT6_FUNC_PCIE0_WAKE_N>,
  413. // <MT7623_PIN_27_EINT5_FUNC_PCIE1_WAKE_N>,
  414. // <MT7623_PIN_26_EINT4_FUNC_PCIE2_WAKE_N>,
  415.  
  416. // <MT7623_PIN_250_GPIO250_FUNC_PCIE0_CLKREQ_N>,
  417. // <MT7623_PIN_252_GPIO252_FUNC_PCIE1_CLKREQ_N>,
  418. // <MT7623_PIN_254_GPIO254_FUNC_PCIE2_CLKREQ_N>,
  419.  
  420. <MT7623_PIN_208_AUD_EXT_CK1_FUNC_PCIE0_PERST_N>,
  421. <MT7623_PIN_209_AUD_EXT_CK2_FUNC_PCIE1_PERST_N>,
  422. <MT7623_PIN_24_EINT2_FUNC_PCIE2_PERST_N>;
  423. bias-disable;
  424. };
  425. };
  426. };
  427.  
  428. &pwm {
  429. pinctrl-names = "default";
  430. pinctrl-0 = <&pwm_pins_a>;
  431. status = "disabled";
  432. };
  433.  
  434. &pwrap {
  435. mt6323 {
  436. mt6323led: led {
  437. compatible = "mediatek,mt6323-led";
  438. #address-cells = <1>;
  439. #size-cells = <0>;
  440.  
  441. led@0 {
  442. reg = <0>;
  443. label = "led0";
  444. default-state = "off";
  445. };
  446. };
  447. };
  448. };
  449.  
  450. //&spi0 {
  451. // pinctrl-names = "default";
  452. // pinctrl-0 = <&spi0_pins_a>;
  453. // status = "okay";
  454. //};
  455.  
  456. //&uart0 {
  457. // pinctrl-names = "default";
  458. // pinctrl-0 = <&uart0_pins_a>;
  459. // status = "disabled";
  460. //};
  461.  
  462. //&uart1 {
  463. // pinctrl-names = "default";
  464. // pinctrl-0 = <&uart1_pins_a>;
  465. // status = "disabled";
  466. //};
  467.  
  468. &uart2 {
  469. pinctrl-names = "default";
  470. pinctrl-0 = <&uart2_pins_b>;
  471. status = "okay";
  472. };
  473.  
  474. &usb1 {
  475. vusb33-supply = <&reg_3p3v>;
  476. vbus-supply = <&reg_3p3v>;
  477. status = "okay";
  478. };
  479.  
  480. //&usb2 {
  481. // vusb33-supply = <&reg_3p3v>;
  482. // vbus-supply = <&reg_5v>;
  483. // status = "okay";
  484. //};
  485.  
  486. &u3phy1 {
  487. status = "okay";
  488. };
  489.  
  490. &u3phy2 {
  491. status = "okay";
  492. mediatek,phy-switch = <&hifsys>;
  493. };
  494.  
  495. &pcie {
  496. pinctrl-names = "default";
  497. pinctrl-0 = <&pcie_default>;
  498. status = "okay";
  499.  
  500. pcie@0,0 {
  501. status = "okay";
  502. };
  503.  
  504. pcie@1,0 {
  505. status = "okay";
  506. };
  507.  
  508. pcie@2,0 {
  509. status = "okay";
  510. };
  511. };
  512.  
  513. &pcie0_phy {
  514. status = "okay";
  515. };
  516.  
  517. &pcie1_phy {
  518. status = "okay";
  519. };
  520.  
  521.  
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