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  1. diff --git a/bfd/archures.c b/bfd/archures.c
  2. index e83c57a..8e65a3d 100644
  3. --- a/bfd/archures.c
  4. +++ b/bfd/archures.c
  5. @@ -193,7 +193,9 @@ DESCRIPTION
  6. .#define bfd_mach_mips5 5
  7. .#define bfd_mach_mips_loongson_2e 3001
  8. .#define bfd_mach_mips_loongson_2f 3002
  9. -.#define bfd_mach_mips_loongson_3a 3003
  10. +.#define bfd_mach_mips_gs464 3003
  11. +.#define bfd_mach_mips_gs464e 3004
  12. +.#define bfd_mach_mips_gs264e 3005
  13. .#define bfd_mach_mips_sb1 12310201 {* octal 'SB', 01. *}
  14. .#define bfd_mach_mips_octeon 6501
  15. .#define bfd_mach_mips_octeonp 6601
  16. diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
  17. index f4b3720..95078d1 100644
  18. --- a/bfd/bfd-in2.h
  19. +++ b/bfd/bfd-in2.h
  20. @@ -2054,7 +2054,9 @@ enum bfd_architecture
  21. #define bfd_mach_mips5 5
  22. #define bfd_mach_mips_loongson_2e 3001
  23. #define bfd_mach_mips_loongson_2f 3002
  24. -#define bfd_mach_mips_loongson_3a 3003
  25. +#define bfd_mach_mips_gs464 3003
  26. +#define bfd_mach_mips_gs464e 3004
  27. +#define bfd_mach_mips_gs264e 3005
  28. #define bfd_mach_mips_sb1 12310201 /* octal 'SB', 01. */
  29. #define bfd_mach_mips_octeon 6501
  30. #define bfd_mach_mips_octeonp 6601
  31. diff --git a/bfd/cpu-mips.c b/bfd/cpu-mips.c
  32. index cb50c64..339b111 100644
  33. --- a/bfd/cpu-mips.c
  34. +++ b/bfd/cpu-mips.c
  35. @@ -98,7 +98,9 @@ enum
  36. I_sb1,
  37. I_loongson_2e,
  38. I_loongson_2f,
  39. - I_loongson_3a,
  40. + I_gs464,
  41. + I_gs464e,
  42. + I_gs264e,
  43. I_mipsocteon,
  44. I_mipsocteonp,
  45. I_mipsocteon2,
  46. @@ -150,7 +152,9 @@ static const bfd_arch_info_type arch_info_struct[] =
  47. N (64, 64, bfd_mach_mips_sb1, "mips:sb1", FALSE, NN(I_sb1)),
  48. N (64, 64, bfd_mach_mips_loongson_2e, "mips:loongson_2e", FALSE, NN(I_loongson_2e)),
  49. N (64, 64, bfd_mach_mips_loongson_2f, "mips:loongson_2f", FALSE, NN(I_loongson_2f)),
  50. - N (64, 64, bfd_mach_mips_loongson_3a, "mips:loongson_3a", FALSE, NN(I_loongson_3a)),
  51. + N (64, 64, bfd_mach_mips_gs464, "mips:gs464", FALSE, NN(I_gs464)),
  52. + N (64, 64, bfd_mach_mips_gs464e, "mips:gs464e", FALSE, NN(I_gs464e)),
  53. + N (64, 64, bfd_mach_mips_gs264e, "mips:gs264e", FALSE, NN(I_gs264e)),
  54. N (64, 64, bfd_mach_mips_octeon,"mips:octeon", FALSE, NN(I_mipsocteon)),
  55. N (64, 64, bfd_mach_mips_octeonp,"mips:octeon+", FALSE, NN(I_mipsocteonp)),
  56. N (64, 64, bfd_mach_mips_octeon2,"mips:octeon2", FALSE, NN(I_mipsocteon2)),
  57. diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c
  58. index b237957..556560f 100644
  59. --- a/bfd/elfxx-mips.c
  60. +++ b/bfd/elfxx-mips.c
  61. @@ -6815,8 +6815,14 @@ _bfd_elf_mips_mach (flagword flags)
  62. case E_MIPS_MACH_LS2F:
  63. return bfd_mach_mips_loongson_2f;
  64.  
  65. - case E_MIPS_MACH_LS3A:
  66. - return bfd_mach_mips_loongson_3a;
  67. + case E_MIPS_MACH_GS464:
  68. + return bfd_mach_mips_gs464;
  69. +
  70. + case E_MIPS_MACH_GS464E:
  71. + return bfd_mach_mips_gs464e;
  72. +
  73. + case E_MIPS_MACH_GS264E:
  74. + return bfd_mach_mips_gs264e;
  75.  
  76. case E_MIPS_MACH_OCTEON3:
  77. return bfd_mach_mips_octeon3;
  78. @@ -11888,8 +11894,8 @@ mips_set_isa_flags (bfd *abfd)
  79. switch (bfd_get_mach (abfd))
  80. {
  81. default:
  82. - case bfd_mach_mips_loongson_3a:
  83. - val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_LS3A;
  84. + case bfd_mach_mips_gs464:
  85. + val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_GS464;
  86. break;
  87.  
  88. case bfd_mach_mips3000:
  89. @@ -11973,6 +11979,14 @@ mips_set_isa_flags (bfd *abfd)
  90. val = E_MIPS_ARCH_64 | E_MIPS_MACH_SB1;
  91. break;
  92.  
  93. + case bfd_mach_mips_gs464e:
  94. + val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_GS464E;
  95. + break;
  96. +
  97. + case bfd_mach_mips_gs264e:
  98. + val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_GS264E;
  99. + break;
  100. +
  101. case bfd_mach_mips_octeon:
  102. case bfd_mach_mips_octeonp:
  103. val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON;
  104. @@ -13962,7 +13976,9 @@ static const struct mips_mach_extension mips_mach_extensions[] =
  105. { bfd_mach_mips_octeon2, bfd_mach_mips_octeonp },
  106. { bfd_mach_mips_octeonp, bfd_mach_mips_octeon },
  107. { bfd_mach_mips_octeon, bfd_mach_mipsisa64r2 },
  108. - { bfd_mach_mips_loongson_3a, bfd_mach_mipsisa64r2 },
  109. + { bfd_mach_mips_gs264e, bfd_mach_mips_gs464e },
  110. + { bfd_mach_mips_gs464e, bfd_mach_mips_gs464 },
  111. + { bfd_mach_mips_gs464, bfd_mach_mipsisa64r2 },
  112.  
  113. /* MIPS64 extensions. */
  114. { bfd_mach_mipsisa64r2, bfd_mach_mipsisa64 },
  115. @@ -14074,7 +14090,6 @@ bfd_mips_isa_ext_mach (unsigned int isa_ext)
  116. case AFL_EXT_10000: return bfd_mach_mips10000;
  117. case AFL_EXT_LOONGSON_2E: return bfd_mach_mips_loongson_2e;
  118. case AFL_EXT_LOONGSON_2F: return bfd_mach_mips_loongson_2f;
  119. - case AFL_EXT_LOONGSON_3A: return bfd_mach_mips_loongson_3a;
  120. case AFL_EXT_SB1: return bfd_mach_mips_sb1;
  121. case AFL_EXT_OCTEON: return bfd_mach_mips_octeon;
  122. case AFL_EXT_OCTEONP: return bfd_mach_mips_octeonp;
  123. @@ -14103,7 +14118,6 @@ bfd_mips_isa_ext (bfd *abfd)
  124. case bfd_mach_mips10000: return AFL_EXT_10000;
  125. case bfd_mach_mips_loongson_2e: return AFL_EXT_LOONGSON_2E;
  126. case bfd_mach_mips_loongson_2f: return AFL_EXT_LOONGSON_2F;
  127. - case bfd_mach_mips_loongson_3a: return AFL_EXT_LOONGSON_3A;
  128. case bfd_mach_mips_sb1: return AFL_EXT_SB1;
  129. case bfd_mach_mips_octeon: return AFL_EXT_OCTEON;
  130. case bfd_mach_mips_octeonp: return AFL_EXT_OCTEONP;
  131. @@ -14219,7 +14233,7 @@ infer_mips_abiflags (bfd *abfd, Elf_Internal_ABIFlags_v0* abiflags)
  132. && abiflags->fp_abi != Val_GNU_MIPS_ABI_FP_SOFT
  133. && abiflags->fp_abi != Val_GNU_MIPS_ABI_FP_64A
  134. && abiflags->isa_level >= 32
  135. - && abiflags->isa_ext != AFL_EXT_LOONGSON_3A)
  136. + && abiflags->ases != AFL_ASE_LOONGSON_EXT)
  137. abiflags->flags1 |= AFL_FLAGS1_ODDSPREG;
  138. }
  139.  
  140. @@ -15644,6 +15658,14 @@ print_mips_ases (FILE *file, unsigned int mask)
  141. fputs ("\n\tXPA ASE", file);
  142. if (mask & AFL_ASE_MIPS16E2)
  143. fputs ("\n\tMIPS16e2 ASE", file);
  144. + if (mask & AFL_ASE_LOONGSON_MMI)
  145. + fputs ("\n\tLoongson MMI ASE", file);
  146. + if (mask & AFL_ASE_LOONGSON_CAM)
  147. + fputs ("\n\tLoongson CAM ASE", file);
  148. + if (mask & AFL_ASE_LOONGSON_EXT)
  149. + fputs ("\n\tLoongson EXT ASE", file);
  150. + if (mask & AFL_ASE_LOONGSON_EXT2)
  151. + fputs ("\n\tLoongson EXT2 ASE", file);
  152. if (mask == 0)
  153. fprintf (file, "\n\t%s", _("None"));
  154. else if ((mask & ~AFL_ASE_MASK) != 0)
  155. @@ -15670,9 +15692,6 @@ print_mips_isa_ext (FILE *file, unsigned int isa_ext)
  156. case AFL_EXT_OCTEONP:
  157. fputs ("Cavium Networks OcteonP", file);
  158. break;
  159. - case AFL_EXT_LOONGSON_3A:
  160. - fputs ("Loongson 3A", file);
  161. - break;
  162. case AFL_EXT_OCTEON:
  163. fputs ("Cavium Networks Octeon", file);
  164. break;
  165. diff --git a/binutils/MAINTAINERS b/binutils/MAINTAINERS
  166. index 3bb542d..92c7b74 100644
  167. --- a/binutils/MAINTAINERS
  168. +++ b/binutils/MAINTAINERS
  169. @@ -104,6 +104,7 @@ responsibility among the other maintainers.
  170. MEP Dave Brolley <brolley@redhat.com>
  171. METAG Markos Chandras <markos.chandras@imgtec.com>
  172. MICROBLAZE Michael Eager <eager@eagercon.com>
  173. + MIPS Chenghua Xu <paul.hua.gm@gmail.com>
  174. MIPS Maciej W. Rozycki <macro@mips.com>
  175. MMIX Hans-Peter Nilsson <hp@bitrange.com>
  176. MN10300 Alexandre Oliva <aoliva@redhat.com>
  177. diff --git a/binutils/readelf.c b/binutils/readelf.c
  178. index 761c8d5..ee193f5 100644
  179. --- a/binutils/readelf.c
  180. +++ b/binutils/readelf.c
  181. @@ -3366,7 +3366,9 @@ get_machine_flags (Filedata * filedata, unsigned e_flags, unsigned e_machine)
  182. case E_MIPS_MACH_9000: strcat (buf, ", 9000"); break;
  183. case E_MIPS_MACH_LS2E: strcat (buf, ", loongson-2e"); break;
  184. case E_MIPS_MACH_LS2F: strcat (buf, ", loongson-2f"); break;
  185. - case E_MIPS_MACH_LS3A: strcat (buf, ", loongson-3a"); break;
  186. + case E_MIPS_MACH_GS464: strcat (buf, ", gs464"); break;
  187. + case E_MIPS_MACH_GS464E: strcat (buf, ", gs464e"); break;
  188. + case E_MIPS_MACH_GS264E: strcat (buf, ", gs264e"); break;
  189. case E_MIPS_MACH_OCTEON: strcat (buf, ", octeon"); break;
  190. case E_MIPS_MACH_OCTEON2: strcat (buf, ", octeon2"); break;
  191. case E_MIPS_MACH_OCTEON3: strcat (buf, ", octeon3"); break;
  192. @@ -15455,6 +15457,14 @@ print_mips_ases (unsigned int mask)
  193. fputs ("\n\tXPA ASE", stdout);
  194. if (mask & AFL_ASE_MIPS16E2)
  195. fputs ("\n\tMIPS16e2 ASE", stdout);
  196. + if (mask & AFL_ASE_LOONGSON_MMI)
  197. + fputs ("\n\tLoongson MMI ASE", stdout);
  198. + if (mask & AFL_ASE_LOONGSON_CAM)
  199. + fputs ("\n\tLoongson CAM ASE", stdout);
  200. + if (mask & AFL_ASE_LOONGSON_EXT)
  201. + fputs ("\n\tLoongson EXT ASE", stdout);
  202. + if (mask & AFL_ASE_LOONGSON_EXT2)
  203. + fputs ("\n\tLoongson EXT2 ASE", stdout);
  204. if (mask == 0)
  205. fprintf (stdout, "\n\t%s", _("None"));
  206. else if ((mask & ~AFL_ASE_MASK) != 0)
  207. @@ -15481,9 +15491,6 @@ print_mips_isa_ext (unsigned int isa_ext)
  208. case AFL_EXT_OCTEONP:
  209. fputs ("Cavium Networks OcteonP", stdout);
  210. break;
  211. - case AFL_EXT_LOONGSON_3A:
  212. - fputs ("Loongson 3A", stdout);
  213. - break;
  214. case AFL_EXT_OCTEON:
  215. fputs ("Cavium Networks Octeon", stdout);
  216. break;
  217. diff --git a/elfcpp/mips.h b/elfcpp/mips.h
  218. index cac8592..c724fd0 100644
  219. --- a/elfcpp/mips.h
  220. +++ b/elfcpp/mips.h
  221. @@ -235,7 +235,9 @@ enum
  222. E_MIPS_MACH_9000 = 0x00990000,
  223. E_MIPS_MACH_LS2E = 0x00A00000,
  224. E_MIPS_MACH_LS2F = 0x00A10000,
  225. - E_MIPS_MACH_LS3A = 0x00A20000,
  226. + E_MIPS_MACH_GS464 = 0x00A20000,
  227. + E_MIPS_MACH_GS464E = 0x00A30000,
  228. + E_MIPS_MACH_GS264E = 0x00A40000,
  229. };
  230.  
  231. // MIPS architecture
  232. @@ -308,7 +310,9 @@ enum
  233. // MICROMIPS ASE.
  234. AFL_ASE_MICROMIPS = 0x00000800,
  235. // XPA ASE.
  236. - AFL_ASE_XPA = 0x00001000
  237. + AFL_ASE_XPA = 0x00001000,
  238. + // Loongson EXT ASE.
  239. + AFL_ASE_LOONGSON_EXT = 0x00002000
  240. };
  241.  
  242. // Values for the isa_ext word of an ABI flags structure.
  243. diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
  244. index 8c0cda9..a221800 100644
  245. --- a/gas/config/tc-mips.c
  246. +++ b/gas/config/tc-mips.c
  247. @@ -422,7 +422,9 @@ static int mips_32bitmode = 0;
  248. || (ISA) == ISA_MIPS64R5 \
  249. || (ISA) == ISA_MIPS64R6 \
  250. || (CPU) == CPU_R5900) \
  251. - && (CPU) != CPU_LOONGSON_3A)
  252. + && ((CPU) != CPU_GS464 \
  253. + || (CPU) != CPU_GS464E \
  254. + || (CPU) != CPU_GS264E))
  255.  
  256. /* Return true if ISA supports move to/from high part of a 64-bit
  257. floating-point register. */
  258. @@ -1540,6 +1542,14 @@ enum options
  259. OPTION_NAN,
  260. OPTION_ODD_SPREG,
  261. OPTION_NO_ODD_SPREG,
  262. + OPTION_LOONGSON_MMI,
  263. + OPTION_NO_LOONGSON_MMI,
  264. + OPTION_LOONGSON_CAM,
  265. + OPTION_NO_LOONGSON_CAM,
  266. + OPTION_LOONGSON_EXT,
  267. + OPTION_NO_LOONGSON_EXT,
  268. + OPTION_LOONGSON_EXT2,
  269. + OPTION_NO_LOONGSON_EXT2,
  270. OPTION_END_OF_ENUM
  271. };
  272.  
  273. @@ -1596,6 +1606,14 @@ struct option md_longopts[] =
  274. {"mno-xpa", no_argument, NULL, OPTION_NO_XPA},
  275. {"mmips16e2", no_argument, NULL, OPTION_MIPS16E2},
  276. {"mno-mips16e2", no_argument, NULL, OPTION_NO_MIPS16E2},
  277. + {"mloongson-mmi", no_argument, NULL, OPTION_LOONGSON_MMI},
  278. + {"mno-loongson-mmi", no_argument, NULL, OPTION_NO_LOONGSON_MMI},
  279. + {"mloongson-cam", no_argument, NULL, OPTION_LOONGSON_CAM},
  280. + {"mno-loongson-cam", no_argument, NULL, OPTION_NO_LOONGSON_CAM},
  281. + {"mloongson-ext", no_argument, NULL, OPTION_LOONGSON_EXT},
  282. + {"mno-loongson-ext", no_argument, NULL, OPTION_NO_LOONGSON_EXT},
  283. + {"mloongson-ext2", no_argument, NULL, OPTION_LOONGSON_EXT2},
  284. + {"mno-loongson-ext2", no_argument, NULL, OPTION_NO_LOONGSON_EXT2},
  285.  
  286. /* Old-style architecture options. Don't add more of these. */
  287. {"m4650", no_argument, NULL, OPTION_M4650},
  288. @@ -1787,6 +1805,26 @@ static const struct mips_ase mips_ases[] = {
  289. OPTION_MIPS16E2, OPTION_NO_MIPS16E2,
  290. 2, 2, -1, -1,
  291. 6 },
  292. +
  293. + { "loongson-mmi", ASE_LOONGSON_MMI, 0,
  294. + OPTION_LOONGSON_MMI, OPTION_NO_LOONGSON_MMI,
  295. + 0, 0, -1, -1,
  296. + -1 },
  297. +
  298. + { "loongson-cam", ASE_LOONGSON_CAM, 0,
  299. + OPTION_LOONGSON_CAM, OPTION_NO_LOONGSON_CAM,
  300. + 0, 0, -1, -1,
  301. + -1 },
  302. +
  303. + { "loongson-ext", ASE_LOONGSON_EXT, 0,
  304. + OPTION_LOONGSON_EXT, OPTION_NO_LOONGSON_EXT,
  305. + 0, 0, -1, -1,
  306. + -1 },
  307. +
  308. + { "loongson-ext2", ASE_LOONGSON_EXT | ASE_LOONGSON_EXT2, 0,
  309. + OPTION_LOONGSON_EXT2, OPTION_NO_LOONGSON_EXT2,
  310. + 0, 0, -1, -1,
  311. + -1 },
  312. };
  313.  
  314. /* The set of ASEs that require -mfp64. */
  315. @@ -1794,7 +1832,8 @@ static const struct mips_ase mips_ases[] = {
  316.  
  317. /* Groups of ASE_* flags that represent different revisions of an ASE. */
  318. static const unsigned int mips_ase_groups[] = {
  319. - ASE_DSP | ASE_DSPR2 | ASE_DSPR3
  320. + ASE_DSP | ASE_DSPR2 | ASE_DSPR3,
  321. + ASE_LOONGSON_EXT | ASE_LOONGSON_EXT2
  322. };
  324. /* Pseudo-op table.
  325. @@ -19114,6 +19153,14 @@ mips_convert_ase_flags (int ase)
  326. ext_ases |= AFL_ASE_XPA;
  327. if (ase & ASE_MIPS16E2)
  328. ext_ases |= file_ase_mips16 ? AFL_ASE_MIPS16E2 : 0;
  329. + if (ase & ASE_LOONGSON_MMI)
  330. + ext_ases |= AFL_ASE_LOONGSON_MMI;
  331. + if (ase & ASE_LOONGSON_CAM)
  332. + ext_ases |= AFL_ASE_LOONGSON_CAM;
  333. + if (ase & ASE_LOONGSON_EXT)
  334. + ext_ases |= AFL_ASE_LOONGSON_EXT;
  335. + if (ase & ASE_LOONGSON_EXT2)
  336. + ext_ases |= AFL_ASE_LOONGSON_EXT2;
  337.  
  338. return ext_ases;
  339. }
  340. @@ -19760,7 +19807,7 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
  341. { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 },
  342. /* ST Microelectronics Loongson 2E and 2F cores */
  343. { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E },
  344. - { "loongson2f", 0, 0, ISA_MIPS3, CPU_LOONGSON_2F },
  345. + { "loongson2f", 0, ASE_LOONGSON_MMI, ISA_MIPS3, CPU_LOONGSON_2F },
  346.  
  347. /* MIPS IV */
  348. { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 },
  349. @@ -19859,9 +19906,17 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
  350. /* Broadcom SB-1A CPU core */
  351. { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
  352.  
  353. - { "loongson3a", 0, 0, ISA_MIPS64R2, CPU_LOONGSON_3A },
  354. -
  355. /* MIPS 64 Release 2 */
  356. + /* Loongson CPU core */
  357. + /* -march=loongson3a is an alias of -march=gs464 for compatibility */
  358. + { "loongson3a", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT,
  359. + ISA_MIPS64R2, CPU_GS464 },
  360. + { "gs464", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT,
  361. + ISA_MIPS64R2, CPU_GS464 },
  362. + { "gs464e", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT
  363. + | ASE_LOONGSON_EXT2, ISA_MIPS64R2, CPU_GS464E },
  364. + { "gs264e", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT
  365. + | ASE_LOONGSON_EXT2 | ASE_MSA | ASE_MSA64, ISA_MIPS64R2, CPU_GS264E },
  366.  
  367. /* Cavium Networks Octeon CPU core */
  368. { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON },
  369. @@ -20125,6 +20180,18 @@ MIPS options:\n\
  370. -mvirt generate Virtualization instructions\n\
  371. -mno-virt do not generate Virtualization instructions\n"));
  372. fprintf (stream, _("\
  373. +-mloongson-mmi generate Loongson MultiMedia extensions Instructions (MMI) instructions\n\
  374. +-mno-loongson-mmi do not generate Loongson MultiMedia extensions Instructions\n"));
  375. + fprintf (stream, _("\
  376. +-mloongson-cam generate Loongson Content Address Memory (CAM) instructions\n\
  377. +-mno-loongson-cam do not generate Loongson Content Address Memory Instructions\n"));
  378. + fprintf (stream, _("\
  379. +-mloongson-ext generate Loongson EXTensions (EXT) instructions\n\
  380. +-mno-loongson-ext do not generate Loongson EXTensions Instructions\n"));
  381. + fprintf (stream, _("\
  382. +-mloongson-ext2 generate Loongson EXTensions R2 (EXT2) instructions\n\
  383. +-mno-loongson-ext2 do not generate Loongson EXTensions R2 Instructions\n"));
  384. + fprintf (stream, _("\
  385. -minsn32 only generate 32-bit microMIPS instructions\n\
  386. -mno-insn32 generate all microMIPS instructions\n"));
  387. fprintf (stream, _("\
  388. diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi
  389. index 650d886..3d4c93e 100644
  390. --- a/gas/doc/c-mips.texi
  391. +++ b/gas/doc/c-mips.texi
  392. @@ -234,6 +234,34 @@ Generate code for the Virtualization Application Specific Extension.
  393. This tells the assembler to accept Virtualization instructions.
  394. @samp{-mno-virt} turns off this option.
  395.  
  396. +@item -mloongson-mmi
  397. +@itemx -mno-loongson-mmi
  398. +Generate code for the Loongson MultiMedia extensions Instructions (MMI)
  399. +Application Specific Extension. This tells the assembler to accept MMI
  400. +instructions.
  401. +@samp{-mno-loongson-mmi} turns off this option.
  402. +
  403. +@item -mloongson-cam
  404. +@itemx -mno-loongson-cam
  405. +Generate code for the Loongson Content Address Memory (CAM)
  406. +Application Specific Extension. This tells the assembler to accept CAM
  407. +instructions.
  408. +@samp{-mno-loongson-cam} turns off this option.
  409. +
  410. +@item -mloongson-ext
  411. +@itemx -mno-loongson-ext
  412. +Generate code for the Loongson EXTensions (EXT) instructions
  413. +Application Specific Extension. This tells the assembler to accept EXT
  414. +instructions.
  415. +@samp{-mno-loongson-ext} turns off this option.
  416. +
  417. +@item -mloongson-ext2
  418. +@itemx -mno-loongson-ext2
  419. +Generate code for the Loongson EXTensions R2 (EXT2) instructions
  420. +Application Specific Extension. This tells the assembler to accept EXT2
  421. +instructions.
  422. +@samp{-mno-loongson-ext2} turns off this option.
  423. +
  424. @item -minsn32
  425. @itemx -mno-insn32
  426. Only use 32-bit instruction encodings when generating code for the
  427. @@ -397,7 +425,9 @@ i6400,
  428. p6600,
  429. loongson2e,
  430. loongson2f,
  431. -loongson3a,
  432. +gs464,
  433. +gs464e,
  434. +gs264e,
  435. octeon,
  436. octeon+,
  437. octeon2,
  438. @@ -1134,6 +1164,39 @@ float-point operations. These directives always override the default
  439. (that double-precision operations are accepted) or the command-line
  440. options (@samp{-msingle-float} and @samp{-mdouble-float}).
  441.  
  442. +@cindex Loongson MultiMedia extensions Instructions (MMI) generation override
  443. +@kindex @code{.set loongson-mmi}
  444. +@kindex @code{.set noloongson-mmi}
  445. +The directive @code{.set loongson-mmi} makes the assembler accept
  446. +instructions from the MMI Extension from that point on in the assembly.
  447. +The @code{.set noloongson-mmi} directive prevents MMI instructions from
  448. +being accepted.
  449. +
  450. +@cindex Loongson Content Address Memory (CAM) generation override
  451. +@kindex @code{.set loongson-cam}
  452. +@kindex @code{.set noloongson-cam}
  453. +The directive @code{.set loongson-cam} makes the assembler accept
  454. +instructions from the Loongson CAM from that point on in the assembly.
  455. +The @code{.set noloongson-cam} directive prevents Loongson CAM instructions
  456. +from being accepted.
  457. +
  458. +@cindex Loongson EXTensions (EXT) instructions generation override
  459. +@kindex @code{.set loongson-ext}
  460. +@kindex @code{.set noloongson-ext}
  461. +The directive @code{.set loongson-ext} makes the assembler accept
  462. +instructions from the Loongson EXT from that point on in the assembly.
  463. +The @code{.set noloongson-ext} directive prevents Loongson EXT instructions
  464. +from being accepted.
  465. +
  466. +@cindex Loongson EXTensions R2 (EXT2) instructions generation override
  467. +@kindex @code{.set loongson-ext2}
  468. +@kindex @code{.set noloongson-ext2}
  469. +The directive @code{.set loongson-ext2} makes the assembler accept
  470. +instructions from the Loongson EXT2 from that point on in the assembly.
  471. +This directive implies @code{.set loognson-ext}.
  472. +The @code{.set noloongson-ext2} directive prevents Loongson EXT2 instructions
  473. +from being accepted.
  474. +
  475. Traditional MIPS assemblers do not support these directives.
  476.  
  477. @node MIPS Syntax
  478. diff --git a/gas/testsuite/gas/mips/loongson-2f-mmi.d b/gas/testsuite/gas/mips/loongson-2f-mmi.d
  479. new file mode 100644
  480. index 0000000..84224f9
  481. --- /dev/null
  482. +++ b/gas/testsuite/gas/mips/loongson-2f-mmi.d
  483. @@ -0,0 +1,106 @@
  484. +#as: -march=loongson2f -mabi=o64
  485. +#objdump: -M reg-names=numeric -dp
  486. +#name: Loongson-2F MMI tests
  487. +
  488. +.*: file format .*
  489. +
  490. +private flags = .*
  491. +
  492. +MIPS ABI Flags Version: 0
  493. +ISA: .*
  494. +GPR size: .*
  495. +CPR1 size: .*
  496. +CPR2 size: .*
  497. +FP ABI: .*
  498. +ISA Extension: ST Microelectronics Loongson 2F
  499. +ASEs:
  500. + Loongson MMI ASE
  501. +FLAGS 1: .*
  502. +FLAGS 2: .*
  503. +
  504. +Disassembly of section .text:
  505. +
  506. +[0-9a-f]+ <simd_insns>:
  507. +.*: 4b420802 packsshb \$f0,\$f1,\$f2
  508. +.*: 4b2520c2 packsswh \$f3,\$f4,\$f5
  509. +.*: 4b683982 packushb \$f6,\$f7,\$f8
  510. +.*: 4bcb5240 paddb \$f9,\$f10,\$f11
  511. +.*: 4b4e6b00 paddh \$f12,\$f13,\$f14
  512. +.*: 4b7183c0 paddw \$f15,\$f16,\$f17
  513. +.*: 4bf49c80 paddd \$f18,\$f19,\$f20
  514. +.*: 4b97b540 paddsb \$f21,\$f22,\$f23
  515. +.*: 4b1ace00 paddsh \$f24,\$f25,\$f26
  516. +.*: 4bbde6c0 paddusb \$f27,\$f28,\$f29
  517. +.*: 4b220800 paddush \$f0,\$f1,\$f2
  518. +.*: 4be520c2 pandn \$f3,\$f4,\$f5
  519. +.*: 4b283988 pavgb \$f6,\$f7,\$f8
  520. +.*: 4b0b5248 pavgh \$f9,\$f10,\$f11
  521. +.*: 4b8e6b09 pcmpeqb \$f12,\$f13,\$f14
  522. +.*: 4b5183c9 pcmpeqh \$f15,\$f16,\$f17
  523. +.*: 4b149c89 pcmpeqw \$f18,\$f19,\$f20
  524. +.*: 4bb7b549 pcmpgtb \$f21,\$f22,\$f23
  525. +.*: 4b7ace09 pcmpgth \$f24,\$f25,\$f26
  526. +.*: 4b3de6c9 pcmpgtw \$f27,\$f28,\$f29
  527. +.*: 4b42080e pextrh \$f0,\$f1,\$f2
  528. +.*: 4b8520c3 pinsrh_0 \$f3,\$f4,\$f5
  529. +.*: 4ba83983 pinsrh_1 \$f6,\$f7,\$f8
  530. +.*: 4bcb5243 pinsrh_2 \$f9,\$f10,\$f11
  531. +.*: 4bee6b03 pinsrh_3 \$f12,\$f13,\$f14
  532. +.*: 4b7183ce pmaddhw \$f15,\$f16,\$f17
  533. +.*: 4b549c88 pmaxsh \$f18,\$f19,\$f20
  534. +.*: 4b97b548 pmaxub \$f21,\$f22,\$f23
  535. +.*: 4b7ace08 pminsh \$f24,\$f25,\$f26
  536. +.*: 4bbde6c8 pminub \$f27,\$f28,\$f29
  537. +.*: 4ba0080f pmovmskb \$f0,\$f1
  538. +.*: 4ba4188a pmulhuh \$f2,\$f3,\$f4
  539. +.*: 4b67314a pmulhh \$f5,\$f6,\$f7
  540. +.*: 4b4a4a0a pmullh \$f8,\$f9,\$f10
  541. +.*: 4b8d62ca pmuluw \$f11,\$f12,\$f13
  542. +.*: 4b307b8d pasubub \$f14,\$f15,\$f16
  543. +.*: 4b80944f biadd \$f17,\$f18
  544. +.*: 4b15a4c2 pshufh \$f19,\$f20,\$f21
  545. +.*: 4b38bd8a psllh \$f22,\$f23,\$f24
  546. +.*: 4b1bd64a psllw \$f25,\$f26,\$f27
  547. +.*: 4b7eef0b psrah \$f28,\$f29,\$f30
  548. +.*: 4b42080b psraw \$f0,\$f1,\$f2
  549. +.*: 4b2520cb psrlh \$f3,\$f4,\$f5
  550. +.*: 4b08398b psrlw \$f6,\$f7,\$f8
  551. +.*: 4bcb5241 psubb \$f9,\$f10,\$f11
  552. +.*: 4b4e6b01 psubh \$f12,\$f13,\$f14
  553. +.*: 4b7183c1 psubw \$f15,\$f16,\$f17
  554. +.*: 4bf49c81 psubd \$f18,\$f19,\$f20
  555. +.*: 4b97b541 psubsb \$f21,\$f22,\$f23
  556. +.*: 4b1ace01 psubsh \$f24,\$f25,\$f26
  557. +.*: 4bbde6c1 psubusb \$f27,\$f28,\$f29
  558. +.*: 4b220801 psubush \$f0,\$f1,\$f2
  559. +.*: 4b6520c3 punpckhbh \$f3,\$f4,\$f5
  560. +.*: 4b283983 punpckhhw \$f6,\$f7,\$f8
  561. +.*: 4bab524b punpckhwd \$f9,\$f10,\$f11
  562. +.*: 4b4e6b03 punpcklbh \$f12,\$f13,\$f14
  563. +.*: 4b1183c3 punpcklhw \$f15,\$f16,\$f17
  564. +.*: 4b949c8b punpcklwd \$f18,\$f19,\$f20
  565. +
  566. +[0-9a-f]+ <fixed_point_insns>:
  567. +.*: 4b42080c add \$f0,\$f1,\$f2
  568. +.*: 4b0520cc addu \$f3,\$f4,\$f5
  569. +.*: 4b68398c dadd \$f6,\$f7,\$f8
  570. +.*: 4b4b524d sub \$f9,\$f10,\$f11
  571. +.*: 4b0e6b0d subu \$f12,\$f13,\$f14
  572. +.*: 4b7183cd dsub \$f15,\$f16,\$f17
  573. +.*: 4b349c8c or \$f18,\$f19,\$f20
  574. +.*: 4b17b54e sll \$f21,\$f22,\$f23
  575. +.*: 4b3ace0e dsll \$f24,\$f25,\$f26
  576. +.*: 4b9de6c2 xor \$f27,\$f28,\$f29
  577. +.*: 4ba20802 nor \$f0,\$f1,\$f2
  578. +.*: 4bc520c2 and \$f3,\$f4,\$f5
  579. +.*: 4b08398f srl \$f6,\$f7,\$f8
  580. +.*: 4b2b524f dsrl \$f9,\$f10,\$f11
  581. +.*: 4b4e6b0f sra \$f12,\$f13,\$f14
  582. +.*: 4b7183cf dsra \$f15,\$f16,\$f17
  583. +.*: 4b93900c sequ \$f18,\$f19
  584. +.*: 4b95a00d sltu \$f20,\$f21
  585. +.*: 4b97b00e sleu \$f22,\$f23
  586. +.*: 4bb9c00c seq \$f24,\$f25
  587. +.*: 4bbbd00d slt \$f26,\$f27
  588. +.*: 4bbde00e sle \$f28,\$f29
  589. +#pass
  590. diff --git a/gas/testsuite/gas/mips/loongson-2f-mmi.s b/gas/testsuite/gas/mips/loongson-2f-mmi.s
  591. new file mode 100644
  592. index 0000000..e87d66e
  593. --- /dev/null
  594. +++ b/gas/testsuite/gas/mips/loongson-2f-mmi.s
  595. @@ -0,0 +1,86 @@
  596. + .text
  597. + .set noreorder
  598. +
  599. +simd_insns:
  600. + packsshb $f0, $f1, $f2
  601. + packsswh $f3, $f4, $f5
  602. + packushb $f6, $f7, $f8
  603. + paddb $f9, $f10, $f11
  604. + paddh $f12, $f13, $f14
  605. + paddw $f15, $f16, $f17
  606. + paddd $f18, $f19, $f20
  607. + paddsb $f21, $f22, $f23
  608. + paddsh $f24, $f25, $f26
  609. + paddusb $f27, $f28, $f29
  610. + paddush $f0, $f1, $f2
  611. + pandn $f3, $f4, $f5
  612. + pavgb $f6, $f7, $f8
  613. + pavgh $f9, $f10, $f11
  614. + pcmpeqb $f12, $f13, $f14
  615. + pcmpeqh $f15, $f16, $f17
  616. + pcmpeqw $f18, $f19, $f20
  617. + pcmpgtb $f21, $f22, $f23
  618. + pcmpgth $f24, $f25, $f26
  619. + pcmpgtw $f27, $f28, $f29
  620. + pextrh $f0, $f1, $f2
  621. + pinsrh_0 $f3, $f4, $f5
  622. + pinsrh_1 $f6, $f7, $f8
  623. + pinsrh_2 $f9, $f10, $f11
  624. + pinsrh_3 $f12, $f13, $f14
  625. + pmaddhw $f15, $f16, $f17
  626. + pmaxsh $f18, $f19, $f20
  627. + pmaxub $f21, $f22, $f23
  628. + pminsh $f24, $f25, $f26
  629. + pminub $f27, $f28, $f29
  630. + pmovmskb $f0, $f1
  631. + pmulhuh $f2, $f3, $f4
  632. + pmulhh $f5, $f6, $f7
  633. + pmullh $f8, $f9, $f10
  634. + pmuluw $f11, $f12, $f13
  635. + pasubub $f14, $f15, $f16
  636. + biadd $f17, $f18
  637. + pshufh $f19, $f20, $f21
  638. + psllh $f22, $f23, $f24
  639. + psllw $f25, $f26, $f27
  640. + psrah $f28, $f29, $f30
  641. + psraw $f0, $f1, $f2
  642. + psrlh $f3, $f4, $f5
  643. + psrlw $f6, $f7, $f8
  644. + psubb $f9, $f10, $f11
  645. + psubh $f12, $f13, $f14
  646. + psubw $f15, $f16, $f17
  647. + psubd $f18, $f19, $f20
  648. + psubsb $f21, $f22, $f23
  649. + psubsh $f24, $f25, $f26
  650. + psubusb $f27, $f28, $f29
  651. + psubush $f0, $f1, $f2
  652. + punpckhbh $f3, $f4, $f5
  653. + punpckhhw $f6, $f7, $f8
  654. + punpckhwd $f9, $f10, $f11
  655. + punpcklbh $f12, $f13, $f14
  656. + punpcklhw $f15, $f16, $f17
  657. + punpcklwd $f18, $f19, $f20
  658. +
  659. +fixed_point_insns:
  660. + add $f0, $f1, $f2
  661. + addu $f3, $f4, $f5
  662. + dadd $f6, $f7, $f8
  663. + sub $f9, $f10, $f11
  664. + subu $f12, $f13, $f14
  665. + dsub $f15, $f16, $f17
  666. + or $f18, $f19, $f20
  667. + sll $f21, $f22, $f23
  668. + dsll $f24, $f25, $f26
  669. + xor $f27, $f28, $f29
  670. + nor $f0, $f1, $f2
  671. + and $f3, $f4, $f5
  672. + srl $f6, $f7, $f8
  673. + dsrl $f9, $f10, $f11
  674. + sra $f12, $f13, $f14
  675. + dsra $f15, $f16, $f17
  676. + sequ $f18, $f19
  677. + sltu $f20, $f21
  678. + sleu $f22, $f23
  679. + seq $f24, $f25
  680. + slt $f26, $f27
  681. + sle $f28, $f29
  682. diff --git a/gas/testsuite/gas/mips/loongson-2f.d b/gas/testsuite/gas/mips/loongson-2f.d
  683. index 8d1d8f7..4bd8f15 100644
  684. --- a/gas/testsuite/gas/mips/loongson-2f.d
  685. +++ b/gas/testsuite/gas/mips/loongson-2f.d
  686. @@ -39,91 +39,7 @@ Disassembly of section .text:
  687. .*: 7222081b nmsub.d \$f0,\$f1,\$f2
  688. .*: 72c520db nmsub.ps \$f3,\$f4,\$f5
  689.  
  690. -[0-9a-f]+ <simd_insns>:
  691. -.*: 4b420802 packsshb \$f0,\$f1,\$f2
  692. -.*: 4b2520c2 packsswh \$f3,\$f4,\$f5
  693. -.*: 4b683982 packushb \$f6,\$f7,\$f8
  694. -.*: 4bcb5240 paddb \$f9,\$f10,\$f11
  695. -.*: 4b4e6b00 paddh \$f12,\$f13,\$f14
  696. -.*: 4b7183c0 paddw \$f15,\$f16,\$f17
  697. -.*: 4bf49c80 paddd \$f18,\$f19,\$f20
  698. -.*: 4b97b540 paddsb \$f21,\$f22,\$f23
  699. -.*: 4b1ace00 paddsh \$f24,\$f25,\$f26
  700. -.*: 4bbde6c0 paddusb \$f27,\$f28,\$f29
  701. -.*: 4b220800 paddush \$f0,\$f1,\$f2
  702. -.*: 4be520c2 pandn \$f3,\$f4,\$f5
  703. -.*: 4b283988 pavgb \$f6,\$f7,\$f8
  704. -.*: 4b0b5248 pavgh \$f9,\$f10,\$f11
  705. -.*: 4b8e6b09 pcmpeqb \$f12,\$f13,\$f14
  706. -.*: 4b5183c9 pcmpeqh \$f15,\$f16,\$f17
  707. -.*: 4b149c89 pcmpeqw \$f18,\$f19,\$f20
  708. -.*: 4bb7b549 pcmpgtb \$f21,\$f22,\$f23
  709. -.*: 4b7ace09 pcmpgth \$f24,\$f25,\$f26
  710. -.*: 4b3de6c9 pcmpgtw \$f27,\$f28,\$f29
  711. -.*: 4b42080e pextrh \$f0,\$f1,\$f2
  712. -.*: 4b8520c3 pinsrh_0 \$f3,\$f4,\$f5
  713. -.*: 4ba83983 pinsrh_1 \$f6,\$f7,\$f8
  714. -.*: 4bcb5243 pinsrh_2 \$f9,\$f10,\$f11
  715. -.*: 4bee6b03 pinsrh_3 \$f12,\$f13,\$f14
  716. -.*: 4b7183ce pmaddhw \$f15,\$f16,\$f17
  717. -.*: 4b549c88 pmaxsh \$f18,\$f19,\$f20
  718. -.*: 4b97b548 pmaxub \$f21,\$f22,\$f23
  719. -.*: 4b7ace08 pminsh \$f24,\$f25,\$f26
  720. -.*: 4bbde6c8 pminub \$f27,\$f28,\$f29
  721. -.*: 4ba0080f pmovmskb \$f0,\$f1
  722. -.*: 4ba4188a pmulhuh \$f2,\$f3,\$f4
  723. -.*: 4b67314a pmulhh \$f5,\$f6,\$f7
  724. -.*: 4b4a4a0a pmullh \$f8,\$f9,\$f10
  725. -.*: 4b8d62ca pmuluw \$f11,\$f12,\$f13
  726. -.*: 4b307b8d pasubub \$f14,\$f15,\$f16
  727. -.*: 4b80944f biadd \$f17,\$f18
  728. -.*: 4b15a4c2 pshufh \$f19,\$f20,\$f21
  729. -.*: 4b38bd8a psllh \$f22,\$f23,\$f24
  730. -.*: 4b1bd64a psllw \$f25,\$f26,\$f27
  731. -.*: 4b7eef0b psrah \$f28,\$f29,\$f30
  732. -.*: 4b42080b psraw \$f0,\$f1,\$f2
  733. -.*: 4b2520cb psrlh \$f3,\$f4,\$f5
  734. -.*: 4b08398b psrlw \$f6,\$f7,\$f8
  735. -.*: 4bcb5241 psubb \$f9,\$f10,\$f11
  736. -.*: 4b4e6b01 psubh \$f12,\$f13,\$f14
  737. -.*: 4b7183c1 psubw \$f15,\$f16,\$f17
  738. -.*: 4bf49c81 psubd \$f18,\$f19,\$f20
  739. -.*: 4b97b541 psubsb \$f21,\$f22,\$f23
  740. -.*: 4b1ace01 psubsh \$f24,\$f25,\$f26
  741. -.*: 4bbde6c1 psubusb \$f27,\$f28,\$f29
  742. -.*: 4b220801 psubush \$f0,\$f1,\$f2
  743. -.*: 4b6520c3 punpckhbh \$f3,\$f4,\$f5
  744. -.*: 4b283983 punpckhhw \$f6,\$f7,\$f8
  745. -.*: 4bab524b punpckhwd \$f9,\$f10,\$f11
  746. -.*: 4b4e6b03 punpcklbh \$f12,\$f13,\$f14
  747. -.*: 4b1183c3 punpcklhw \$f15,\$f16,\$f17
  748. -.*: 4b949c8b punpcklwd \$f18,\$f19,\$f20
  749. -
  750. -[0-9a-f]+ <fixed_point_insns>:
  751. -.*: 4b42080c add \$f0,\$f1,\$f2
  752. -.*: 4b0520cc addu \$f3,\$f4,\$f5
  753. -.*: 4b68398c dadd \$f6,\$f7,\$f8
  754. -.*: 4b4b524d sub \$f9,\$f10,\$f11
  755. -.*: 4b0e6b0d subu \$f12,\$f13,\$f14
  756. -.*: 4b7183cd dsub \$f15,\$f16,\$f17
  757. -.*: 4b349c8c or \$f18,\$f19,\$f20
  758. -.*: 4b17b54e sll \$f21,\$f22,\$f23
  759. -.*: 4b3ace0e dsll \$f24,\$f25,\$f26
  760. -.*: 4b9de6c2 xor \$f27,\$f28,\$f29
  761. -.*: 4ba20802 nor \$f0,\$f1,\$f2
  762. -.*: 4bc520c2 and \$f3,\$f4,\$f5
  763. -.*: 4b08398f srl \$f6,\$f7,\$f8
  764. -.*: 4b2b524f dsrl \$f9,\$f10,\$f11
  765. -.*: 4b4e6b0f sra \$f12,\$f13,\$f14
  766. -.*: 4b7183cf dsra \$f15,\$f16,\$f17
  767. -.*: 4b93900c sequ \$f18,\$f19
  768. -.*: 4b95a00d sltu \$f20,\$f21
  769. -.*: 4b97b00e sleu \$f22,\$f23
  770. -.*: 4bb9c00c seq \$f24,\$f25
  771. -.*: 4bbbd00d slt \$f26,\$f27
  772. -.*: 4bbde00e sle \$f28,\$f29
  773. -
  774. -000001ac <mips5_ps_insns>:
  775. +[0-9a-f]+ <mips5_ps_insns>:
  776. .*: 46c01005 abs.ps \$f0,\$f2
  777. .*: 46c62080 add.ps \$f2,\$f4,\$f6
  778. .*: 46ca4032 c.eq.ps \$f8,\$f10
  779. diff --git a/gas/testsuite/gas/mips/loongson-2f.s b/gas/testsuite/gas/mips/loongson-2f.s
  780. index 4b47a99..412b139 100644
  781. --- a/gas/testsuite/gas/mips/loongson-2f.s
  782. +++ b/gas/testsuite/gas/mips/loongson-2f.s
  783. @@ -34,90 +34,6 @@ fpu_insns:
  784. nmsub.d $f0, $f1, $f2
  785. nmsub.ps $f3, $f4, $f5
  786.  
  787. -simd_insns:
  788. - packsshb $f0, $f1, $f2
  789. - packsswh $f3, $f4, $f5
  790. - packushb $f6, $f7, $f8
  791. - paddb $f9, $f10, $f11
  792. - paddh $f12, $f13, $f14
  793. - paddw $f15, $f16, $f17
  794. - paddd $f18, $f19, $f20
  795. - paddsb $f21, $f22, $f23
  796. - paddsh $f24, $f25, $f26
  797. - paddusb $f27, $f28, $f29
  798. - paddush $f0, $f1, $f2
  799. - pandn $f3, $f4, $f5
  800. - pavgb $f6, $f7, $f8
  801. - pavgh $f9, $f10, $f11
  802. - pcmpeqb $f12, $f13, $f14
  803. - pcmpeqh $f15, $f16, $f17
  804. - pcmpeqw $f18, $f19, $f20
  805. - pcmpgtb $f21, $f22, $f23
  806. - pcmpgth $f24, $f25, $f26
  807. - pcmpgtw $f27, $f28, $f29
  808. - pextrh $f0, $f1, $f2
  809. - pinsrh_0 $f3, $f4, $f5
  810. - pinsrh_1 $f6, $f7, $f8
  811. - pinsrh_2 $f9, $f10, $f11
  812. - pinsrh_3 $f12, $f13, $f14
  813. - pmaddhw $f15, $f16, $f17
  814. - pmaxsh $f18, $f19, $f20
  815. - pmaxub $f21, $f22, $f23
  816. - pminsh $f24, $f25, $f26
  817. - pminub $f27, $f28, $f29
  818. - pmovmskb $f0, $f1
  819. - pmulhuh $f2, $f3, $f4
  820. - pmulhh $f5, $f6, $f7
  821. - pmullh $f8, $f9, $f10
  822. - pmuluw $f11, $f12, $f13
  823. - pasubub $f14, $f15, $f16
  824. - biadd $f17, $f18
  825. - pshufh $f19, $f20, $f21
  826. - psllh $f22, $f23, $f24
  827. - psllw $f25, $f26, $f27
  828. - psrah $f28, $f29, $f30
  829. - psraw $f0, $f1, $f2
  830. - psrlh $f3, $f4, $f5
  831. - psrlw $f6, $f7, $f8
  832. - psubb $f9, $f10, $f11
  833. - psubh $f12, $f13, $f14
  834. - psubw $f15, $f16, $f17
  835. - psubd $f18, $f19, $f20
  836. - psubsb $f21, $f22, $f23
  837. - psubsh $f24, $f25, $f26
  838. - psubusb $f27, $f28, $f29
  839. - psubush $f0, $f1, $f2
  840. - punpckhbh $f3, $f4, $f5
  841. - punpckhhw $f6, $f7, $f8
  842. - punpckhwd $f9, $f10, $f11
  843. - punpcklbh $f12, $f13, $f14
  844. - punpcklhw $f15, $f16, $f17
  845. - punpcklwd $f18, $f19, $f20
  846. -
  847. -fixed_point_insns:
  848. - add $f0, $f1, $f2
  849. - addu $f3, $f4, $f5
  850. - dadd $f6, $f7, $f8
  851. - sub $f9, $f10, $f11
  852. - subu $f12, $f13, $f14
  853. - dsub $f15, $f16, $f17
  854. - or $f18, $f19, $f20
  855. - sll $f21, $f22, $f23
  856. - dsll $f24, $f25, $f26
  857. - xor $f27, $f28, $f29
  858. - nor $f0, $f1, $f2
  859. - and $f3, $f4, $f5
  860. - srl $f6, $f7, $f8
  861. - dsrl $f9, $f10, $f11
  862. - sra $f12, $f13, $f14
  863. - dsra $f15, $f16, $f17
  864. - sequ $f18, $f19
  865. - sltu $f20, $f21
  866. - sleu $f22, $f23
  867. - seq $f24, $f25
  868. - slt $f26, $f27
  869. - sle $f28, $f29
  870. -
  871. mips5_ps_insns:
  872. abs.ps $f0, $f2
  873. add.ps $f2, $f4, $f6
  874. diff --git a/gas/testsuite/gas/mips/loongson-3a-2.d b/gas/testsuite/gas/mips/loongson-3a-2.d
  875. index 32fea2e..e80b98b 100644
  876. --- a/gas/testsuite/gas/mips/loongson-3a-2.d
  877. +++ b/gas/testsuite/gas/mips/loongson-3a-2.d
  878. @@ -7,10 +7,6 @@
  879. Disassembly of section .text:
  880.  
  881. [0-9a-f]+ <.text>:
  882. -.*: 70601075 campi \$2,\$3
  883. -.*: 70a02035 campv \$4,\$5
  884. -.*: 70e830b5 camwi \$6,\$7,\$8
  885. -.*: 714048f5 ramri \$9,\$10
  886. .*: 716c0026 gsle \$11,\$12
  887. .*: 71ae0027 gsgt \$13,\$14
  888. .*: c8622010 gslble \$2,\$3,\$4
  889. diff --git a/gas/testsuite/gas/mips/loongson-3a-mmi.d b/gas/testsuite/gas/mips/loongson-3a-mmi.d
  890. new file mode 100644
  891. index 0000000..3a52c5a
  892. --- /dev/null
  893. +++ b/gas/testsuite/gas/mips/loongson-3a-mmi.d
  894. @@ -0,0 +1,108 @@
  895. +#as: -march=loongson3a -mabi=o64
  896. +#objdump: -M reg-names=numeric -dp
  897. +#name: Loongson-3A MMI tests
  898. +
  899. +.*: file format .*
  900. +
  901. +private flags = .*
  902. +
  903. +MIPS ABI Flags Version: 0
  904. +ISA: .*
  905. +GPR size: .*
  906. +CPR1 size: .*
  907. +CPR2 size: .*
  908. +FP ABI: .*
  909. +ISA Extension: None
  910. +ASEs:
  911. + Loongson MMI ASE
  912. + Loongson CAM ASE
  913. + Loongson EXT ASE
  914. +FLAGS 1: .*
  915. +FLAGS 2: .*
  916. +
  917. +Disassembly of section .text:
  918. +
  919. +[0-9a-f]+ <simd_insns>:
  920. +.*: 4b420802 packsshb \$f0,\$f1,\$f2
  921. +.*: 4b2520c2 packsswh \$f3,\$f4,\$f5
  922. +.*: 4b683982 packushb \$f6,\$f7,\$f8
  923. +.*: 4bcb5240 paddb \$f9,\$f10,\$f11
  924. +.*: 4b4e6b00 paddh \$f12,\$f13,\$f14
  925. +.*: 4b7183c0 paddw \$f15,\$f16,\$f17
  926. +.*: 4bf49c80 paddd \$f18,\$f19,\$f20
  927. +.*: 4b97b540 paddsb \$f21,\$f22,\$f23
  928. +.*: 4b1ace00 paddsh \$f24,\$f25,\$f26
  929. +.*: 4bbde6c0 paddusb \$f27,\$f28,\$f29
  930. +.*: 4b220800 paddush \$f0,\$f1,\$f2
  931. +.*: 4be520c2 pandn \$f3,\$f4,\$f5
  932. +.*: 4b283988 pavgb \$f6,\$f7,\$f8
  933. +.*: 4b0b5248 pavgh \$f9,\$f10,\$f11
  934. +.*: 4b8e6b09 pcmpeqb \$f12,\$f13,\$f14
  935. +.*: 4b5183c9 pcmpeqh \$f15,\$f16,\$f17
  936. +.*: 4b149c89 pcmpeqw \$f18,\$f19,\$f20
  937. +.*: 4bb7b549 pcmpgtb \$f21,\$f22,\$f23
  938. +.*: 4b7ace09 pcmpgth \$f24,\$f25,\$f26
  939. +.*: 4b3de6c9 pcmpgtw \$f27,\$f28,\$f29
  940. +.*: 4b42080e pextrh \$f0,\$f1,\$f2
  941. +.*: 4b8520c3 pinsrh_0 \$f3,\$f4,\$f5
  942. +.*: 4ba83983 pinsrh_1 \$f6,\$f7,\$f8
  943. +.*: 4bcb5243 pinsrh_2 \$f9,\$f10,\$f11
  944. +.*: 4bee6b03 pinsrh_3 \$f12,\$f13,\$f14
  945. +.*: 4b7183ce pmaddhw \$f15,\$f16,\$f17
  946. +.*: 4b549c88 pmaxsh \$f18,\$f19,\$f20
  947. +.*: 4b97b548 pmaxub \$f21,\$f22,\$f23
  948. +.*: 4b7ace08 pminsh \$f24,\$f25,\$f26
  949. +.*: 4bbde6c8 pminub \$f27,\$f28,\$f29
  950. +.*: 4ba0080f pmovmskb \$f0,\$f1
  951. +.*: 4ba4188a pmulhuh \$f2,\$f3,\$f4
  952. +.*: 4b67314a pmulhh \$f5,\$f6,\$f7
  953. +.*: 4b4a4a0a pmullh \$f8,\$f9,\$f10
  954. +.*: 4b8d62ca pmuluw \$f11,\$f12,\$f13
  955. +.*: 4b307b8d pasubub \$f14,\$f15,\$f16
  956. +.*: 4b80944f biadd \$f17,\$f18
  957. +.*: 4b15a4c2 pshufh \$f19,\$f20,\$f21
  958. +.*: 4b38bd8a psllh \$f22,\$f23,\$f24
  959. +.*: 4b1bd64a psllw \$f25,\$f26,\$f27
  960. +.*: 4b7eef0b psrah \$f28,\$f29,\$f30
  961. +.*: 4b42080b psraw \$f0,\$f1,\$f2
  962. +.*: 4b2520cb psrlh \$f3,\$f4,\$f5
  963. +.*: 4b08398b psrlw \$f6,\$f7,\$f8
  964. +.*: 4bcb5241 psubb \$f9,\$f10,\$f11
  965. +.*: 4b4e6b01 psubh \$f12,\$f13,\$f14
  966. +.*: 4b7183c1 psubw \$f15,\$f16,\$f17
  967. +.*: 4bf49c81 psubd \$f18,\$f19,\$f20
  968. +.*: 4b97b541 psubsb \$f21,\$f22,\$f23
  969. +.*: 4b1ace01 psubsh \$f24,\$f25,\$f26
  970. +.*: 4bbde6c1 psubusb \$f27,\$f28,\$f29
  971. +.*: 4b220801 psubush \$f0,\$f1,\$f2
  972. +.*: 4b6520c3 punpckhbh \$f3,\$f4,\$f5
  973. +.*: 4b283983 punpckhhw \$f6,\$f7,\$f8
  974. +.*: 4bab524b punpckhwd \$f9,\$f10,\$f11
  975. +.*: 4b4e6b03 punpcklbh \$f12,\$f13,\$f14
  976. +.*: 4b1183c3 punpcklhw \$f15,\$f16,\$f17
  977. +.*: 4b949c8b punpcklwd \$f18,\$f19,\$f20
  978. +
  979. +[0-9a-f]+ <fixed_point_insns>:
  980. +.*: 4b42080c add \$f0,\$f1,\$f2
  981. +.*: 4b0520cc addu \$f3,\$f4,\$f5
  982. +.*: 4b68398c dadd \$f6,\$f7,\$f8
  983. +.*: 4b4b524d sub \$f9,\$f10,\$f11
  984. +.*: 4b0e6b0d subu \$f12,\$f13,\$f14
  985. +.*: 4b7183cd dsub \$f15,\$f16,\$f17
  986. +.*: 4b349c8c or \$f18,\$f19,\$f20
  987. +.*: 4b17b54e sll \$f21,\$f22,\$f23
  988. +.*: 4b3ace0e dsll \$f24,\$f25,\$f26
  989. +.*: 4b9de6c2 xor \$f27,\$f28,\$f29
  990. +.*: 4ba20802 nor \$f0,\$f1,\$f2
  991. +.*: 4bc520c2 and \$f3,\$f4,\$f5
  992. +.*: 4b08398f srl \$f6,\$f7,\$f8
  993. +.*: 4b2b524f dsrl \$f9,\$f10,\$f11
  994. +.*: 4b4e6b0f sra \$f12,\$f13,\$f14
  995. +.*: 4b7183cf dsra \$f15,\$f16,\$f17
  996. +.*: 4b93900c sequ \$f18,\$f19
  997. +.*: 4b95a00d sltu \$f20,\$f21
  998. +.*: 4b97b00e sleu \$f22,\$f23
  999. +.*: 4bb9c00c seq \$f24,\$f25
  1000. +.*: 4bbbd00d slt \$f26,\$f27
  1001. +.*: 4bbde00e sle \$f28,\$f29
  1002. +#pass
  1003. diff --git a/gas/testsuite/gas/mips/loongson-3a-mmi.s b/gas/testsuite/gas/mips/loongson-3a-mmi.s
  1004. new file mode 100644
  1005. index 0000000..e87d66e
  1006. --- /dev/null
  1007. +++ b/gas/testsuite/gas/mips/loongson-3a-mmi.s
  1008. @@ -0,0 +1,86 @@
  1009. + .text
  1010. + .set noreorder
  1011. +
  1012. +simd_insns:
  1013. + packsshb $f0, $f1, $f2
  1014. + packsswh $f3, $f4, $f5
  1015. + packushb $f6, $f7, $f8
  1016. + paddb $f9, $f10, $f11
  1017. + paddh $f12, $f13, $f14
  1018. + paddw $f15, $f16, $f17
  1019. + paddd $f18, $f19, $f20
  1020. + paddsb $f21, $f22, $f23
  1021. + paddsh $f24, $f25, $f26
  1022. + paddusb $f27, $f28, $f29
  1023. + paddush $f0, $f1, $f2
  1024. + pandn $f3, $f4, $f5
  1025. + pavgb $f6, $f7, $f8
  1026. + pavgh $f9, $f10, $f11
  1027. + pcmpeqb $f12, $f13, $f14
  1028. + pcmpeqh $f15, $f16, $f17
  1029. + pcmpeqw $f18, $f19, $f20
  1030. + pcmpgtb $f21, $f22, $f23
  1031. + pcmpgth $f24, $f25, $f26
  1032. + pcmpgtw $f27, $f28, $f29
  1033. + pextrh $f0, $f1, $f2
  1034. + pinsrh_0 $f3, $f4, $f5
  1035. + pinsrh_1 $f6, $f7, $f8
  1036. + pinsrh_2 $f9, $f10, $f11
  1037. + pinsrh_3 $f12, $f13, $f14
  1038. + pmaddhw $f15, $f16, $f17
  1039. + pmaxsh $f18, $f19, $f20
  1040. + pmaxub $f21, $f22, $f23
  1041. + pminsh $f24, $f25, $f26
  1042. + pminub $f27, $f28, $f29
  1043. + pmovmskb $f0, $f1
  1044. + pmulhuh $f2, $f3, $f4
  1045. + pmulhh $f5, $f6, $f7
  1046. + pmullh $f8, $f9, $f10
  1047. + pmuluw $f11, $f12, $f13
  1048. + pasubub $f14, $f15, $f16
  1049. + biadd $f17, $f18
  1050. + pshufh $f19, $f20, $f21
  1051. + psllh $f22, $f23, $f24
  1052. + psllw $f25, $f26, $f27
  1053. + psrah $f28, $f29, $f30
  1054. + psraw $f0, $f1, $f2
  1055. + psrlh $f3, $f4, $f5
  1056. + psrlw $f6, $f7, $f8
  1057. + psubb $f9, $f10, $f11
  1058. + psubh $f12, $f13, $f14
  1059. + psubw $f15, $f16, $f17
  1060. + psubd $f18, $f19, $f20
  1061. + psubsb $f21, $f22, $f23
  1062. + psubsh $f24, $f25, $f26
  1063. + psubusb $f27, $f28, $f29
  1064. + psubush $f0, $f1, $f2
  1065. + punpckhbh $f3, $f4, $f5
  1066. + punpckhhw $f6, $f7, $f8
  1067. + punpckhwd $f9, $f10, $f11
  1068. + punpcklbh $f12, $f13, $f14
  1069. + punpcklhw $f15, $f16, $f17
  1070. + punpcklwd $f18, $f19, $f20
  1071. +
  1072. +fixed_point_insns:
  1073. + add $f0, $f1, $f2
  1074. + addu $f3, $f4, $f5
  1075. + dadd $f6, $f7, $f8
  1076. + sub $f9, $f10, $f11
  1077. + subu $f12, $f13, $f14
  1078. + dsub $f15, $f16, $f17
  1079. + or $f18, $f19, $f20
  1080. + sll $f21, $f22, $f23
  1081. + dsll $f24, $f25, $f26
  1082. + xor $f27, $f28, $f29
  1083. + nor $f0, $f1, $f2
  1084. + and $f3, $f4, $f5
  1085. + srl $f6, $f7, $f8
  1086. + dsrl $f9, $f10, $f11
  1087. + sra $f12, $f13, $f14
  1088. + dsra $f15, $f16, $f17
  1089. + sequ $f18, $f19
  1090. + sltu $f20, $f21
  1091. + sleu $f22, $f23
  1092. + seq $f24, $f25
  1093. + slt $f26, $f27
  1094. + sle $f28, $f29
  1095. diff --git a/gas/testsuite/gas/mips/loongson-cam.d b/gas/testsuite/gas/mips/loongson-cam.d
  1096. new file mode 100644
  1097. index 0000000..ae973ea
  1098. --- /dev/null
  1099. +++ b/gas/testsuite/gas/mips/loongson-cam.d
  1100. @@ -0,0 +1,27 @@
  1101. +#as: -mloongson-cam -mabi=64
  1102. +#objdump: -M reg-names=numeric -M loongson-cam -dp
  1103. +#name: Loongson CAM tests
  1104. +
  1105. +.*: file format .*
  1106. +
  1107. +private flags = .*
  1108. +
  1109. +MIPS ABI Flags Version: 0
  1110. +ISA: .*
  1111. +GPR size: .*
  1112. +CPR1 size: .*
  1113. +CPR2 size: .*
  1114. +FP ABI: .*
  1115. +ISA Extension: None
  1116. +ASEs:
  1117. + Loongson CAM ASE
  1118. +FLAGS 1: .*
  1119. +FLAGS 2: .*
  1120. +
  1121. +Disassembly of section .text:
  1122. +
  1123. +[0-9a-f]+ <.text>:
  1124. +.*: 70601075 campi \$2,\$3
  1125. +.*: 70a02035 campv \$4,\$5
  1126. +.*: 70e830b5 camwi \$6,\$7,\$8
  1127. +.*: 714048f5 ramri \$9,\$10
  1128. diff --git a/gas/testsuite/gas/mips/loongson-cam.s b/gas/testsuite/gas/mips/loongson-cam.s
  1129. new file mode 100644
  1130. index 0000000..688e9d4
  1131. --- /dev/null
  1132. +++ b/gas/testsuite/gas/mips/loongson-cam.s
  1133. @@ -0,0 +1,7 @@
  1134. + .text
  1135. + .set noreorder
  1136. +
  1137. + campi $2,$3
  1138. + campv $4,$5
  1139. + camwi $6,$7,$8
  1140. + ramri $9,$10
  1141. diff --git a/gas/testsuite/gas/mips/loongson-ext2.d b/gas/testsuite/gas/mips/loongson-ext2.d
  1142. new file mode 100644
  1143. index 0000000..d821386
  1144. --- /dev/null
  1145. +++ b/gas/testsuite/gas/mips/loongson-ext2.d
  1146. @@ -0,0 +1,28 @@
  1147. +#as: -mloongson-ext2 -mabi=64
  1148. +#objdump: -M reg-names=numeric -M loongson-ext2 -dp
  1149. +#name: Loongson EXT2 tests
  1150. +
  1151. +.*: file format .*
  1152. +
  1153. +private flags = .*
  1154. +
  1155. +MIPS ABI Flags Version: 0
  1156. +ISA: .*
  1157. +GPR size: .*
  1158. +CPR1 size: .*
  1159. +CPR2 size: .*
  1160. +FP ABI: .*
  1161. +ISA Extension: None
  1162. +ASEs:
  1163. + Loongson EXT ASE
  1164. + Loongson EXT2 ASE
  1165. +FLAGS 1: .*
  1166. +FLAGS 2: .*
  1167. +
  1168. +Disassembly of section .text:
  1169. +
  1170. +[0-9a-f]+ <.text>:
  1171. +.*: 70801062 cto \$2,\$4
  1172. +.*: 70801022 ctz \$2,\$4
  1173. +.*: 708010e2 dcto \$2,\$4
  1174. +.*: 708010a2 dctz \$2,\$4
  1175. diff --git a/gas/testsuite/gas/mips/loongson-ext2.s b/gas/testsuite/gas/mips/loongson-ext2.s
  1176. new file mode 100644
  1177. index 0000000..023a469
  1178. --- /dev/null
  1179. +++ b/gas/testsuite/gas/mips/loongson-ext2.s
  1180. @@ -0,0 +1,7 @@
  1181. + .text
  1182. + .set noreorder
  1183. +
  1184. + cto $2,$4
  1185. + ctz $2,$4
  1186. + dcto $2,$4
  1187. + dctz $2,$4
  1188. diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
  1189. index 74c39d4..895c2b9 100644
  1190. --- a/gas/testsuite/gas/mips/mips.exp
  1191. +++ b/gas/testsuite/gas/mips/mips.exp
  1192. @@ -1385,6 +1385,12 @@ if { [istarget mips*-*-vxworks*] } {
  1193. run_dump_test "loongson-3a-2"
  1194. run_dump_test "loongson-3a-3"
  1195.  
  1196. + run_dump_test "loongson-2f-mmi"
  1197. + run_dump_test "loongson-3a-mmi"
  1198. +
  1199. + run_dump_test_arches "loongson-cam" [mips_arch_list_matching gs464]
  1200. + run_dump_test_arches "loongson-ext2" [mips_arch_list_matching gs464]
  1201. +
  1202. if { $has_newabi } {
  1203. run_dump_test_arches "octeon" [mips_arch_list_matching octeon]
  1204. }
  1205. diff --git a/gold/mips.cc b/gold/mips.cc
  1206. index 543a234..5795bd9 100644
  1207. --- a/gold/mips.cc
  1208. +++ b/gold/mips.cc
  1209. @@ -3984,7 +3984,9 @@ class Target_mips : public Sized_target<size, big_endian>
  1210. mach_mips5 = 5,
  1211. mach_mips_loongson_2e = 3001,
  1212. mach_mips_loongson_2f = 3002,
  1213. - mach_mips_loongson_3a = 3003,
  1214. + mach_mips_gs464 = 3003,
  1215. + mach_mips_gs464e = 3004,
  1216. + mach_mips_gs264e = 3005,
  1217. mach_mips_sb1 = 12310201, // octal 'SB', 01
  1218. mach_mips_octeon = 6501,
  1219. mach_mips_octeonp = 6601,
  1220. @@ -4150,7 +4152,9 @@ class Target_mips : public Sized_target<size, big_endian>
  1221. this->add_extension(mach_mips_octeon2, mach_mips_octeonp);
  1222. this->add_extension(mach_mips_octeonp, mach_mips_octeon);
  1223. this->add_extension(mach_mips_octeon, mach_mipsisa64r2);
  1224. - this->add_extension(mach_mips_loongson_3a, mach_mipsisa64r2);
  1225. + this->add_extension(mach_mips_gs264e, mach_mips_gs464e);
  1226. + this->add_extension(mach_mips_gs464e, mach_mips_gs464);
  1227. + this->add_extension(mach_mips_gs464, mach_mipsisa64r2);
  1228.  
  1229. // MIPS64 extensions.
  1230. this->add_extension(mach_mipsisa64r2, mach_mipsisa64);
  1231. @@ -8884,8 +8888,14 @@ Target_mips<size, big_endian>::elf_mips_mach(elfcpp::Elf_Word flags)
  1232. case elfcpp::E_MIPS_MACH_LS2F:
  1233. return mach_mips_loongson_2f;
  1234.  
  1235. - case elfcpp::E_MIPS_MACH_LS3A:
  1236. - return mach_mips_loongson_3a;
  1237. + case elfcpp::E_MIPS_MACH_GS464:
  1238. + return mach_mips_gs464;
  1239. +
  1240. + case elfcpp::E_MIPS_MACH_GS464E:
  1241. + return mach_mips_gs464e;
  1242. +
  1243. + case elfcpp::E_MIPS_MACH_GS264E:
  1244. + return mach_mips_gs264e;
  1245.  
  1246. case elfcpp::E_MIPS_MACH_OCTEON3:
  1247. return mach_mips_octeon3;
  1248. @@ -8985,9 +8995,6 @@ Target_mips<size, big_endian>::mips_isa_ext_mach(unsigned int isa_ext)
  1249. case elfcpp::AFL_EXT_LOONGSON_2F:
  1250. return mach_mips_loongson_2f;
  1251.  
  1252. - case elfcpp::AFL_EXT_LOONGSON_3A:
  1253. - return mach_mips_loongson_3a;
  1254. -
  1255. case elfcpp::AFL_EXT_SB1:
  1256. return mach_mips_sb1;
  1257.  
  1258. @@ -9052,9 +9059,6 @@ Target_mips<size, big_endian>::mips_isa_ext(unsigned int mips_mach)
  1259. case mach_mips_loongson_2f:
  1260. return elfcpp::AFL_EXT_LOONGSON_2F;
  1261.  
  1262. - case mach_mips_loongson_3a:
  1263. - return elfcpp::AFL_EXT_LOONGSON_3A;
  1264. -
  1265. case mach_mips_sb1:
  1266. return elfcpp::AFL_EXT_SB1;
  1267.  
  1268. @@ -9186,7 +9190,7 @@ Target_mips<size, big_endian>::infer_abiflags(
  1269. && abiflags->fp_abi != elfcpp::Val_GNU_MIPS_ABI_FP_SOFT
  1270. && abiflags->fp_abi != elfcpp::Val_GNU_MIPS_ABI_FP_64A
  1271. && abiflags->isa_level >= 32
  1272. - && abiflags->isa_ext != elfcpp::AFL_EXT_LOONGSON_3A)
  1273. + && abiflags->ases != elfcpp::AFL_ASE_LOONGSON_EXT)
  1274. abiflags->flags1 |= elfcpp::AFL_FLAGS1_ODDSPREG;
  1275. }
  1276.  
  1277. @@ -12556,8 +12560,12 @@ Target_mips<size, big_endian>::elf_mips_mach_name(elfcpp::Elf_Word e_flags)
  1278. return "mips:loongson_2e";
  1279. case elfcpp::E_MIPS_MACH_LS2F:
  1280. return "mips:loongson_2f";
  1281. - case elfcpp::E_MIPS_MACH_LS3A:
  1282. - return "mips:loongson_3a";
  1283. + case elfcpp::E_MIPS_MACH_GS464:
  1284. + return "mips:gs464";
  1285. + case elfcpp::E_MIPS_MACH_GS464E:
  1286. + return "mips:gs464e";
  1287. + case elfcpp::E_MIPS_MACH_GS264E:
  1288. + return "mips:gs264e";
  1289. case elfcpp::E_MIPS_MACH_OCTEON:
  1290. return "mips:octeon";
  1291. case elfcpp::E_MIPS_MACH_OCTEON2:
  1292. diff --git a/include/elf/mips.h b/include/elf/mips.h
  1293. index 9de0b4e..fd02955 100644
  1294. --- a/include/elf/mips.h
  1295. +++ b/include/elf/mips.h
  1296. @@ -299,7 +299,9 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
  1297. #define E_MIPS_MACH_9000 0x00990000
  1298. #define E_MIPS_MACH_LS2E 0x00A00000
  1299. #define E_MIPS_MACH_LS2F 0x00A10000
  1300. -#define E_MIPS_MACH_LS3A 0x00A20000
  1301. +#define E_MIPS_MACH_GS464 0x00A20000
  1302. +#define E_MIPS_MACH_GS464E 0x00A30000
  1303. +#define E_MIPS_MACH_GS264E 0x00A40000
  1305. /* Processor specific section indices. These sections do not actually
  1306. exist. Symbols with a st_shndx field corresponding to one of these
  1307. @@ -1235,14 +1237,17 @@ extern void bfd_mips_elf_swap_abiflags_v0_out
  1308. #define AFL_ASE_XPA 0x00001000 /* XPA ASE. */
  1309. #define AFL_ASE_DSPR3 0x00002000 /* DSP R3 ASE. */
  1310. #define AFL_ASE_MIPS16E2 0x00004000 /* MIPS16e2 ASE. */
  1311. -#define AFL_ASE_MASK 0x00007fff /* All ASEs. */
  1312. +#define AFL_ASE_LOONGSON_MMI 0x00040000 /* Loongson MMI ASE. */
  1313. +#define AFL_ASE_LOONGSON_CAM 0x00080000 /* Loongson CAM ASE. */
  1314. +#define AFL_ASE_LOONGSON_EXT 0x00100000 /* Loongson EXT instructions. */
  1315. +#define AFL_ASE_LOONGSON_EXT2 0x00200000 /* Loongson EXT2 instructions. */
  1316. +#define AFL_ASE_MASK 0x003effff /* All ASEs. */
  1317.  
  1318. /* Values for the isa_ext word of an ABI flags structure. */
  1319.  
  1320. #define AFL_EXT_XLR 1 /* RMI Xlr instruction. */
  1321. #define AFL_EXT_OCTEON2 2 /* Cavium Networks Octeon2. */
  1322. #define AFL_EXT_OCTEONP 3 /* Cavium Networks OcteonP. */
  1323. -#define AFL_EXT_LOONGSON_3A 4 /* Loongson 3A. */
  1324. #define AFL_EXT_OCTEON 5 /* Cavium Networks Octeon. */
  1325. #define AFL_EXT_5900 6 /* MIPS R5900 instruction. */
  1326. #define AFL_EXT_4650 7 /* MIPS R4650 instruction. */
  1327. diff --git a/include/opcode/mips.h b/include/opcode/mips.h
  1328. index a8036ab..2a32c1e 100644
  1329. --- a/include/opcode/mips.h
  1330. +++ b/include/opcode/mips.h
  1331. @@ -928,7 +928,7 @@ mips_opcode_32bit_p (const struct mips_opcode *mo)
  1332. "+S" Length-minus-one field of cins/exts. Requires msb position
  1333. of the field to be <= 63.
  1334.  
  1335. - Loongson-3A:
  1336. + Loongson-ext ASE:
  1337. "+a" 8-bit signed offset in bit 6 (OP_*_OFFSET_A)
  1338. "+b" 8-bit signed offset in bit 3 (OP_*_OFFSET_B)
  1339. "+c" 9-bit signed offset in bit 6 (OP_*_OFFSET_C)
  1340. @@ -1256,8 +1256,6 @@ static const unsigned int mips_isa_table[] = {
  1341. #define INSN_LOONGSON_2E 0x40000000
  1342. /* ST Microelectronics Loongson 2F. */
  1343. #define INSN_LOONGSON_2F 0x80000000
  1344. -/* Loongson 3A. */
  1345. -#define INSN_LOONGSON_3A 0x00000400
  1346. /* RMI Xlr instruction */
  1347. #define INSN_XLR 0x00000020
  1348. /* Imagination interAptiv MR2. */
  1349. @@ -1297,6 +1295,14 @@ static const unsigned int mips_isa_table[] = {
  1350. /* The Virtualization ASE has eXtended Physical Addressing (XPA)
  1351. instructions which are only valid when both ASEs are enabled. */
  1352. #define ASE_XPA_VIRT 0x00020000
  1353. +/* Loongson MultiMedia extensions Instructions (MMI). */
  1354. +#define ASE_LOONGSON_MMI 0x00200000
  1355. +/* Loongson Content Address Memory (CAM). */
  1356. +#define ASE_LOONGSON_CAM 0x00400000
  1357. +/* Loongson EXTensions (EXT) instructions. */
  1358. +#define ASE_LOONGSON_EXT 0x00800000
  1359. +/* Loongson EXTensions R2 (EXT2) instructions. */
  1360. +#define ASE_LOONGSON_EXT2 0x01000000
  1361.  
  1362. /* MIPS ISA defines, use instead of hardcoding ISA level. */
  1363.  
  1364. @@ -1361,7 +1367,9 @@ static const unsigned int mips_isa_table[] = {
  1365. #define CPU_SB1 12310201 /* octal 'SB', 01. */
  1366. #define CPU_LOONGSON_2E 3001
  1367. #define CPU_LOONGSON_2F 3002
  1368. -#define CPU_LOONGSON_3A 3003
  1369. +#define CPU_GS464 3003
  1370. +#define CPU_GS464E 3004
  1371. +#define CPU_GS264E 3005
  1372. #define CPU_OCTEON 6501
  1373. #define CPU_OCTEONP 6601
  1374. #define CPU_OCTEON2 6502
  1375. @@ -1420,9 +1428,6 @@ cpu_is_member (int cpu, unsigned int mask)
  1376. case CPU_LOONGSON_2F:
  1377. return (mask & INSN_LOONGSON_2F) != 0;
  1378.  
  1379. - case CPU_LOONGSON_3A:
  1380. - return (mask & INSN_LOONGSON_3A) != 0;
  1381. -
  1382. case CPU_OCTEON:
  1383. return (mask & INSN_OCTEON) != 0;
  1384.  
  1385. diff --git a/ld/testsuite/ld-mips-elf/mips-elf-flags.exp b/ld/testsuite/ld-mips-elf/mips-elf-flags.exp
  1386. index 654f8ae..b35d13a0 100644
  1387. --- a/ld/testsuite/ld-mips-elf/mips-elf-flags.exp
  1388. +++ b/ld/testsuite/ld-mips-elf/mips-elf-flags.exp
  1389. @@ -197,7 +197,7 @@ isa_conflict { "-march=sb1 -32" "-mips64r2 -32" } sb1 isa64r2
  1390. isa_conflict { "-march=vr4100 -32" "-march=r10000 -32" } 4100 8000
  1391. isa_conflict { "-march=r5900 -32" "-march=vr4111 -32" } 5900 4111
  1392. isa_conflict { "-march=loongson2e -32" "-march=loongson2f -32" } loongson_2e loongson_2f
  1393. -isa_conflict { "-march=loongson3a -32" "-march=loongson2f -32" } loongson_3a loongson_2f
  1394. +isa_conflict { "-march=gs464 -32" "-march=loongson2f -32" } gs464 loongson_2f
  1395.  
  1396. isa_conflict { "-march=interaptiv-mr2 -32" \
  1397. "-march=r4010 -32" } interaptiv-mr2 4010
  1398. @@ -270,3 +270,12 @@ good_combination { "-march=interaptiv-mr2 -32" "-march=m5100 -32" } \
  1399. { mips32r2 interaptiv-mr2 } \
  1400. MIPS32r5 "Imagination interAptiv MR2" \
  1401. { "DSP ASE" "Enhanced VA Scheme" "MT ASE" }
  1402. +
  1403. +good_combination { "-march=gs464 -32" "-march=gs464e -32" } \
  1404. + { gs464e o32 } \
  1405. + MIPS64r2 "None" \
  1406. + { "Loongson MMI ASE" "Loongson CAM ASE" "Loongson EXT ASE" "Loongson EXT2 ASE" }
  1407. +good_combination { "-march=gs264e -32" "-march=gs464e -32" } \
  1408. + { gs264e o32 } \
  1409. + MIPS64r2 "None" \
  1410. + { "Loongson MMI ASE" "Loongson CAM ASE" "Loongson EXT ASE" "Loongson EXT2 ASE" }
  1411. diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
  1412. index 984fcbb..5b9e173 100644
  1413. --- a/opcodes/mips-dis.c
  1414. +++ b/opcodes/mips-dis.c
  1415. @@ -625,12 +625,29 @@ const struct mips_arch_choice mips_arch_choices[] =
  1416. NULL, 0, mips_cp1_names_numeric, mips_hwr_names_numeric },
  1417.  
  1418. { "loongson2f", 1, bfd_mach_mips_loongson_2f, CPU_LOONGSON_2F,
  1419. - ISA_MIPS3 | INSN_LOONGSON_2F, 0, mips_cp0_names_numeric,
  1420. + ISA_MIPS3 | INSN_LOONGSON_2F, ASE_LOONGSON_MMI, mips_cp0_names_numeric,
  1421. NULL, 0, mips_cp1_names_numeric, mips_hwr_names_numeric },
  1422.  
  1423. - { "loongson3a", 1, bfd_mach_mips_loongson_3a, CPU_LOONGSON_3A,
  1424. - ISA_MIPS64R2 | INSN_LOONGSON_3A, 0, mips_cp0_names_numeric,
  1425. - NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric },
  1426. + /* The loongson3a is an alias of gs464 for compatibility */
  1427. + { "loongson3a", 1, bfd_mach_mips_gs464, CPU_GS464,
  1428. + ISA_MIPS64R2, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT,
  1429. + mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips3264,
  1430. + mips_hwr_names_numeric },
  1431. +
  1432. + { "g464", 1, bfd_mach_mips_gs464, CPU_GS464,
  1433. + ISA_MIPS64R2, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT,
  1434. + mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips3264,
  1435. + mips_hwr_names_numeric },
  1436. +
  1437. + { "g464e", 1, bfd_mach_mips_gs464e, CPU_GS464E,
  1438. + ISA_MIPS64R2, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT
  1439. + | ASE_LOONGSON_EXT2, mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips3264,
  1440. + mips_hwr_names_numeric },
  1441. +
  1442. + { "g264e", 1, bfd_mach_mips_gs464e, CPU_GS264E,
  1443. + ISA_MIPS64R2, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT
  1444. + | ASE_LOONGSON_EXT2 | ASE_MSA | ASE_MSA64, mips_cp0_names_numeric, NULL,
  1445. + 0, mips_cp1_names_mips3264, mips_hwr_names_numeric },
  1446.  
  1447. { "octeon", 1, bfd_mach_mips_octeon, CPU_OCTEON,
  1448. ISA_MIPS64R2 | INSN_OCTEON, 0, mips_cp0_names_numeric, NULL, 0,
  1449. @@ -928,6 +945,31 @@ parse_mips_ase_option (const char *option)
  1450. return TRUE;
  1451. }
  1452.  
  1453. + if (CONST_STRNEQ (option, "loongson-mmi"))
  1454. + {
  1455. + mips_ase |= ASE_LOONGSON_MMI;
  1456. + return TRUE;
  1457. + }
  1458. +
  1459. + if (CONST_STRNEQ (option, "loongson-cam"))
  1460. + {
  1461. + mips_ase |= ASE_LOONGSON_CAM;
  1462. + return TRUE;
  1463. + }
  1464. +
  1465. + /* Put here for match ext2 frist */
  1466. + if (CONST_STRNEQ (option, "loongson-ext2"))
  1467. + {
  1468. + mips_ase |= ASE_LOONGSON_EXT2;
  1469. + return TRUE;
  1470. + }
  1471. +
  1472. + if (CONST_STRNEQ (option, "loongson-ext"))
  1473. + {
  1474. + mips_ase |= ASE_LOONGSON_EXT;
  1475. + return TRUE;
  1476. + }
  1477. +
  1478. return FALSE;
  1479. }
  1480.  
  1481. @@ -2594,6 +2636,21 @@ with the -M switch (multiple options should be separated by commas):\n"));
  1482. specified architecture.\n"));
  1483.  
  1484. fprintf (stream, _("\n\
  1485. + loongson-mmi Recognize the Loongson MultiMedia extensions\n\
  1486. + Instructions (MMI) ASE instructions.\n"));
  1487. +
  1488. + fprintf (stream, _("\n\
  1489. + loongson-cam Recognize the Loongson Content Address Memory (CAM)\n\
  1490. + instructions.\n"));
  1491. +
  1492. + fprintf (stream, _("\n\
  1493. + loongson-ext Recognize the Loongson EXTensions (EXT)\n\
  1494. + instructions.\n"));
  1495. +
  1496. + fprintf (stream, _("\n\
  1497. + loongson-ext2 Recognize the Loongson EXTensions R2 (EXT2)\n\
  1498. + instructions.\n"));
  1499. + fprintf (stream, _("\n\
  1500. For the options above, the following values are supported for \"ABI\":\n\
  1501. "));
  1502. for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++)
  1503. diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
  1504. index 2f0c41d..4b891a1 100644
  1505. --- a/opcodes/mips-opc.c
  1506. +++ b/opcodes/mips-opc.c
  1507. @@ -307,7 +307,6 @@ decode_mips_operand (const char *p)
  1508.  
  1509. #define IL2E (INSN_LOONGSON_2E)
  1510. #define IL2F (INSN_LOONGSON_2F)
  1511. -#define IL3A (INSN_LOONGSON_3A)
  1512.  
  1513. #define P3 INSN_4650
  1514. #define L1 INSN_4010
  1515. @@ -406,6 +405,18 @@ decode_mips_operand (const char *p)
  1516. #define XPA ASE_XPA
  1517. #define XPAVZ ASE_XPA_VIRT
  1518.  
  1519. +/* Loongson MultiMedia extensions Instructions (MMI) support. */
  1520. +#define LMMI ASE_LOONGSON_MMI
  1521. +
  1522. +/* Loongson Content Address Memory (CAM) support. */
  1523. +#define LCAM ASE_LOONGSON_CAM
  1524. +
  1525. +/* Loongson EXTensions (EXT) instructions support. */
  1526. +#define LEXT ASE_LOONGSON_EXT
  1527. +
  1528. +/* Loongson EXTensions R2 (EXT2) instructions support. */
  1529. +#define LEXT2 ASE_LOONGSON_EXT2
  1530. +
  1531. /* The order of overloaded instructions matters. Label arguments and
  1532. register arguments look the same. Instructions that can have either
  1533. for arguments must apear in the correct order in this table for the
  1534. @@ -447,63 +458,67 @@ const struct mips_opcode mips_builtin_opcodes[] =
  1535. {"lapc", "s,-A", 0xec000000, 0xfc180000, WR_1, RD_pc, I37, 0, 0 },
  1536. {"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, 0, I1, 0, 0 },
  1537.  
  1538. -/* Loongson specific instructions. Loongson 3A redefines the Coprocessor 2
  1539. +/* Loongson specific instructions. Loongson gs464 (aka loongson3a) redefines the Coprocessor 2
  1540. instructions. Put them here so that disassembler will find them first.
  1541. The assemblers uses a hash table based on the instruction name anyhow. */
  1542. -{"campi", "d,s", 0x70000075, 0xfc1f07ff, WR_1|RD_2, 0, IL3A, 0, 0 },
  1543. -{"campv", "d,s", 0x70000035, 0xfc1f07ff, WR_1|RD_2, 0, IL3A, 0, 0 },
  1544. -{"camwi", "d,s,t", 0x700000b5, 0xfc0007ff, RD_1|RD_2|RD_3, 0, IL3A, 0, 0 },
  1545. -{"ramri", "d,s", 0x700000f5, 0xfc1f07ff, WR_1|RD_2, 0, IL3A, 0, 0 },
  1546. -{"gsle", "s,t", 0x70000026, 0xfc00ffff, RD_1|RD_2, 0, IL3A, 0, 0 },
  1547. -{"gsgt", "s,t", 0x70000027, 0xfc00ffff, RD_1|RD_2, 0, IL3A, 0, 0 },
  1548. -{"gslble", "t,b,d", 0xc8000010, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 },
  1549. -{"gslbgt", "t,b,d", 0xc8000011, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 },
  1550. -{"gslhle", "t,b,d", 0xc8000012, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 },
  1551. -{"gslhgt", "t,b,d", 0xc8000013, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 },
  1552. -{"gslwle", "t,b,d", 0xc8000014, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 },
  1553. -{"gslwgt", "t,b,d", 0xc8000015, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 },
  1554. -{"gsldle", "t,b,d", 0xc8000016, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 },
  1555. -{"gsldgt", "t,b,d", 0xc8000017, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 },
  1556. -{"gssble", "t,b,d", 0xe8000010, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 },
  1557. -{"gssbgt", "t,b,d", 0xe8000011, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 },
  1558. -{"gsshle", "t,b,d", 0xe8000012, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 },
  1559. -{"gsshgt", "t,b,d", 0xe8000013, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 },
  1560. -{"gsswle", "t,b,d", 0xe8000014, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 },
  1561. -{"gsswgt", "t,b,d", 0xe8000015, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 },
  1562. -{"gssdle", "t,b,d", 0xe8000016, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 },
  1563. -{"gssdgt", "t,b,d", 0xe8000017, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 },
  1564. -{"gslwlec1", "T,b,d", 0xc800001c, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 },
  1565. -{"gslwgtc1", "T,b,d", 0xc800001d, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 },
  1566. -{"gsldlec1", "T,b,d", 0xc800001e, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 },
  1567. -{"gsldgtc1", "T,b,d", 0xc800001f, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 },
  1568. -{"gsswlec1", "T,b,d", 0xe800001c, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 },
  1569. -{"gsswgtc1", "T,b,d", 0xe800001d, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 },
  1570. -{"gssdlec1", "T,b,d", 0xe800001e, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 },
  1571. -{"gssdgtc1", "T,b,d", 0xe800001f, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 },
  1572. -{"gslwlc1", "T,+a(b)", 0xc8000004, 0xfc00c03f, WR_1|RD_3|LM, 0, IL3A, 0, 0 },
  1573. -{"gslwrc1", "T,+a(b)", 0xc8000005, 0xfc00c03f, WR_1|RD_3|LM, 0, IL3A, 0, 0 },
  1574. -{"gsldlc1", "T,+a(b)", 0xc8000006, 0xfc00c03f, WR_1|RD_3|LM, 0, IL3A, 0, 0 },
  1575. -{"gsldrc1", "T,+a(b)", 0xc8000007, 0xfc00c03f, WR_1|RD_3|LM, 0, IL3A, 0, 0 },
  1576. -{"gsswlc1", "T,+a(b)", 0xe8000004, 0xfc00c03f, RD_1|RD_3|SM, 0, IL3A, 0, 0 },
  1577. -{"gsswrc1", "T,+a(b)", 0xe8000005, 0xfc00c03f, RD_1|RD_3|SM, 0, IL3A, 0, 0 },
  1578. -{"gssdlc1", "T,+a(b)", 0xe8000006, 0xfc00c03f, RD_1|RD_3|SM, 0, IL3A, 0, 0 },
  1579. -{"gssdrc1", "T,+a(b)", 0xe8000007, 0xfc00c03f, RD_1|RD_3|SM, 0, IL3A, 0, 0 },
  1580. -{"gslbx", "t,+b(b,d)", 0xd8000000, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, IL3A, 0, 0 },
  1581. -{"gslhx", "t,+b(b,d)", 0xd8000001, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, IL3A, 0, 0 },
  1582. -{"gslwx", "t,+b(b,d)", 0xd8000002, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, IL3A, 0, 0 },
  1583. -{"gsldx", "t,+b(b,d)", 0xd8000003, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, IL3A, 0, 0 },
  1584. -{"gssbx", "t,+b(b,d)", 0xf8000000, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, IL3A, 0, 0 },
  1585. -{"gsshx", "t,+b(b,d)", 0xf8000001, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, IL3A, 0, 0 },
  1586. -{"gsswx", "t,+b(b,d)", 0xf8000002, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, IL3A, 0, 0 },
  1587. -{"gssdx", "t,+b(b,d)", 0xf8000003, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, IL3A, 0, 0 },
  1588. -{"gslwxc1", "T,+b(b,d)", 0xd8000006, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, IL3A, 0, 0 },
  1589. -{"gsldxc1", "T,+b(b,d)", 0xd8000007, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, IL3A, 0, 0 },
  1590. -{"gsswxc1", "T,+b(b,d)", 0xf8000006, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, IL3A, 0, 0 },
  1591. -{"gssdxc1", "T,+b(b,d)", 0xf8000007, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, IL3A, 0, 0 },
  1592. -{"gslq", "+z,t,+c(b)", 0xc8000020, 0xfc008020, WR_1|WR_2|RD_4|LM, LMS, IL3A, 0, 0 },
  1593. -{"gssq", "+z,t,+c(b)", 0xe8000020, 0xfc008020, RD_1|RD_2|RD_4|SM, 0, IL3A, 0, 0 },
  1594. -{"gslqc1", "+Z,T,+c(b)", 0xc8008020, 0xfc008020, WR_1|WR_2|RD_4|LM, LMS, IL3A, 0, 0 },
  1595. -{"gssqc1", "+Z,T,+c(b)", 0xe8008020, 0xfc008020, RD_1|RD_2|RD_4|SM, 0, IL3A, 0, 0 },
  1596. +{"campi", "d,s", 0x70000075, 0xfc1f07ff, WR_1|RD_2, 0, 0, LCAM, 0 },
  1597. +{"campv", "d,s", 0x70000035, 0xfc1f07ff, WR_1|RD_2, 0, 0, LCAM, 0 },
  1598. +{"camwi", "d,s,t", 0x700000b5, 0xfc0007ff, RD_1|RD_2|RD_3, 0, 0, LCAM, 0 },
  1599. +{"ramri", "d,s", 0x700000f5, 0xfc1f07ff, WR_1|RD_2, 0, 0, LCAM, 0 },
  1600. +{"gsle", "s,t", 0x70000026, 0xfc00ffff, RD_1|RD_2, 0, 0, LEXT, 0 },
  1601. +{"gsgt", "s,t", 0x70000027, 0xfc00ffff, RD_1|RD_2, 0, 0, LEXT, 0 },
  1602. +{"gslble", "t,b,d", 0xc8000010, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 },
  1603. +{"gslbgt", "t,b,d", 0xc8000011, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 },
  1604. +{"gslhle", "t,b,d", 0xc8000012, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 },
  1605. +{"gslhgt", "t,b,d", 0xc8000013, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 },
  1606. +{"gslwle", "t,b,d", 0xc8000014, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 },
  1607. +{"gslwgt", "t,b,d", 0xc8000015, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 },
  1608. +{"gsldle", "t,b,d", 0xc8000016, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 },
  1609. +{"gsldgt", "t,b,d", 0xc8000017, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 },
  1610. +{"gssble", "t,b,d", 0xe8000010, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 },
  1611. +{"gssbgt", "t,b,d", 0xe8000011, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 },
  1612. +{"gsshle", "t,b,d", 0xe8000012, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 },
  1613. +{"gsshgt", "t,b,d", 0xe8000013, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 },
  1614. +{"gsswle", "t,b,d", 0xe8000014, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 },
  1615. +{"gsswgt", "t,b,d", 0xe8000015, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 },
  1616. +{"gssdle", "t,b,d", 0xe8000016, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 },
  1617. +{"gssdgt", "t,b,d", 0xe8000017, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 },
  1618. +{"gslwlec1", "T,b,d", 0xc8000018, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 },
  1619. +{"gslwgtc1", "T,b,d", 0xc8000019, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 },
  1620. +{"gsldlec1", "T,b,d", 0xc800001a, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 },
  1621. +{"gsldgtc1", "T,b,d", 0xc800001b, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 },
  1622. +{"gsswlec1", "T,b,d", 0xe800001c, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 },
  1623. +{"gsswgtc1", "T,b,d", 0xe800001d, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 },
  1624. +{"gssdlec1", "T,b,d", 0xe800001e, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 },
  1625. +{"gssdgtc1", "T,b,d", 0xe800001f, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 },
  1626. +{"gslwlc1", "T,+a(b)", 0xc8000004, 0xfc00c03f, WR_1|RD_3|LM, 0, 0, LEXT, 0 },
  1627. +{"gslwrc1", "T,+a(b)", 0xc8000005, 0xfc00c03f, WR_1|RD_3|LM, 0, 0, LEXT, 0 },
  1628. +{"gsldlc1", "T,+a(b)", 0xc8000006, 0xfc00c03f, WR_1|RD_3|LM, 0, 0, LEXT, 0 },
  1629. +{"gsldrc1", "T,+a(b)", 0xc8000007, 0xfc00c03f, WR_1|RD_3|LM, 0, 0, LEXT, 0 },
  1630. +{"gsswlc1", "T,+a(b)", 0xe8000004, 0xfc00c03f, RD_1|RD_3|SM, 0, 0, LEXT, 0 },
  1631. +{"gsswrc1", "T,+a(b)", 0xe8000005, 0xfc00c03f, RD_1|RD_3|SM, 0, 0, LEXT, 0 },
  1632. +{"gssdlc1", "T,+a(b)", 0xe8000006, 0xfc00c03f, RD_1|RD_3|SM, 0, 0, LEXT, 0 },
  1633. +{"gssdrc1", "T,+a(b)", 0xe8000007, 0xfc00c03f, RD_1|RD_3|SM, 0, 0, LEXT, 0 },
  1634. +{"gslbx", "t,+b(b,d)", 0xd8000000, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, 0, LEXT, 0 },
  1635. +{"gslhx", "t,+b(b,d)", 0xd8000001, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, 0, LEXT, 0 },
  1636. +{"gslwx", "t,+b(b,d)", 0xd8000002, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, 0, LEXT, 0 },
  1637. +{"gsldx", "t,+b(b,d)", 0xd8000003, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, 0, LEXT, 0 },
  1638. +{"gssbx", "t,+b(b,d)", 0xf8000000, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, 0, LEXT, 0 },
  1639. +{"gsshx", "t,+b(b,d)", 0xf8000001, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, 0, LEXT, 0 },
  1640. +{"gsswx", "t,+b(b,d)", 0xf8000002, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, 0, LEXT, 0 },
  1641. +{"gssdx", "t,+b(b,d)", 0xf8000003, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, 0, LEXT, 0 },
  1642. +{"gslwxc1", "T,+b(b,d)", 0xd8000006, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, 0, LEXT, 0 },
  1643. +{"gsldxc1", "T,+b(b,d)", 0xd8000007, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, 0, LEXT, 0 },
  1644. +{"gsswxc1", "T,+b(b,d)", 0xf8000006, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, 0, LEXT, 0 },
  1645. +{"gssdxc1", "T,+b(b,d)", 0xf8000007, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, 0, LEXT, 0 },
  1646. +{"gslq", "+z,t,+c(b)", 0xc8000020, 0xfc008020, WR_1|WR_2|RD_4|LM, 0, 0, LEXT, 0 },
  1647. +{"gssq", "+z,t,+c(b)", 0xe8000020, 0xfc008020, RD_1|RD_2|RD_4|SM, 0, 0, LEXT, 0 },
  1648. +{"gslqc1", "+Z,T,+c(b)", 0xc8008020, 0xfc008020, WR_1|WR_2|RD_4|LM, 0, 0, LEXT, 0 },
  1649. +{"gssqc1", "+Z,T,+c(b)", 0xe8008020, 0xfc008020, RD_1|RD_2|RD_4|SM, 0, 0, LEXT, 0 },
  1650. +{"cto", "d,s", 0x70000062, 0xfc1f07ff, WR_1|RD_2, 0, 0, LEXT2, 0 },
  1651. +{"ctz", "d,s", 0x70000022, 0xfc1f07ff, WR_1|RD_2, 0, 0, LEXT2, 0 },
  1652. +{"dcto", "d,s", 0x700000e2, 0xfc1f07ff, WR_1|RD_2, 0, 0, LEXT2, 0 },
  1653. +{"dctz", "d,s", 0x700000a2, 0xfc1f07ff, WR_1|RD_2, 0, 0, LEXT2, 0 },
  1654.  
  1655. /* R5900 VU0 Macromode instructions. */
  1656. {"vabs", "+7+K,+6+K", 0x4a0001fd, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
  1657. @@ -646,7 +661,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
  1658. {"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 },
  1659. {"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, 0, I1, 0, I37 },
  1660. {"add", "D,S,T", 0x45c00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2E, 0, 0 },
  1661. -{"add", "D,S,T", 0x4b40000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2F|IL3A, 0, 0 },
  1662. +{"add", "D,S,T", 0x4b40000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, 0, LMMI, 0 },
  1663. {"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I1, 0, 0 },
  1664. {"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, SF },
  1665. {"add.ob", "X,Y,Q", 0x7800000b, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 },
  1666. @@ -667,7 +682,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
  1667. {"addu", "d,v,t", 0x00000021, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 },
  1668. {"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, 0, I1, 0, 0 },
  1669. {"addu", "D,S,T", 0x45800000, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2E, 0, 0 },
  1670. -{"addu", "D,S,T", 0x4b00000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2F|IL3A, 0, 0 },
  1671. +{"addu", "D,S,T", 0x4b00000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, 0, LMMI, 0 },
  1672. {"alni.ob", "X,Y,Z,O", 0x78000018, 0xff00003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 },
  1673. {"alni.ob", "D,S,T,%", 0x48000018, 0xff00003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 },
  1674. {"alni.qh", "X,Y,Z,O", 0x7800001a, 0xff00003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 },
  1675. @@ -677,7 +692,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
  1676. {"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 },
  1677. {"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, 0, I1, 0, 0 },
  1678. {"and", "D,S,T", 0x47c00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  1679. -{"and", "D,S,T", 0x4bc00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  1680. +{"and", "D,S,T", 0x4bc00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  1681. {"and.ob", "X,Y,Q", 0x7800000c, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 },
  1682. {"and.ob", "D,S,Q", 0x4800000c, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 },
  1683. {"and.qh", "X,Y,Q", 0x7820000c, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 },
  1684. @@ -995,7 +1010,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
  1685. {"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 },
  1686. {"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, 0, I3, 0, I69 },
  1687. {"dadd", "D,S,T", 0x45e00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  1688. -{"dadd", "D,S,T", 0x4b60000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  1689. +{"dadd", "D,S,T", 0x4b60000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  1690. {"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_1|RD_2, 0, I3, 0, I69 },
  1691. {"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_1|RD_2, 0, I3, 0, 0 },
  1692. {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 },
  1693. @@ -1135,25 +1150,25 @@ const struct mips_opcode mips_builtin_opcodes[] =
  1694. {"dsll", "d,w,>", 0x0000003c, 0xffe0003f, WR_1|RD_2, 0, I3, 0, 0 }, /* dsll32 */
  1695. {"dsll", "d,w,<", 0x00000038, 0xffe0003f, WR_1|RD_2, 0, I3, 0, 0 },
  1696. {"dsll", "D,S,T", 0x45a00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  1697. -{"dsll", "D,S,T", 0x4b20000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  1698. +{"dsll", "D,S,T", 0x4b20000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  1699. {"dsrav", "d,t,s", 0x00000017, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 },
  1700. {"dsra32", "d,w,<", 0x0000003f, 0xffe0003f, WR_1|RD_2, 0, I3, 0, 0 },
  1701. {"dsra", "d,w,s", 0x00000017, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, /* dsrav */
  1702. {"dsra", "d,w,>", 0x0000003f, 0xffe0003f, WR_1|RD_2, 0, I3, 0, 0 }, /* dsra32 */
  1703. {"dsra", "d,w,<", 0x0000003b, 0xffe0003f, WR_1|RD_2, 0, I3, 0, 0 },
  1704. {"dsra", "D,S,T", 0x45e00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  1705. -{"dsra", "D,S,T", 0x4b60000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  1706. +{"dsra", "D,S,T", 0x4b60000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  1707. {"dsrlv", "d,t,s", 0x00000016, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 },
  1708. {"dsrl32", "d,w,<", 0x0000003e, 0xffe0003f, WR_1|RD_2, 0, I3, 0, 0 },
  1709. {"dsrl", "d,w,s", 0x00000016, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, /* dsrlv */
  1710. {"dsrl", "d,w,>", 0x0000003e, 0xffe0003f, WR_1|RD_2, 0, I3, 0, 0 }, /* dsrl32 */
  1711. {"dsrl", "d,w,<", 0x0000003a, 0xffe0003f, WR_1|RD_2, 0, I3, 0, 0 },
  1712. {"dsrl", "D,S,T", 0x45a00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  1713. -{"dsrl", "D,S,T", 0x4b20000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  1714. +{"dsrl", "D,S,T", 0x4b20000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  1715. {"dsub", "d,v,t", 0x0000002e, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 },
  1716. {"dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, 0, I3, 0, I69 },
  1717. {"dsub", "D,S,T", 0x45e00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  1718. -{"dsub", "D,S,T", 0x4b60000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  1719. +{"dsub", "D,S,T", 0x4b60000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  1720. {"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 },
  1721. {"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I3, 0, 0 },
  1722. {"dvpe", "", 0x41600001, 0xffffffff, TRAP, 0, 0, MT32, 0 },
  1723. @@ -1430,7 +1445,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
  1724. {"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_S, 0, I4_32, 0, I37 },
  1725. {"movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D, 0, I5_33, 0, I37 },
  1726. {"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I4_32|IL2E|IL2F|EE, 0, I37 },
  1727. -{"movnz", "d,v,t", 0x0000000b, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E|IL2F|IL3A, 0, 0 },
  1728. +{"movnz", "d,v,t", 0x0000000b, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E|IL2F, LEXT, 0 },
  1729. {"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_1|RD_2, 0, L1, 0, 0 },
  1730. {"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I4_32, 0, I37 },
  1731. {"movn.l", "D,S,t", 0x46a00013, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 },
  1732. @@ -1622,7 +1637,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
  1733. {"nor", "d,v,t", 0x00000027, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 },
  1734. {"nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO, 0, I1, 0, 0 },
  1735. {"nor", "D,S,T", 0x47a00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  1736. -{"nor", "D,S,T", 0x4ba00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  1737. +{"nor", "D,S,T", 0x4ba00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  1738. {"nor.ob", "X,Y,Q", 0x7800000f, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 },
  1739. {"nor.ob", "D,S,Q", 0x4800000f, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 },
  1740. {"nor.qh", "X,Y,Q", 0x7820000f, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 },
  1741. @@ -1630,7 +1645,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
  1742. {"or", "d,v,t", 0x00000025, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 },
  1743. {"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO, 0, I1, 0, 0 },
  1744. {"or", "D,S,T", 0x45a00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  1745. -{"or", "D,S,T", 0x4b20000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  1746. +{"or", "D,S,T", 0x4b20000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  1747. {"or.ob", "X,Y,Q", 0x7800000e, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 },
  1748. {"or.ob", "D,S,Q", 0x4800000e, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 },
  1749. {"or.qh", "X,Y,Q", 0x7820000e, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 },
  1750. @@ -1843,7 +1858,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
  1751. {"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO, 0, I1, 0, 0 },
  1752. {"seq", "d,v,I", 0, (int) M_SEQ_I, INSN_MACRO, 0, I1, 0, 0 },
  1753. {"seq", "S,T", 0x46a00032, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 },
  1754. -{"seq", "S,T", 0x4ba0000c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2F|IL3A, 0, 0 },
  1755. +{"seq", "S,T", 0x4ba0000c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, 0, LMMI, 0 },
  1756. {"seqi", "t,r,+Q", 0x7000002e, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 },
  1757. {"sge", "d,v,t", 0, (int) M_SGE, INSN_MACRO, 0, I1, 0, 0 },
  1758. {"sge", "d,v,I", 0, (int) M_SGE_I, INSN_MACRO, 0, I1, 0, 0 },
  1759. @@ -1873,29 +1888,29 @@ const struct mips_opcode mips_builtin_opcodes[] =
  1760. {"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO, 0, I1, 0, 0 },
  1761. {"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO, 0, I1, 0, 0 },
  1762. {"sle", "S,T", 0x46a0003e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 },
  1763. -{"sle", "S,T", 0x4ba0000e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2F|IL3A, 0, 0 },
  1764. +{"sle", "S,T", 0x4ba0000e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, 0, LMMI, 0 },
  1765. {"sleu", "d,v,t", 0, (int) M_SLEU, INSN_MACRO, 0, I1, 0, 0 },
  1766. {"sleu", "d,v,I", 0, (int) M_SLEU_I, INSN_MACRO, 0, I1, 0, 0 },
  1767. {"sleu", "S,T", 0x4680003e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 },
  1768. -{"sleu", "S,T", 0x4b80000e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2F|IL3A, 0, 0 },
  1769. +{"sleu", "S,T", 0x4b80000e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, 0, LMMI, 0 },
  1770. {"sllv", "d,t,s", 0x00000004, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 },
  1771. {"sll", "d,w,s", 0x00000004, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, /* sllv */
  1772. {"sll", "d,w,<", 0x00000000, 0xffe0003f, WR_1|RD_2, 0, I1, 0, 0 },
  1773. {"sll", "D,S,T", 0x45800002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  1774. -{"sll", "D,S,T", 0x4b00000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  1775. +{"sll", "D,S,T", 0x4b00000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  1776. {"sll.ob", "X,Y,Q", 0x78000010, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 },
  1777. {"sll.ob", "D,S,Q", 0x48000010, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 },
  1778. {"sll.qh", "X,Y,Q", 0x78200010, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 },
  1779. {"slt", "d,v,t", 0x0000002a, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 },
  1780. {"slt", "d,v,I", 0, (int) M_SLT_I, INSN_MACRO, 0, I1, 0, 0 },
  1781. {"slt", "S,T", 0x46a0003c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 },
  1782. -{"slt", "S,T", 0x4ba0000d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2F|IL3A, 0, 0 },
  1783. +{"slt", "S,T", 0x4ba0000d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, 0, LMMI, 0 },
  1784. {"slti", "t,r,j", 0x28000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, 0 },
  1785. {"sltiu", "t,r,j", 0x2c000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, 0 },
  1786. {"sltu", "d,v,t", 0x0000002b, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 },
  1787. {"sltu", "d,v,I", 0, (int) M_SLTU_I, INSN_MACRO, 0, I1, 0, 0 },
  1788. {"sltu", "S,T", 0x4680003c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 },
  1789. -{"sltu", "S,T", 0x4b80000d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2F|IL3A, 0, 0 },
  1790. +{"sltu", "S,T", 0x4b80000d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, 0, LMMI, 0 },
  1791. {"sne", "d,v,t", 0x7000002b, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IOCT, 0, 0 },
  1792. {"sne", "d,v,t", 0, (int) M_SNE, INSN_MACRO, 0, I1, 0, 0 },
  1793. {"sne", "d,v,I", 0, (int) M_SNE_I, INSN_MACRO, 0, I1, 0, 0 },
  1794. @@ -1911,13 +1926,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
  1795. {"sra", "d,w,s", 0x00000007, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, /* srav */
  1796. {"sra", "d,w,<", 0x00000003, 0xffe0003f, WR_1|RD_2, 0, I1, 0, 0 },
  1797. {"sra", "D,S,T", 0x45c00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  1798. -{"sra", "D,S,T", 0x4b40000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  1799. +{"sra", "D,S,T", 0x4b40000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  1800. {"sra.qh", "X,Y,Q", 0x78200013, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 },
  1801. {"srlv", "d,t,s", 0x00000006, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 },
  1802. {"srl", "d,w,s", 0x00000006, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, /* srlv */
  1803. {"srl", "d,w,<", 0x00000002, 0xffe0003f, WR_1|RD_2, 0, I1, 0, 0 },
  1804. {"srl", "D,S,T", 0x45800003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  1805. -{"srl", "D,S,T", 0x4b00000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  1806. +{"srl", "D,S,T", 0x4b00000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  1807. {"srl.ob", "X,Y,Q", 0x78000012, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 },
  1808. {"srl.ob", "D,S,Q", 0x48000012, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 },
  1809. {"srl.qh", "X,Y,Q", 0x78200012, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 },
  1810. @@ -1926,7 +1941,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
  1811. {"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 },
  1812. {"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, 0, I1, 0, I37 },
  1813. {"sub", "D,S,T", 0x45c00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2E, 0, 0 },
  1814. -{"sub", "D,S,T", 0x4b40000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2F|IL3A, 0, 0 },
  1815. +{"sub", "D,S,T", 0x4b40000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, 0, LMMI, 0 },
  1816. {"sub.d", "D,V,T", 0x46200001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, SF },
  1817. {"sub.s", "D,V,T", 0x46000001, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I1, 0, 0 },
  1818. {"sub.ob", "X,Y,Q", 0x7800000a, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 },
  1819. @@ -1942,7 +1957,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
  1820. {"subu", "d,v,t", 0x00000023, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 },
  1821. {"subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO, 0, I1, 0, 0 },
  1822. {"subu", "D,S,T", 0x45800001, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2E, 0, 0 },
  1823. -{"subu", "D,S,T", 0x4b00000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2F|IL3A, 0, 0 },
  1824. +{"subu", "D,S,T", 0x4b00000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, 0, LMMI, 0 },
  1825. {"suspend", "", 0x42000022, 0xffffffff, 0, 0, V1, 0, 0 },
  1826. {"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D, 0, I5_33|N55, 0, I37},
  1827. {"sw", "t,o(b)", 0xac000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, 0 },
  1828. @@ -2063,7 +2078,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
  1829. {"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 },
  1830. {"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, 0, I1, 0, 0 },
  1831. {"xor", "D,S,T", 0x47800002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  1832. -{"xor", "D,S,T", 0x4b800002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  1833. +{"xor", "D,S,T", 0x4b800002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  1834. {"xor.ob", "X,Y,Q", 0x7800000d, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 },
  1835. {"xor.ob", "D,S,Q", 0x4800000d, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 },
  1836. {"xor.qh", "X,Y,Q", 0x7820000d, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 },
  1837. @@ -2429,174 +2444,174 @@ const struct mips_opcode mips_builtin_opcodes[] =
  1838. /* ST Microelectronics Loongson-2E and -2F. */
  1839. {"mult.g", "d,s,t", 0x7c000018, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 },
  1840. {"mult.g", "d,s,t", 0x70000010, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 },
  1841. -{"gsmult", "d,s,t", 0x70000010, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL3A, 0, 0 },
  1842. +{"gsmult", "d,s,t", 0x70000010, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 },
  1843. {"multu.g", "d,s,t", 0x7c000019, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 },
  1844. {"multu.g", "d,s,t", 0x70000012, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 },
  1845. -{"gsmultu", "d,s,t", 0x70000012, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL3A, 0, 0 },
  1846. +{"gsmultu", "d,s,t", 0x70000012, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 },
  1847. {"dmult.g", "d,s,t", 0x7c00001c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 },
  1848. {"dmult.g", "d,s,t", 0x70000011, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 },
  1849. -{"gsdmult", "d,s,t", 0x70000011, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL3A, 0, 0 },
  1850. +{"gsdmult", "d,s,t", 0x70000011, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 },
  1851. {"dmultu.g", "d,s,t", 0x7c00001d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 },
  1852. {"dmultu.g", "d,s,t", 0x70000013, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 },
  1853. -{"gsdmultu", "d,s,t", 0x70000013, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL3A, 0, 0 },
  1854. +{"gsdmultu", "d,s,t", 0x70000013, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 },
  1855. {"div.g", "d,s,t", 0x7c00001a, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 },
  1856. {"div.g", "d,s,t", 0x70000014, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 },
  1857. -{"gsdiv", "d,s,t", 0x70000014, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL3A, 0, 0 },
  1858. +{"gsdiv", "d,s,t", 0x70000014, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 },
  1859. {"divu.g", "d,s,t", 0x7c00001b, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 },
  1860. {"divu.g", "d,s,t", 0x70000016, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 },
  1861. -{"gsdivu", "d,s,t", 0x70000016, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL3A, 0, 0 },
  1862. +{"gsdivu", "d,s,t", 0x70000016, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 },
  1863. {"ddiv.g", "d,s,t", 0x7c00001e, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 },
  1864. {"ddiv.g", "d,s,t", 0x70000015, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 },
  1865. -{"gsddiv", "d,s,t", 0x70000015, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL3A, 0, 0 },
  1866. +{"gsddiv", "d,s,t", 0x70000015, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 },
  1867. {"ddivu.g", "d,s,t", 0x7c00001f, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 },
  1868. {"ddivu.g", "d,s,t", 0x70000017, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 },
  1869. -{"gsddivu", "d,s,t", 0x70000017, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL3A, 0, 0 },
  1870. +{"gsddivu", "d,s,t", 0x70000017, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 },
  1871. {"mod.g", "d,s,t", 0x7c000022, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 },
  1872. {"mod.g", "d,s,t", 0x7000001c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 },
  1873. -{"gsmod", "d,s,t", 0x7000001c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL3A, 0, 0 },
  1874. +{"gsmod", "d,s,t", 0x7000001c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 },
  1875. {"modu.g", "d,s,t", 0x7c000023, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 },
  1876. {"modu.g", "d,s,t", 0x7000001e, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 },
  1877. -{"gsmodu", "d,s,t", 0x7000001e, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL3A, 0, 0 },
  1878. +{"gsmodu", "d,s,t", 0x7000001e, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 },
  1879. {"dmod.g", "d,s,t", 0x7c000026, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 },
  1880. {"dmod.g", "d,s,t", 0x7000001d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 },
  1881. -{"gsdmod", "d,s,t", 0x7000001d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL3A, 0, 0 },
  1882. +{"gsdmod", "d,s,t", 0x7000001d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 },
  1883. {"dmodu.g", "d,s,t", 0x7c000027, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 },
  1884. {"dmodu.g", "d,s,t", 0x7000001f, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 },
  1885. -{"gsdmodu", "d,s,t", 0x7000001f, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL3A, 0, 0 },
  1886. +{"gsdmodu", "d,s,t", 0x7000001f, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 },
  1887. {"packsshb", "D,S,T", 0x47400002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  1888. -{"packsshb", "D,S,T", 0x4b400002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  1889. +{"packsshb", "D,S,T", 0x4b400002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  1890. {"packsswh", "D,S,T", 0x47200002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  1891. -{"packsswh", "D,S,T", 0x4b200002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  1892. +{"packsswh", "D,S,T", 0x4b200002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  1893. {"packushb", "D,S,T", 0x47600002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  1894. -{"packushb", "D,S,T", 0x4b600002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  1895. +{"packushb", "D,S,T", 0x4b600002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  1896. {"paddb", "D,S,T", 0x47c00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  1897. -{"paddb", "D,S,T", 0x4bc00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  1898. +{"paddb", "D,S,T", 0x4bc00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  1899. {"paddb", "d,s,t", 0x70000208, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 },
  1900. {"paddh", "D,S,T", 0x47400000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  1901. {"paddh", "d,s,t", 0x70000108, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 },
  1902. -{"paddh", "D,S,T", 0x4b400000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  1903. +{"paddh", "D,S,T", 0x4b400000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  1904. {"paddw", "D,S,T", 0x47600000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  1905. -{"paddw", "D,S,T", 0x4b600000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  1906. +{"paddw", "D,S,T", 0x4b600000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  1907. {"paddw", "d,s,t", 0x70000008, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 },
  1908. {"paddd", "D,S,T", 0x47e00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  1909. -{"paddd", "D,S,T", 0x4be00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  1910. +{"paddd", "D,S,T", 0x4be00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  1911. {"paddsb", "D,S,T", 0x47800000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  1912. -{"paddsb", "D,S,T", 0x4b800000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  1913. +{"paddsb", "D,S,T", 0x4b800000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  1914. {"paddsb", "d,s,t", 0x70000608, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 },
  1915. {"paddsh", "D,S,T", 0x47000000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  1916. -{"paddsh", "D,S,T", 0x4b000000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  1917. +{"paddsh", "D,S,T", 0x4b000000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  1918. {"paddsh", "d,s,t", 0x70000508, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 },
  1919. {"paddusb", "D,S,T", 0x47a00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  1920. -{"paddusb", "D,S,T", 0x4ba00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  1921. +{"paddusb", "D,S,T", 0x4ba00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  1922. {"paddush", "D,S,T", 0x47200000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  1923. -{"paddush", "D,S,T", 0x4b200000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  1924. +{"paddush", "D,S,T", 0x4b200000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  1925. {"pandn", "D,S,T", 0x47e00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  1926. -{"pandn", "D,S,T", 0x4be00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  1927. +{"pandn", "D,S,T", 0x4be00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  1928. {"pavgb", "D,S,T", 0x46600000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  1929. -{"pavgb", "D,S,T", 0x4b200008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  1930. +{"pavgb", "D,S,T", 0x4b200008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  1931. {"pavgh", "D,S,T", 0x46400000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  1932. -{"pavgh", "D,S,T", 0x4b000008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  1933. +{"pavgh", "D,S,T", 0x4b000008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  1934. {"pcmpeqb", "D,S,T", 0x46c00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  1935. -{"pcmpeqb", "D,S,T", 0x4b800009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  1936. +{"pcmpeqb", "D,S,T", 0x4b800009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  1937. {"pcmpeqh", "D,S,T", 0x46800001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  1938. -{"pcmpeqh", "D,S,T", 0x4b400009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  1939. +{"pcmpeqh", "D,S,T", 0x4b400009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  1940. {"pcmpeqw", "D,S,T", 0x46400001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  1941. -{"pcmpeqw", "D,S,T", 0x4b000009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  1942. +{"pcmpeqw", "D,S,T", 0x4b000009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  1943. {"pcmpgtb", "D,S,T", 0x46e00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  1944. -{"pcmpgtb", "D,S,T", 0x4ba00009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  1945. +{"pcmpgtb", "D,S,T", 0x4ba00009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  1946. {"pcmpgth", "D,S,T", 0x46a00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  1947. -{"pcmpgth", "D,S,T", 0x4b600009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  1948. +{"pcmpgth", "D,S,T", 0x4b600009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  1949. {"pcmpgtw", "D,S,T", 0x46600001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  1950. -{"pcmpgtw", "D,S,T", 0x4b200009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  1951. +{"pcmpgtw", "D,S,T", 0x4b200009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  1952. {"pextrh", "D,S,T", 0x45c00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  1953. -{"pextrh", "D,S,T", 0x4b40000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  1954. +{"pextrh", "D,S,T", 0x4b40000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  1955. {"pinsrh_0", "D,S,T", 0x47800003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  1956. -{"pinsrh_0", "D,S,T", 0x4b800003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  1957. +{"pinsrh_0", "D,S,T", 0x4b800003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  1958. {"pinsrh_1", "D,S,T", 0x47a00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  1959. -{"pinsrh_1", "D,S,T", 0x4ba00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  1960. +{"pinsrh_1", "D,S,T", 0x4ba00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  1961. {"pinsrh_2", "D,S,T", 0x47c00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  1962. -{"pinsrh_2", "D,S,T", 0x4bc00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  1963. +{"pinsrh_2", "D,S,T", 0x4bc00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  1964. {"pinsrh_3", "D,S,T", 0x47e00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  1965. -{"pinsrh_3", "D,S,T", 0x4be00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  1966. +{"pinsrh_3", "D,S,T", 0x4be00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  1967. {"pmaddhw", "D,S,T", 0x45e00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  1968. -{"pmaddhw", "D,S,T", 0x4b60000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  1969. +{"pmaddhw", "D,S,T", 0x4b60000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  1970. {"pmaxsh", "D,S,T", 0x46800000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  1971. -{"pmaxsh", "D,S,T", 0x4b400008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  1972. +{"pmaxsh", "D,S,T", 0x4b400008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  1973. {"pmaxub", "D,S,T", 0x46c00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  1974. -{"pmaxub", "D,S,T", 0x4b800008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  1975. +{"pmaxub", "D,S,T", 0x4b800008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  1976. {"pminsh", "D,S,T", 0x46a00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  1977. -{"pminsh", "D,S,T", 0x4b600008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  1978. +{"pminsh", "D,S,T", 0x4b600008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  1979. {"pminub", "D,S,T", 0x46e00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  1980. -{"pminub", "D,S,T", 0x4ba00008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  1981. +{"pminub", "D,S,T", 0x4ba00008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  1982. {"pmovmskb", "D,S", 0x46a00005, 0xffff003f, WR_1|RD_2|FP_D, 0, IL2E, 0, 0 },
  1983. -{"pmovmskb", "D,S", 0x4ba0000f, 0xffff003f, WR_1|RD_2|FP_D, 0, IL2F|IL3A, 0, 0 },
  1984. +{"pmovmskb", "D,S", 0x4ba0000f, 0xffff003f, WR_1|RD_2|FP_D, 0, 0, LMMI, 0 },
  1985. {"pmulhuh", "D,S,T", 0x46e00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  1986. -{"pmulhuh", "D,S,T", 0x4ba0000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  1987. +{"pmulhuh", "D,S,T", 0x4ba0000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  1988. {"pmulhh", "D,S,T", 0x46a00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  1989. -{"pmulhh", "D,S,T", 0x4b60000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  1990. +{"pmulhh", "D,S,T", 0x4b60000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  1991. {"pmullh", "D,S,T", 0x46800002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  1992. -{"pmullh", "D,S,T", 0x4b40000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  1993. +{"pmullh", "D,S,T", 0x4b40000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  1994. {"pmuluw", "D,S,T", 0x46c00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  1995. -{"pmuluw", "D,S,T", 0x4b80000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  1996. +{"pmuluw", "D,S,T", 0x4b80000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  1997. {"pasubub", "D,S,T", 0x45a00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  1998. -{"pasubub", "D,S,T", 0x4b20000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  1999. +{"pasubub", "D,S,T", 0x4b20000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  2000. {"biadd", "D,S", 0x46800005, 0xffff003f, WR_1|RD_2|FP_D, 0, IL2E, 0, 0 },
  2001. -{"biadd", "D,S", 0x4b80000f, 0xffff003f, WR_1|RD_2|FP_D, 0, IL2F|IL3A, 0, 0 },
  2002. +{"biadd", "D,S", 0x4b80000f, 0xffff003f, WR_1|RD_2|FP_D, 0, 0, LMMI, 0 },
  2003. {"pshufh", "D,S,T", 0x47000002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  2004. -{"pshufh", "D,S,T", 0x4b000002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  2005. +{"pshufh", "D,S,T", 0x4b000002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  2006. {"psllh", "D,S,T", 0x46600002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  2007. -{"psllh", "D,S,T", 0x4b20000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  2008. +{"psllh", "D,S,T", 0x4b20000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  2009. {"psllh", "d,t,<", 0x70000034, 0xffe0003f, WR_1|RD_2, 0, MMI, 0, 0 },
  2010. {"psllw", "D,S,T", 0x46400002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  2011. -{"psllw", "D,S,T", 0x4b00000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  2012. +{"psllw", "D,S,T", 0x4b00000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  2013. {"psllw", "d,t,<", 0x7000003c, 0xffe0003f, WR_1|RD_2, 0, MMI, 0, 0 },
  2014. {"psrah", "D,S,T", 0x46a00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  2015. -{"psrah", "D,S,T", 0x4b60000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  2016. +{"psrah", "D,S,T", 0x4b60000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  2017. {"psrah", "d,t,<", 0x70000037, 0xffe0003f, WR_1|RD_2, 0, MMI, 0, 0 },
  2018. {"psraw", "D,S,T", 0x46800003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  2019. -{"psraw", "D,S,T", 0x4b40000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  2020. +{"psraw", "D,S,T", 0x4b40000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  2021. {"psraw", "d,t,<", 0x7000003f, 0xffe0003f, WR_1|RD_2, 0, MMI, 0, 0 },
  2022. {"psrlh", "D,S,T", 0x46600003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  2023. -{"psrlh", "D,S,T", 0x4b20000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  2024. +{"psrlh", "D,S,T", 0x4b20000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  2025. {"psrlh", "d,t,<", 0x70000036, 0xffe0003f, WR_1|RD_2, 0, MMI, 0, 0 },
  2026. {"psrlw", "D,S,T", 0x46400003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  2027. -{"psrlw", "D,S,T", 0x4b00000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  2028. +{"psrlw", "D,S,T", 0x4b00000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  2029. {"psrlw", "d,t,<", 0x7000003e, 0xffe0003f, WR_1|RD_2, 0, MMI, 0, 0 },
  2030. {"psubb", "D,S,T", 0x47c00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  2031. -{"psubb", "D,S,T", 0x4bc00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  2032. +{"psubb", "D,S,T", 0x4bc00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  2033. {"psubb", "d,s,t", 0x70000248, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 },
  2034. {"psubh", "D,S,T", 0x47400001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  2035. -{"psubh", "D,S,T", 0x4b400001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  2036. +{"psubh", "D,S,T", 0x4b400001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  2037. {"psubh", "d,s,t", 0x70000148, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 },
  2038. {"psubw", "D,S,T", 0x47600001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  2039. -{"psubw", "D,S,T", 0x4b600001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  2040. +{"psubw", "D,S,T", 0x4b600001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  2041. {"psubw", "d,s,t", 0x70000048, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 },
  2042. {"psubd", "D,S,T", 0x47e00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  2043. -{"psubd", "D,S,T", 0x4be00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  2044. +{"psubd", "D,S,T", 0x4be00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  2045. {"psubsb", "D,S,T", 0x47800001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  2046. -{"psubsb", "D,S,T", 0x4b800001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  2047. +{"psubsb", "D,S,T", 0x4b800001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  2048. {"psubsb", "d,s,t", 0x70000648, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 },
  2049. {"psubsh", "D,S,T", 0x47000001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  2050. -{"psubsh", "D,S,T", 0x4b000001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  2051. +{"psubsh", "D,S,T", 0x4b000001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  2052. {"psubsh", "d,s,t", 0x70000548, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 },
  2053. {"psubusb", "D,S,T", 0x47a00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  2054. -{"psubusb", "D,S,T", 0x4ba00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  2055. +{"psubusb", "D,S,T", 0x4ba00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  2056. {"psubush", "D,S,T", 0x47200001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  2057. -{"psubush", "D,S,T", 0x4b200001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  2058. +{"psubush", "D,S,T", 0x4b200001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  2059. {"punpckhbh", "D,S,T", 0x47600003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  2060. -{"punpckhbh", "D,S,T", 0x4b600003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  2061. +{"punpckhbh", "D,S,T", 0x4b600003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  2062. {"punpckhhw", "D,S,T", 0x47200003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  2063. -{"punpckhhw", "D,S,T", 0x4b200003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  2064. +{"punpckhhw", "D,S,T", 0x4b200003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  2065. {"punpckhwd", "D,S,T", 0x46e00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  2066. -{"punpckhwd", "D,S,T", 0x4ba0000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  2067. +{"punpckhwd", "D,S,T", 0x4ba0000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  2068. {"punpcklbh", "D,S,T", 0x47400003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  2069. -{"punpcklbh", "D,S,T", 0x4b400003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  2070. +{"punpcklbh", "D,S,T", 0x4b400003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  2071. {"punpcklhw", "D,S,T", 0x47000003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  2072. -{"punpcklhw", "D,S,T", 0x4b000003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  2073. +{"punpcklhw", "D,S,T", 0x4b000003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  2074. {"punpcklwd", "D,S,T", 0x46c00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
  2075. -{"punpcklwd", "D,S,T", 0x4b80000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 },
  2076. +{"punpcklwd", "D,S,T", 0x4b80000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
  2077. {"sequ", "S,T", 0x46800032, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 },
  2078. -{"sequ", "S,T", 0x4b80000c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2F|IL3A, 0, 0 },
  2079. +{"sequ", "S,T", 0x4b80000c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, 0, LMMI, 0 },
  2080. /* MIPS Enhanced VA Scheme */
  2081. {"lbue", "t,+j(b)", 0x7c000028, 0xfc00007f, WR_1|RD_3|LM, 0, 0, EVA, 0 },
  2082. {"lbue", "t,A(b)", 0, (int) M_LBUE_AB, INSN_MACRO, 0, 0, EVA, 0 },
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