digital_lock.sv

`timescale 1ns / 1ns

typedef enum logic [2:0] {
    S0,
    S1,
    S2,
    S3,
    V0,
    V1,
    V2,
    V3
} state_t;

module digital_lock(
    input wire clock,
    input wire reset,
    input wire [3:0] code,
    input wire mode,

    output wire unlock,
    output wire error,
    output wire [1:0] index_output,
    output wire [1:0] count_output,
    output wire status_output
    );

    reg unlock_reg = 1'b0;
    reg error_reg = 1'b0;
    reg dead = 1'b0;
    reg [3:0] sudo_code [3:0] = {4'b0000, 4'b0000, 4'b0000, 4'b0000};
    reg [3:0] user_code [3:0] = {4'b0000, 4'b0000, 4'b0000, 4'b0000};
    reg [3:0] input_reg [3:0];
    state_t state;
    reg [1:0] index;
    reg [1:0] count = 0;

    always_ff @(posedge clock or posedge reset) begin
        if (reset) begin
            index <= 2'b00;
            unlock_reg <= 1'b0;
            if (state == V0 || state == V1 || state == V2 || state == V3) begin
                state <= V0;
                if (~dead) begin
                    error_reg <= 1'b0;
                end
            end
            else begin
                state <= S0;
            end
        end
        else if (mode == 0 && state <= S3) begin
            state <= V1;
            index <= 2'b01;
            input_reg[0] <= code;
        end
        else if (mode == 1 && state >= V0) begin
            state <= S1;
            index <= 2'b01;
            input_reg[0] <= code;
            if (state == V0) begin
                if (~dead) begin
                    unlock_reg <= 1'b0;
                    error_reg <= 1'b0;
                end
            end
        end
        else if (state >= V0) begin
            input_reg[index] <= code;
            index <= index + 1;
            if (state == V3) begin
                state <= V0;
                if (input_reg[2:0] == sudo_code[2:0] && code == sudo_code[3]) begin
                    unlock_reg <= 1'b1;
                    error_reg <= 1'b0;
                    dead <= 1'b0;
                    count <= 0;
                end
                else if (~dead && input_reg[2:0] == user_code[2:0] && code == user_code[3]) begin
                    unlock_reg <= 1'b1;
                    error_reg <= 1'b0;
                    count <= 0;
                end
                else begin
                    unlock_reg <= 1'b0;
                    error_reg <= 1'b1;
                    if (~dead) begin
                        count <= count + 1;
                    end
                    if (count == 2) begin
                        dead <= 1'b1;
                    end
                end
            end
            else if (state == V0) begin
                state <= state_t'(state + 1);
                if (~dead) begin
                    unlock_reg <= 1'b0;
                    error_reg <= 1'b0;
                end
            end
            else begin
                state <= state_t'(state + 1);
            end
        end
        else begin
            input_reg[index] <= code;
            index <= index + 1;
            state <= state_t'(state + 1);
            if (state == S3) begin
                state <= S0;
                user_code[2:0] <= input_reg[2:0];
                user_code[3] <= code;
            end
        end
    end

    assign unlock = unlock_reg;
    assign error = error_reg;
    assign index_output = index;
    assign count_output = count;
    assign status_output = state <= S3 ? 1'b1 : 1'b0;

endmodule