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  1. 2020.01.02.20:15:05 Info: Saving generation log to <path_to_project>HPSPlatform/HPSPlatform_generation.rpt
  2. 2020.01.02.20:15:05 Info: Starting: <b>Create HDL design files for synthesis</b>
  3. 2020.01.02.20:15:05 Info: qsys-generate <path_to_project>HPSPlatform.qsys --synthesis=VERILOG --output-directory=<path_to_project>HPSPlatform/synthesis --family="Cyclone V" --part=5CSEMA5F31C6
  4. 2020.01.02.20:15:05 Info: Loading hdl/HPSPlatform.qsys2020.01.02.20:15:05 Info: Reading input file2020.01.02.20:15:05 Info: Adding clk_0 [clock_source 18.1]2020.01.02.20:15:05 Warning: clk_0: Used clock_source <b>19.1</b> (instead of 18.1)
  5. 2020.01.02.20:15:05 Info: Parameterizing module clk_02020.01.02.20:15:05 Info: Adding hmi [subsystemHMI 1.0]2020.01.02.20:15:05 Info: Parameterizing module hmi2020.01.02.20:15:05 Info: Adding hps_0 [altera_hps 18.1]
  6. 2020.01.02.20:15:05 Warning: hps_0: Used altera_hps <b>19.1</b> (instead of 18.1)
  7. 2020.01.02.20:15:05 Info: Parameterizing module hps_0
  8. 2020.01.02.20:15:05 Info: Building connections
  9. 2020.01.02.20:15:05 Info: Parameterizing connections
  10. 2020.01.02.20:15:05 Info: Validating
  11. 2020.01.02.20:15:09 Info: Done reading input file
  12. 2020.01.02.20:15:10 Warning: HPSPlatform.hmi.subsystemApds9301.i2c_0: Interrupt sender <b>i2c_0.interrupt_sender</b> is not connected to an interrupt receiver
  13. 2020.01.02.20:15:10 Warning: HPSPlatform.hmi.subsystemHdc1000.i2c_0: Interrupt sender <b>i2c_0.interrupt_sender</b> is not connected to an interrupt receiver
  14. 2020.01.02.20:15:10 Info: HPSPlatform.hmi.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
  15. 2020.01.02.20:15:10 Info: HPSPlatform.hps_0: HPS Main PLL counter settings: n = 0 m = 73
  16. 2020.01.02.20:15:10 Info: HPSPlatform.hps_0: HPS peripherial PLL counter settings: n = 0 m = 39
  17. 2020.01.02.20:15:10 Warning: HPSPlatform.hps_0: <b>"Configuration/HPS-to-FPGA user 0 clock frequency" (desired_cfg_clk_mhz)</b> requested 100.0 MHz, but only achieved 97.368421 MHz
  18. 2020.01.02.20:15:10 Warning: HPSPlatform.hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies.
  19. 2020.01.02.20:20:28 Info: HPSPlatform: Generating <b>HPSPlatform</b> "<b>HPSPlatform</b>" for QUARTUS_SYNTH
  20. 2020.01.02.20:20:32 Warning: hps_0.f2h_irq0: Cannot connect clock for <b>irq_mapper.sender</b>
  21. 2020.01.02.20:20:32 Warning: hps_0.f2h_irq0: Cannot connect reset for <b>irq_mapper.sender</b>
  22. 2020.01.02.20:20:32 Warning: hps_0.f2h_irq1: Cannot connect clock for <b>irq_mapper_001.sender</b>
  23. 2020.01.02.20:20:32 Warning: hps_0.f2h_irq1: Cannot connect reset for <b>irq_mapper_001.sender</b>
  24. 2020.01.02.20:20:34 Info: hmi: "<b>HPSPlatform</b>" instantiated <b>subsystemHMI</b> "<b>hmi</b>"
  25. 2020.01.02.20:20:34 Info: hps_0: "Running for module: hps_0"
  26. 2020.01.02.20:20:34 Info: hps_0: HPS Main PLL counter settings: n = 0 m = 73
  27. 2020.01.02.20:20:34 Info: hps_0: HPS peripherial PLL counter settings: n = 0 m = 39
  28. 2020.01.02.20:20:34 Warning: hps_0: <b>"Configuration/HPS-to-FPGA user 0 clock frequency" (desired_cfg_clk_mhz)</b> requested 100.0 MHz, but only achieved 97.368421 MHz
  29. 2020.01.02.20:20:34 Warning: hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies.
  30. 2020.01.02.20:20:35 Info: hps_0: "<b>HPSPlatform</b>" instantiated <b>altera_hps</b> "<b>hps_0</b>"
  31. 2020.01.02.20:20:35 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
  32. 2020.01.02.20:20:35 Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0
  33. 2020.01.02.20:20:36 Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0
  34. 2020.01.02.20:20:36 Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0
  35. 2020.01.02.20:20:36 Info: avalon_st_adapter_004: Inserting error_adapter: error_adapter_0
  36. 2020.01.02.20:20:36 Info: avalon_st_adapter_005: Inserting error_adapter: error_adapter_0
  37. 2020.01.02.20:20:36 Info: avalon_st_adapter_006: Inserting error_adapter: error_adapter_0
  38. 2020.01.02.20:20:36 Info: mm_interconnect_0: "<b>HPSPlatform</b>" instantiated <b>altera_mm_interconnect</b> "<b>mm_interconnect_0</b>"
  39. 2020.01.02.20:20:36 Info: irq_mapper: "<b>HPSPlatform</b>" instantiated <b>altera_irq_mapper</b> "<b>irq_mapper</b>"
  40. 2020.01.02.20:20:36 Info: irq_mapper_001: "<b>HPSPlatform</b>" instantiated <b>altera_irq_mapper</b> "<b>irq_mapper_001</b>"
  41. 2020.01.02.20:20:36 Info: rst_controller: "<b>HPSPlatform</b>" instantiated <b>altera_reset_controller</b> "<b>rst_controller</b>"
  42. 2020.01.02.20:20:36 Info: interrupt_test_0: "<b>hmi</b>" instantiated <b>interrupt_test</b> "<b>interrupt_test_0</b>"
  43. 2020.01.02.20:20:36 Info: leds: Starting RTL generation for module 'HPSPlatform_hmi_leds'
  44. 2020.01.02.20:20:36 Info: leds: Generation command is [exec /opt/altera/19.1/quartus/linux64/perl/bin/perl -I /opt/altera/19.1/quartus/sopc_builder/bin/europa -I /opt/altera/19.1/quartus/sopc_builder/bin -I /opt/altera/19.1/quartus/../ip/altera/sopc_builder_ip/common -I /opt/altera/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /opt/altera/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=HPSPlatform_hmi_leds --dir=/tmp/alt8263_996550184454444393.dir/0006_leds_gen/ --quartus_dir=/opt/altera/19.1/quartus --verilog --config=/tmp/alt8263_996550184454444393.dir/0006_leds_gen//HPSPlatform_hmi_leds_component_configuration.pl --do_build_sim=0 ]
  45. 2020.01.02.20:20:36 Info: leds: Can't locate Getopt/Long.pm in @INC (you may need to install the Getopt::Long module) (@INC contains: /opt/altera/19.1/quartus/sopc_builder/bin/europa /opt/altera/19.1/quartus/sopc_builder/bin /opt/altera/19.1/quartus/../ip/altera/sopc_builder_ip/common /opt/altera/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio /tools/perl/5.28.1/linux64/lib/site_perl/5.28.1/x86_64-linux /tools/perl/5.28.1/linux64/lib/site_perl/5.28.1 /tools/perl/5.28.1/linux64/lib/5.28.1/x86_64-linux /tools/perl/5.28.1/linux64/lib/5.28.1) at /opt/altera/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl line 18.
  46. 2020.01.02.20:20:36 Info: leds: BEGIN failed--compilation aborted at /opt/altera/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl line 18.
  47. 2020.01.02.20:20:36 Info: leds: Done RTL generation for module 'HPSPlatform_hmi_leds'
  48. 2020.01.02.20:20:36 Error: leds: Failed to find module HPSPlatform_hmi_leds
  49. 2020.01.02.20:20:36 Info: leds: "<b>hmi</b>" instantiated <b>altera_avalon_pio</b> "<b>leds</b>"
  50. 2020.01.02.20:20:36 Error: Generation stopped, 79 or more modules remaining
  51. 2020.01.02.20:20:36 Info: HPSPlatform: Done "<b>HPSPlatform</b>" with 29 modules, 10 files
  52. 2020.01.02.20:20:37 Error: qsys-generate failed with exit code 1: 2 Errors, 12 Warnings
  53. 2020.01.02.20:20:37 Info: Finished: <b>Create HDL design files for synthesis</b>
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