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Verilog - report utilization

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  1. Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
  2. -------------------------------------------------------------------------------------------------------
  3. | Tool Version : Vivado v.2017.3.1 (win64) Build 2035080 Fri Oct 20 14:20:01 MDT 2017
  4. | Date         : Wed Dec 12 17:36:53 2018
  5. | Host         : cadence36 running 64-bit major release  (build 9200)
  6. | Command      : report_utilization -file artix7_utilization_synth.rpt -pb artix7_utilization_synth.pb
  7. | Design       : artix7
  8. | Device       : 7a35tcpg236-1
  9. | Design State : Synthesized
  10. -------------------------------------------------------------------------------------------------------
  11.  
  12. Utilization Design Information
  13.  
  14. Table of Contents
  15. -----------------
  16. 1. Slice Logic
  17. 1.1 Summary of Registers by Type
  18. 2. Memory
  19. 3. DSP
  20. 4. IO and GT Specific
  21. 5. Clocking
  22. 6. Specific Feature
  23. 7. Primitives
  24. 8. Black Boxes
  25. 9. Instantiated Netlists
  26.  
  27. 1. Slice Logic
  28. --------------
  29.  
  30. +-------------------------+------+-------+-----------+-------+
  31. |        Site Type        | Used | Fixed | Available | Util% |
  32. +-------------------------+------+-------+-----------+-------+
  33. | Slice LUTs*             |    2 |     0 |     20800 | <0.01 |
  34. |   LUT as Logic          |    2 |     0 |     20800 | <0.01 |
  35. |   LUT as Memory         |    0 |     0 |      9600 |  0.00 |
  36. | Slice Registers         |    0 |     0 |     41600 |  0.00 |
  37. |   Register as Flip Flop |    0 |     0 |     41600 |  0.00 |
  38. |   Register as Latch     |    0 |     0 |     41600 |  0.00 |
  39. | F7 Muxes                |    0 |     0 |     16300 |  0.00 |
  40. | F8 Muxes                |    0 |     0 |      8150 |  0.00 |
  41. +-------------------------+------+-------+-----------+-------+
  42. * Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
  43.  
  44.  
  45. 1.1 Summary of Registers by Type
  46. --------------------------------
  47.  
  48. +-------+--------------+-------------+--------------+
  49. | Total | Clock Enable | Synchronous | Asynchronous |
  50. +-------+--------------+-------------+--------------+
  51. | 0     |            _ |           - |            - |
  52. | 0     |            _ |           - |          Set |
  53. | 0     |            _ |           - |        Reset |
  54. | 0     |            _ |         Set |            - |
  55. | 0     |            _ |       Reset |            - |
  56. | 0     |          Yes |           - |            - |
  57. | 0     |          Yes |           - |          Set |
  58. | 0     |          Yes |           - |        Reset |
  59. | 0     |          Yes |         Set |            - |
  60. | 0     |          Yes |       Reset |            - |
  61. +-------+--------------+-------------+--------------+
  62.  
  63.  
  64. 2. Memory
  65. ---------
  66.  
  67. +----------------+------+-------+-----------+-------+
  68. |    Site Type   | Used | Fixed | Available | Util% |
  69. +----------------+------+-------+-----------+-------+
  70. | Block RAM Tile |    0 |     0 |        50 |  0.00 |
  71. |   RAMB36/FIFO* |    0 |     0 |        50 |  0.00 |
  72. |   RAMB18       |    0 |     0 |       100 |  0.00 |
  73. +----------------+------+-------+-----------+-------+
  74. * Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
  75.  
  76.  
  77. 3. DSP
  78. ------
  79.  
  80. +-----------+------+-------+-----------+-------+
  81. | Site Type | Used | Fixed | Available | Util% |
  82. +-----------+------+-------+-----------+-------+
  83. | DSPs      |    0 |     0 |        90 |  0.00 |
  84. +-----------+------+-------+-----------+-------+
  85.  
  86.  
  87. 4. IO and GT Specific
  88. ---------------------
  89.  
  90. +-----------------------------+------+-------+-----------+-------+
  91. |          Site Type          | Used | Fixed | Available | Util% |
  92. +-----------------------------+------+-------+-----------+-------+
  93. | Bonded IOB                  |    6 |     0 |       106 |  5.66 |
  94. | Bonded IPADs                |    0 |     0 |        10 |  0.00 |
  95. | Bonded OPADs                |    0 |     0 |         4 |  0.00 |
  96. | PHY_CONTROL                 |    0 |     0 |         5 |  0.00 |
  97. | PHASER_REF                  |    0 |     0 |         5 |  0.00 |
  98. | OUT_FIFO                    |    0 |     0 |        20 |  0.00 |
  99. | IN_FIFO                     |    0 |     0 |        20 |  0.00 |
  100. | IDELAYCTRL                  |    0 |     0 |         5 |  0.00 |
  101. | IBUFDS                      |    0 |     0 |       104 |  0.00 |
  102. | GTPE2_CHANNEL               |    0 |     0 |         2 |  0.00 |
  103. | PHASER_OUT/PHASER_OUT_PHY   |    0 |     0 |        20 |  0.00 |
  104. | PHASER_IN/PHASER_IN_PHY     |    0 |     0 |        20 |  0.00 |
  105. | IDELAYE2/IDELAYE2_FINEDELAY |    0 |     0 |       250 |  0.00 |
  106. | IBUFDS_GTE2                 |    0 |     0 |         2 |  0.00 |
  107. | ILOGIC                      |    0 |     0 |       106 |  0.00 |
  108. | OLOGIC                      |    0 |     0 |       106 |  0.00 |
  109. +-----------------------------+------+-------+-----------+-------+
  110.  
  111.  
  112. 5. Clocking
  113. -----------
  114.  
  115. +------------+------+-------+-----------+-------+
  116. |  Site Type | Used | Fixed | Available | Util% |
  117. +------------+------+-------+-----------+-------+
  118. | BUFGCTRL   |    0 |     0 |        32 |  0.00 |
  119. | BUFIO      |    0 |     0 |        20 |  0.00 |
  120. | MMCME2_ADV |    0 |     0 |         5 |  0.00 |
  121. | PLLE2_ADV  |    0 |     0 |         5 |  0.00 |
  122. | BUFMRCE    |    0 |     0 |        10 |  0.00 |
  123. | BUFHCE     |    0 |     0 |        72 |  0.00 |
  124. | BUFR       |    0 |     0 |        20 |  0.00 |
  125. +------------+------+-------+-----------+-------+
  126.  
  127.  
  128. 6. Specific Feature
  129. -------------------
  130.  
  131. +-------------+------+-------+-----------+-------+
  132. |  Site Type  | Used | Fixed | Available | Util% |
  133. +-------------+------+-------+-----------+-------+
  134. | BSCANE2     |    0 |     0 |         4 |  0.00 |
  135. | CAPTUREE2   |    0 |     0 |         1 |  0.00 |
  136. | DNA_PORT    |    0 |     0 |         1 |  0.00 |
  137. | EFUSE_USR   |    0 |     0 |         1 |  0.00 |
  138. | FRAME_ECCE2 |    0 |     0 |         1 |  0.00 |
  139. | ICAPE2      |    0 |     0 |         2 |  0.00 |
  140. | PCIE_2_1    |    0 |     0 |         1 |  0.00 |
  141. | STARTUPE2   |    0 |     0 |         1 |  0.00 |
  142. | XADC        |    0 |     0 |         1 |  0.00 |
  143. +-------------+------+-------+-----------+-------+
  144.  
  145.  
  146. 7. Primitives
  147. -------------
  148.  
  149. +----------+------+---------------------+
  150. | Ref Name | Used | Functional Category |
  151. +----------+------+---------------------+
  152. | IBUF     |    4 |                  IO |
  153. | OBUF     |    2 |                  IO |
  154. | LUT2     |    2 |                 LUT |
  155. +----------+------+---------------------+
  156.  
  157.  
  158. 8. Black Boxes
  159. --------------
  160.  
  161. +----------+------+
  162. | Ref Name | Used |
  163. +----------+------+
  164.  
  165.  
  166. 9. Instantiated Netlists
  167. ------------------------
  168.  
  169. +----------+------+
  170. | Ref Name | Used |
  171. +----------+------+
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