IRQ_Handler

ITCM:01FF80F0             @ void __fastcall OS_IrqHandler__()
ITCM:01FF80F0             OS_IrqHandler__:                        @ DATA XREF: nitroStart__+178o
ITCM:01FF80F0                                                     @ RAM_ARM9:off_20049F0o
ITCM:01FF80F0
ITCM:01FF80F0             var_4           = -4
ITCM:01FF80F0
ITCM:01FF80F0 00 40 2D E9                 STMFD   SP!, {LR}
ITCM:01FF80F4 01 C3 A0 E3+                MOV     R12, 0x4000210
ITCM:01FF80FC 08 10 1C E5                 LDR     R1, [R12,#-8]   @ r1 = IME- interrupt master enable pointer
ITCM:01FF8100 00 00 51 E3                 CMP     R1, #0          @ Is the IME off?
ITCM:01FF8104 00 80 BD 08                 LDMFDEQ SP!, {PC}       @ If so, there's no interrupt to process, return
ITCM:01FF8108 06 00 9C E8                 LDMIA   R12, {R1,R2}    @ fetch reg_IE and reg_IF
ITCM:01FF810C 02 10 11 E0                 ANDS    R1, R1, R2
ITCM:01FF8110 00 80 BD 08                 LDMFDEQ SP!, {PC}       @ if reg_IE and reg_IF are both 0, return
ITCM:01FF8114 02 31 A0 E3                 MOV     R3, #0x80000000 @ IRQ code for ARMv5
ITCM:01FF8118
ITCM:01FF8118             loc_1FF8118:                            @ CODE XREF: OS_IrqHandler__+30j
ITCM:01FF8118 11 0F 6F E1                 CLZ     R0, R1          @ fetch lowest one bit
ITCM:01FF811C 33 10 D1 E1                 BICS    R1, R1, R3,LSR R0
ITCM:01FF8120 FC FF FF 1A                 BNE     loc_1FF8118
ITCM:01FF8124 33 10 A0 E1                 MOV     R1, R3,LSR R0   @ clear IE
ITCM:01FF8128 04 10 8C E5                 STR     R1, [R12,#4]
ITCM:01FF812C 1F 00 70 E2                 RSBS    R0, R0, #0x1F   @ get jump vector
ITCM:01FF8130 08 10 9F E5                 LDR     R1, =0x2FE0020  @ IRQ Table @ =0x02FE0020
ITCM:01FF8134 00 01 91 E7                 LDR     R0, [R1,R0,LSL#2]
ITCM:01FF8138 04 E0 9F E5                 LDR     LR, =OS_IrqHandler_ThreadSwitch__
ITCM:01FF813C 10 FF 2F E1                 BX      R0              @ set return address for thread rescheduling