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MUX_ALU.v
kekellner
Nov 16th, 2024
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SystemVerilog
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module
MUX_ALU
(
input
[
7
:
0
]
_0
,
input
[
7
:
0
]
_1
,
input
S
,
output
[
7
:
0
]
Y
)
;
assign
Y
=
S
?
_1
:
_0
;
endmodule
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