Pastebin
API
tools
faq
paste
Login
Sign up
SHARE
TWEET
MUX_ALU.v
kekellner
Nov 16th, 2024
1,227
0
Never
Add comment
Not a member of Pastebin yet?
Sign Up
, it unlocks many cool features!
SystemVerilog
0.14 KB
| None
|
0
0
raw
download
clone
embed
print
report
module
MUX_ALU
(
input
[
7
:
0
]
_0
,
input
[
7
:
0
]
_1
,
input
S
,
output
[
7
:
0
]
Y
)
;
assign
Y
=
S
?
_1
:
_0
;
endmodule
Advertisement
Add Comment
Please,
Sign In
to add comment
Public Pastes
Documents
50 min ago | 0.43 KB
Free Crypto Method
CSS | 50 min ago | 0.72 KB
Crypto admin access
50 min ago | 0.43 KB
+12,000$ in 2 days
CSS | 50 min ago | 0.72 KB
Free $$$ Mehtod
CSS | 56 min ago | 0.71 KB
Free money docs
CSS | 57 min ago | 0.71 KB
2 Day in +12.000$
CSS | 57 min ago | 0.71 KB
Instant Profits with Crypto
CSS | 57 min ago | 0.71 KB
We use cookies for various purposes including analytics. By continuing to use Pastebin, you agree to our use of cookies as described in the
Cookies Policy
.
OK, I Understand
Not a member of Pastebin yet?
Sign Up
, it unlocks many cool features!