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AlexanderAntonov
Nov 2nd, 2022
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SystemVerilog
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module
mux_structural
(
input
[
1
:
0
]
sel_bi
,
input
[
3
:
0
]
data_bi
,
output
q_o
)
;
assign
q_o
=
data_bi
[
sel_bi
]
;
endmodule
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