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linux next20200529 pinebookpro drm diff

xmixahlx
May 31st, 2020
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  1. diff -uNr '--exclude=.git' '--exclude=include-prefixes' linux-next_next-20200501/arch/arm64/boot/dts/rockchip/rk3328.dtsi linux-rockchip_next-20200501-drm-rockchip/arch/arm64/boot/dts/rockchip/rk3328.dtsi
  2. --- linux-next_next-20200501/arch/arm64/boot/dts/rockchip/rk3328.dtsi 2020-05-26 03:51:51.021292080 -0700
  3. +++ linux-rockchip_next-20200501-drm-rockchip/arch/arm64/boot/dts/rockchip/rk3328.dtsi 2020-05-26 04:11:08.422213866 -0700
  4. @@ -801,8 +801,8 @@
  5. <0>, <24000000>,
  6. <24000000>, <24000000>,
  7. <15000000>, <15000000>,
  8. - <100000000>, <100000000>,
  9. - <100000000>, <100000000>,
  10. + <300000000>, <100000000>,
  11. + <400000000>, <100000000>,
  12. <50000000>, <100000000>,
  13. <100000000>, <100000000>,
  14. <50000000>, <50000000>,
  15. diff -uNr '--exclude=.git' '--exclude=include-prefixes' linux-next_next-20200501/arch/arm64/boot/dts/rockchip/rk3399.dtsi linux-rockchip_next-20200501-drm-rockchip/arch/arm64/boot/dts/rockchip/rk3399.dtsi
  16. --- linux-next_next-20200501/arch/arm64/boot/dts/rockchip/rk3399.dtsi 2020-05-26 03:51:51.025292138 -0700
  17. +++ linux-rockchip_next-20200501-drm-rockchip/arch/arm64/boot/dts/rockchip/rk3399.dtsi 2020-05-26 04:11:08.426213904 -0700
  18. @@ -1589,7 +1589,7 @@
  19. reg = <0x0 0xff8f0000 0x0 0x3efc>;
  20. interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
  21. assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
  22. - assigned-clock-rates = <400000000>, <100000000>;
  23. + assigned-clock-rates = <400000000>, <200000000>;
  24. clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
  25. clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
  26. iommus = <&vopl_mmu>;
  27. @@ -1646,7 +1646,7 @@
  28. reg = <0x0 0xff900000 0x0 0x3efc>;
  29. interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
  30. assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
  31. - assigned-clock-rates = <400000000>, <100000000>;
  32. + assigned-clock-rates = <400000000>, <200000000>;
  33. clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
  34. clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
  35. iommus = <&vopb_mmu>;
  36. diff -uNr '--exclude=.git' '--exclude=include-prefixes' linux-next_next-20200501/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts linux-rockchip_next-20200501-drm-rockchip/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts
  37. --- linux-next_next-20200501/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts 2020-05-26 03:51:51.025292138 -0700
  38. +++ linux-rockchip_next-20200501-drm-rockchip/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts 2020-05-26 04:11:08.422213866 -0700
  39. @@ -733,3 +733,6 @@
  40. &vopl_mmu {
  41. status = "okay";
  42. };
  43. +
  44. +/delete-node/ &hdmi_in_vopl;
  45. +/delete-node/ &vopl_out_hdmi;
  46. diff -uNr '--exclude=.git' '--exclude=include-prefixes' linux-next_next-20200501/drivers/clk/rockchip/clk-rk3228.c linux-rockchip_next-20200501-drm-rockchip/drivers/clk/rockchip/clk-rk3228.c
  47. --- linux-next_next-20200501/drivers/clk/rockchip/clk-rk3228.c 2020-05-26 03:51:51.881304576 -0700
  48. +++ linux-rockchip_next-20200501-drm-rockchip/drivers/clk/rockchip/clk-rk3228.c 2020-05-26 04:11:09.270221951 -0700
  49. @@ -408,7 +408,7 @@
  50. RK2928_CLKSEL_CON(29), 0, 3, DFLAGS),
  51. DIV(0, "sclk_vop_pre", "sclk_vop_src", 0,
  52. RK2928_CLKSEL_CON(27), 8, 8, DFLAGS),
  53. - MUX(DCLK_VOP, "dclk_vop", mux_dclk_vop_p, 0,
  54. + MUX(DCLK_VOP, "dclk_vop", mux_dclk_vop_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  55. RK2928_CLKSEL_CON(27), 1, 1, MFLAGS),
  56.  
  57. FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
  58. diff -uNr '--exclude=.git' '--exclude=include-prefixes' linux-next_next-20200501/drivers/clk/rockchip/clk-rk3399.c linux-rockchip_next-20200501-drm-rockchip/drivers/clk/rockchip/clk-rk3399.c
  59. --- linux-next_next-20200501/drivers/clk/rockchip/clk-rk3399.c 2020-05-26 03:51:51.881304576 -0700
  60. +++ linux-rockchip_next-20200501-drm-rockchip/drivers/clk/rockchip/clk-rk3399.c 2020-05-26 04:11:09.270221951 -0700
  61. @@ -103,6 +103,25 @@
  62. { /* sentinel */ },
  63. };
  64.  
  65. +static struct rockchip_pll_rate_table rk3399_vpll_rates[] = {
  66. + /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
  67. + RK3036_PLL_RATE( 594000000, 1, 123, 5, 1, 0, 12582912), /* vco = 2970000000 */
  68. + RK3036_PLL_RATE( 593406592, 1, 123, 5, 1, 0, 10508804), /* vco = 2967032965 */
  69. + RK3036_PLL_RATE( 297000000, 1, 123, 5, 2, 0, 12582912), /* vco = 2970000000 */
  70. + RK3036_PLL_RATE( 296703296, 1, 123, 5, 2, 0, 10508807), /* vco = 2967032970 */
  71. + RK3036_PLL_RATE( 148500000, 1, 129, 7, 3, 0, 15728640), /* vco = 3118500000 */
  72. + RK3036_PLL_RATE( 148351648, 1, 123, 5, 4, 0, 10508800), /* vco = 2967032960 */
  73. + RK3036_PLL_RATE( 106500000, 1, 124, 7, 4, 0, 4194304), /* vco = 2982000000 */
  74. + RK3036_PLL_RATE( 74250000, 1, 129, 7, 6, 0, 15728640), /* vco = 3118500000 */
  75. + RK3036_PLL_RATE( 74175824, 1, 129, 7, 6, 0, 13550823), /* vco = 3115384608 */
  76. + RK3036_PLL_RATE( 65000000, 1, 113, 7, 6, 0, 12582912), /* vco = 2730000000 */
  77. + RK3036_PLL_RATE( 59340659, 1, 121, 7, 7, 0, 2581098), /* vco = 2907692291 */
  78. + RK3036_PLL_RATE( 54000000, 1, 110, 7, 7, 0, 4194304), /* vco = 2646000000 */
  79. + RK3036_PLL_RATE( 27000000, 1, 55, 7, 7, 0, 2097152), /* vco = 1323000000 */
  80. + RK3036_PLL_RATE( 26973026, 1, 55, 7, 7, 0, 1173232), /* vco = 1321678323 */
  81. + { /* sentinel */ },
  82. +};
  83. +
  84. /* CRU parents */
  85. PNAME(mux_pll_p) = { "xin24m", "xin32k" };
  86.  
  87. @@ -121,7 +140,7 @@
  88. PNAME(mux_aclk_cci_p) = { "cpll_aclk_cci_src",
  89. "gpll_aclk_cci_src",
  90. "npll_aclk_cci_src",
  91. - "vpll_aclk_cci_src" };
  92. + "prevent:vpll" };
  93. PNAME(mux_cci_trace_p) = { "cpll_cci_trace",
  94. "gpll_cci_trace" };
  95. PNAME(mux_cs_p) = { "cpll_cs", "gpll_cs",
  96. @@ -148,9 +167,10 @@
  97. "ppll", "upll", "xin24m" };
  98.  
  99. PNAME(mux_pll_src_vpll_cpll_gpll_p) = { "vpll", "cpll", "gpll" };
  100. -PNAME(mux_pll_src_vpll_cpll_gpll_npll_p) = { "vpll", "cpll", "gpll",
  101. +
  102. +PNAME(mux_pll_src_vpll_cpll_gpll_npll_p) = { "prevent:vpll", "cpll", "gpll",
  103. "npll" };
  104. -PNAME(mux_pll_src_vpll_cpll_gpll_24m_p) = { "vpll", "cpll", "gpll",
  105. +PNAME(mux_pll_src_vpll_cpll_gpll_24m_p) = { "prevent:vpll", "cpll", "gpll",
  106. "xin24m" };
  107.  
  108. PNAME(mux_dclk_vop0_p) = { "dclk_vop0_div",
  109. @@ -227,7 +247,7 @@
  110. [npll] = PLL(pll_rk3399, PLL_NPLL, "npll", mux_pll_p, 0, RK3399_PLL_CON(40),
  111. RK3399_PLL_CON(43), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
  112. [vpll] = PLL(pll_rk3399, PLL_VPLL, "vpll", mux_pll_p, 0, RK3399_PLL_CON(48),
  113. - RK3399_PLL_CON(51), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
  114. + RK3399_PLL_CON(51), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_vpll_rates),
  115. };
  116.  
  117. static struct rockchip_pll_clock rk3399_pmu_pll_clks[] __initdata = {
  118. @@ -277,7 +297,7 @@
  119. RK3399_PMU_CLKSEL_CON(5), 8, 2, MFLAGS);
  120.  
  121. static struct rockchip_clk_branch rk3399_dclk_vop0_fracmux __initdata =
  122. - MUX(DCLK_VOP0, "dclk_vop0", mux_dclk_vop0_p, CLK_SET_RATE_PARENT,
  123. + MUX(DCLK_VOP0, "dclk_vop0", mux_dclk_vop0_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  124. RK3399_CLKSEL_CON(49), 11, 1, MFLAGS);
  125.  
  126. static struct rockchip_clk_branch rk3399_dclk_vop1_fracmux __initdata =
  127. @@ -1158,7 +1178,7 @@
  128. GATE(HCLK_VOP0_NOC, "hclk_vop0_noc", "hclk_vop0_pre", CLK_IGNORE_UNUSED,
  129. RK3399_CLKGATE_CON(28), 0, GFLAGS),
  130.  
  131. - COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p, 0,
  132. + COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  133. RK3399_CLKSEL_CON(49), 8, 2, MFLAGS, 0, 8, DFLAGS,
  134. RK3399_CLKGATE_CON(10), 12, GFLAGS),
  135.  
  136. diff -uNr '--exclude=.git' '--exclude=include-prefixes' linux-next_next-20200501/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c linux-rockchip_next-20200501-drm-rockchip/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
  137. --- linux-next_next-20200501/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c 2020-05-26 03:51:52.689316310 -0700
  138. +++ linux-rockchip_next-20200501-drm-rockchip/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c 2020-05-26 04:11:10.078229655 -0700
  139. @@ -79,80 +79,88 @@
  140.  
  141. static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
  142. {
  143. - 27000000, {
  144. - { 0x00b3, 0x0000},
  145. - { 0x2153, 0x0000},
  146. - { 0x40f3, 0x0000}
  147. - },
  148. - }, {
  149. - 36000000, {
  150. - { 0x00b3, 0x0000},
  151. - { 0x2153, 0x0000},
  152. - { 0x40f3, 0x0000}
  153. - },
  154. - }, {
  155. - 40000000, {
  156. - { 0x00b3, 0x0000},
  157. - { 0x2153, 0x0000},
  158. - { 0x40f3, 0x0000}
  159. - },
  160. - }, {
  161. - 54000000, {
  162. - { 0x0072, 0x0001},
  163. - { 0x2142, 0x0001},
  164. - { 0x40a2, 0x0001},
  165. - },
  166. - }, {
  167. - 65000000, {
  168. - { 0x0072, 0x0001},
  169. - { 0x2142, 0x0001},
  170. - { 0x40a2, 0x0001},
  171. - },
  172. - }, {
  173. - 66000000, {
  174. - { 0x013e, 0x0003},
  175. - { 0x217e, 0x0002},
  176. - { 0x4061, 0x0002}
  177. - },
  178. - }, {
  179. - 74250000, {
  180. - { 0x0072, 0x0001},
  181. - { 0x2145, 0x0002},
  182. - { 0x4061, 0x0002}
  183. - },
  184. - }, {
  185. - 83500000, {
  186. - { 0x0072, 0x0001},
  187. - },
  188. - }, {
  189. - 108000000, {
  190. - { 0x0051, 0x0002},
  191. - { 0x2145, 0x0002},
  192. - { 0x4061, 0x0002}
  193. - },
  194. - }, {
  195. - 106500000, {
  196. - { 0x0051, 0x0002},
  197. - { 0x2145, 0x0002},
  198. - { 0x4061, 0x0002}
  199. - },
  200. - }, {
  201. - 146250000, {
  202. - { 0x0051, 0x0002},
  203. - { 0x2145, 0x0002},
  204. - { 0x4061, 0x0002}
  205. - },
  206. - }, {
  207. - 148500000, {
  208. - { 0x0051, 0x0003},
  209. - { 0x214c, 0x0003},
  210. - { 0x4064, 0x0003}
  211. + 30666000, {
  212. + { 0x00b3, 0x0000 },
  213. + { 0x2153, 0x0000 },
  214. + { 0x40f3, 0x0000 },
  215. + },
  216. + }, {
  217. + 36800000, {
  218. + { 0x00b3, 0x0000 },
  219. + { 0x2153, 0x0000 },
  220. + { 0x40a2, 0x0001 },
  221. + },
  222. + }, {
  223. + 46000000, {
  224. + { 0x00b3, 0x0000 },
  225. + { 0x2142, 0x0001 },
  226. + { 0x40a2, 0x0001 },
  227. + },
  228. + }, {
  229. + 61333000, {
  230. + { 0x0072, 0x0001 },
  231. + { 0x2142, 0x0001 },
  232. + { 0x40a2, 0x0001 },
  233. + },
  234. + }, {
  235. + 73600000, {
  236. + { 0x0072, 0x0001 },
  237. + { 0x2142, 0x0001 },
  238. + { 0x4061, 0x0002 },
  239. + },
  240. + }, {
  241. + 92000000, {
  242. + { 0x0072, 0x0001 },
  243. + { 0x2145, 0x0002 },
  244. + { 0x4061, 0x0002 },
  245. + },
  246. + }, {
  247. + 122666000, {
  248. + { 0x0051, 0x0002 },
  249. + { 0x2145, 0x0002 },
  250. + { 0x4061, 0x0002 },
  251. + },
  252. + }, {
  253. + 147200000, {
  254. + { 0x0051, 0x0002 },
  255. + { 0x2145, 0x0002 },
  256. + { 0x4064, 0x0003 },
  257. + },
  258. + }, {
  259. + 184000000, {
  260. + { 0x0051, 0x0002 },
  261. + { 0x214c, 0x0003 },
  262. + { 0x4064, 0x0003 },
  263. + },
  264. + }, {
  265. + 226666000, {
  266. + { 0x0040, 0x0003 },
  267. + { 0x214c, 0x0003 },
  268. + { 0x4064, 0x0003 },
  269. + },
  270. + }, {
  271. + 272000000, {
  272. + { 0x0040, 0x0003 },
  273. + { 0x214c, 0x0003 },
  274. + { 0x5a64, 0x0003 },
  275. + },
  276. + }, {
  277. + 340000000, {
  278. + { 0x0040, 0x0003 },
  279. + { 0x3b4c, 0x0003 },
  280. + { 0x5a64, 0x0003 },
  281. + },
  282. + }, {
  283. + 600000000, {
  284. + { 0x1a40, 0x0003 },
  285. + { 0x3b4c, 0x0003 },
  286. + { 0x5a64, 0x0003 },
  287. },
  288. - }, {
  289. + }, {
  290. ~0UL, {
  291. - { 0x00a0, 0x000a },
  292. - { 0x2001, 0x000f },
  293. - { 0x4002, 0x000f },
  294. + { 0x0000, 0x0000 },
  295. + { 0x0000, 0x0000 },
  296. + { 0x0000, 0x0000 },
  297. },
  298. }
  299. };
  300. @@ -160,20 +168,8 @@
  301. static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
  302. /* pixelclk bpp8 bpp10 bpp12 */
  303. {
  304. - 40000000, { 0x0018, 0x0018, 0x0018 },
  305. - }, {
  306. - 65000000, { 0x0028, 0x0028, 0x0028 },
  307. - }, {
  308. - 66000000, { 0x0038, 0x0038, 0x0038 },
  309. - }, {
  310. - 74250000, { 0x0028, 0x0038, 0x0038 },
  311. - }, {
  312. - 83500000, { 0x0028, 0x0038, 0x0038 },
  313. - }, {
  314. - 146250000, { 0x0038, 0x0038, 0x0038 },
  315. - }, {
  316. - 148500000, { 0x0000, 0x0038, 0x0038 },
  317. - }, {
  318. + 600000000, { 0x0000, 0x0000, 0x0000 },
  319. + }, {
  320. ~0UL, { 0x0000, 0x0000, 0x0000},
  321. }
  322. };
  323. @@ -181,8 +177,9 @@
  324. static const struct dw_hdmi_phy_config rockchip_phy_config[] = {
  325. /*pixelclk symbol term vlev*/
  326. { 74250000, 0x8009, 0x0004, 0x0272},
  327. - { 148500000, 0x802b, 0x0004, 0x028d},
  328. + { 165000000, 0x802b, 0x0004, 0x0209},
  329. { 297000000, 0x8039, 0x0005, 0x028d},
  330. + { 594000000, 0x8039, 0x0000, 0x019d},
  331. { ~0UL, 0x0000, 0x0000, 0x0000}
  332. };
  333.  
  334. @@ -223,25 +220,62 @@
  335. dw_hdmi_rockchip_mode_valid(struct drm_connector *connector,
  336. const struct drm_display_mode *mode)
  337. {
  338. - const struct dw_hdmi_mpll_config *mpll_cfg = rockchip_mpll_cfg;
  339. - int pclk = mode->clock * 1000;
  340. - bool valid = false;
  341. - int i;
  342. -
  343. - for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) {
  344. - if (pclk == mpll_cfg[i].mpixelclock) {
  345. - valid = true;
  346. - break;
  347. - }
  348. - }
  349. + struct drm_display_info *info = &connector->display_info;
  350. + int clock = mode->clock;
  351. +
  352. + if (mode->hdisplay > 3840)
  353. + return MODE_VIRTUAL_X;
  354. +
  355. + if (mode->vdisplay > 2160)
  356. + return MODE_VIRTUAL_Y;
  357. +
  358. + if (connector->ycbcr_420_allowed && drm_mode_is_420(info, mode) &&
  359. + (info->color_formats & DRM_COLOR_FORMAT_YCRCB420))
  360. + clock /= 2;
  361. +
  362. + if (clock > 340000 ||
  363. + (info->max_tmds_clock && clock > info->max_tmds_clock))
  364. + return MODE_CLOCK_HIGH;
  365.  
  366. - return (valid) ? MODE_OK : MODE_BAD;
  367. + return MODE_OK;
  368. }
  369.  
  370. static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder)
  371. {
  372. }
  373.  
  374. +/*
  375. + * The VESA DMT standard specifies a 0.5% pixel clock frequency tolerance.
  376. + * The CVT spec reuses that tolerance in its examples.
  377. + */
  378. +#define CLOCK_TOLERANCE_PER_MILLE 5
  379. +
  380. +static enum drm_mode_status
  381. +dw_hdmi_rockchip_encoder_mode_valid(struct drm_encoder *encoder,
  382. + const struct drm_display_mode *mode)
  383. +{
  384. + struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
  385. + long rounded_rate;
  386. + long lowest, highest;
  387. +
  388. + if (hdmi->vpll_clk) {
  389. + rounded_rate = clk_round_rate(hdmi->vpll_clk,
  390. + mode->clock * 1000 + 999);
  391. + if (rounded_rate < 0)
  392. + return MODE_NOCLOCK;
  393. +
  394. + lowest = mode->clock * (1000 - CLOCK_TOLERANCE_PER_MILLE);
  395. + if (rounded_rate < lowest)
  396. + return MODE_CLOCK_LOW;
  397. +
  398. + highest = mode->clock * (1000 + CLOCK_TOLERANCE_PER_MILLE);
  399. + if (rounded_rate > highest)
  400. + return MODE_CLOCK_HIGH;
  401. + }
  402. +
  403. + return MODE_OK;
  404. +}
  405. +
  406. static bool
  407. dw_hdmi_rockchip_encoder_mode_fixup(struct drm_encoder *encoder,
  408. const struct drm_display_mode *mode,
  409. @@ -303,6 +337,7 @@
  410. }
  411.  
  412. static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = {
  413. + .mode_valid = dw_hdmi_rockchip_encoder_mode_valid,
  414. .mode_fixup = dw_hdmi_rockchip_encoder_mode_fixup,
  415. .mode_set = dw_hdmi_rockchip_encoder_mode_set,
  416. .enable = dw_hdmi_rockchip_encoder_enable,
  417. @@ -315,6 +350,8 @@
  418. {
  419. struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
  420.  
  421. + dw_hdmi_set_high_tmds_clock_ratio(dw_hdmi);
  422. +
  423. return phy_power_on(hdmi->phy);
  424. }
  425.  
  426. @@ -403,9 +440,6 @@
  427.  
  428. static const struct dw_hdmi_plat_data rk3228_hdmi_drv_data = {
  429. .mode_valid = dw_hdmi_rockchip_mode_valid,
  430. - .mpll_cfg = rockchip_mpll_cfg,
  431. - .cur_ctr = rockchip_cur_ctr,
  432. - .phy_config = rockchip_phy_config,
  433. .phy_data = &rk3228_chip_data,
  434. .phy_ops = &rk3228_hdmi_phy_ops,
  435. .phy_name = "inno_dw_hdmi_phy2",
  436. @@ -440,9 +474,6 @@
  437.  
  438. static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = {
  439. .mode_valid = dw_hdmi_rockchip_mode_valid,
  440. - .mpll_cfg = rockchip_mpll_cfg,
  441. - .cur_ctr = rockchip_cur_ctr,
  442. - .phy_config = rockchip_phy_config,
  443. .phy_data = &rk3328_chip_data,
  444. .phy_ops = &rk3328_hdmi_phy_ops,
  445. .phy_name = "inno_dw_hdmi_phy2",
  446. diff -uNr '--exclude=.git' '--exclude=include-prefixes' linux-next_next-20200501/drivers/gpu/drm/rockchip/rockchip_drm_vop.c linux-rockchip_next-20200501-drm-rockchip/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
  447. --- linux-next_next-20200501/drivers/gpu/drm/rockchip/rockchip_drm_vop.c 2020-05-26 03:51:52.689316310 -0700
  448. +++ linux-rockchip_next-20200501-drm-rockchip/drivers/gpu/drm/rockchip/rockchip_drm_vop.c 2020-05-26 04:11:10.082229693 -0700
  449. @@ -1138,6 +1138,34 @@
  450. spin_unlock_irqrestore(&vop->irq_lock, flags);
  451. }
  452.  
  453. +/*
  454. + * The VESA DMT standard specifies a 0.5% pixel clock frequency tolerance.
  455. + * The CVT spec reuses that tolerance in its examples.
  456. + */
  457. +#define CLOCK_TOLERANCE_PER_MILLE 5
  458. +
  459. +static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc,
  460. + const struct drm_display_mode *mode)
  461. +{
  462. + struct vop *vop = to_vop(crtc);
  463. + long rounded_rate;
  464. + long lowest, highest;
  465. +
  466. + rounded_rate = clk_round_rate(vop->dclk, mode->clock * 1000 + 999);
  467. + if (rounded_rate < 0)
  468. + return MODE_NOCLOCK;
  469. +
  470. + lowest = mode->clock * (1000 - CLOCK_TOLERANCE_PER_MILLE);
  471. + if (rounded_rate < lowest)
  472. + return MODE_CLOCK_LOW;
  473. +
  474. + highest = mode->clock * (1000 + CLOCK_TOLERANCE_PER_MILLE);
  475. + if (rounded_rate > highest)
  476. + return MODE_CLOCK_HIGH;
  477. +
  478. + return MODE_OK;
  479. +}
  480. +
  481. static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
  482. const struct drm_display_mode *mode,
  483. struct drm_display_mode *adjusted_mode)
  484. @@ -1508,6 +1536,7 @@
  485. }
  486.  
  487. static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
  488. + .mode_valid = vop_crtc_mode_valid,
  489. .mode_fixup = vop_crtc_mode_fixup,
  490. .atomic_check = vop_crtc_atomic_check,
  491. .atomic_begin = vop_crtc_atomic_begin,
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