Release 14.7 - xst P.20160913 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
-->
Parameter TMPDIR set to xst/projnav.tmp


Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.12 secs

-->
Parameter xsthdpdir set to xst


Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.12 secs

-->
Reading design: top.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Parsing
  3) HDL Elaboration
  4) HDL Synthesis
       4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
       5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Partition Report
  8) Design Summary
       8.1) Primitive and Black Box Usage
       8.2) Device utilization summary
       8.3) Partition Resource Summary
       8.4) Timing Report
            8.4.1) Clock Information
            8.4.2) Asynchronous Control Signals Information
            8.4.3) Timing Summary
            8.4.4) Timing Details
            8.4.5) Cross Clock Domains Report


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "top.prj"
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "top"
Output Format                      : NGC
Target Device                      : xa6slx4-3-csg225

---- Source Options
Top Module Name                    : top
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : LUT
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Shift Register Extraction          : YES
ROM Style                          : Auto
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Shift Register Minimum Size        : 2
Use DSP Block                      : Auto
Automatic Register Balancing       : No

---- Target Options
LUT Combining                      : Auto
Reduce Control Sets                : Auto
Add IO Buffers                     : YES
Global Maximum Fanout              : 100000
Add Generic Clock Buffer(BUFG)     : 24
Register Duplication               : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Yes
Use Synchronous Set                : Yes
Use Synchronous Reset              : Yes
Pack IO Registers into IOBs        : Auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Power Reduction                    : NO
Keep Hierarchy                     : No
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
DSP48 Utilization Ratio            : 100
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

=========================================================================


=========================================================================
*                          HDL Parsing                                  *
=========================================================================
Analyzing Verilog file "/home/ise/Desktop/Keyboard/write_cycle.v" into library work
Parsing module <write_cycle>.
Analyzing Verilog file "/home/ise/Desktop/Keyboard/main_controller.v" into library work
Parsing module <main_controller>.
Analyzing Verilog file "/home/ise/Desktop/Keyboard/lcd_init_refresh.v" into library work
Parsing module <lcd_init_refresh>.
Analyzing Verilog file "/home/ise/Desktop/Keyboard/lcd_dp.v" into library work
Parsing module <lcd_dp>.
Analyzing Verilog file "/home/ise/Desktop/Keyboard/LCD_controller.v" into library work
Parsing module <LCD_controller>.
Analyzing Verilog file "/home/ise/Desktop/Keyboard/clk_divider.v" into library work
Parsing module <clk_divider>.
Analyzing Verilog file "/home/ise/Desktop/Keyboard/LCD_driver.v" into library work
Parsing module <LCD_driver>.
Analyzing Verilog file "/home/ise/Desktop/Keyboard/Keyboard2.v" into library work
Parsing module <Keyboard2>.
Analyzing Verilog file "/home/ise/Desktop/Keyboard/decoder.v" into library work
Parsing module <decoder>.
Analyzing Verilog file "/home/ise/Desktop/Keyboard/top.v" into library work
Parsing module <top>.

=========================================================================
*                            HDL Elaboration                            *
=========================================================================

Elaborating module <top>.

Elaborating module <Keyboard2>.
WARNING:HDLCompiler:413 - "/home/ise/Desktop/Keyboard/Keyboard2.v" Line 37: Result of 5-bit expression is truncated to fit in 4-bit target.

Elaborating module <decoder>.
Reading initialization file \"scan_codes.dat\".

Elaborating module <LCD_driver(div=50000)>.

Elaborating module <LCD_controller>.

Elaborating module <main_controller>.

Elaborating module <write_cycle>.

Elaborating module <lcd_init_refresh>.
WARNING:HDLCompiler:413 - "/home/ise/Desktop/Keyboard/lcd_init_refresh.v" Line 64: Result of 32-bit expression is truncated to fit in 2-bit target.
WARNING:HDLCompiler:413 - "/home/ise/Desktop/Keyboard/lcd_init_refresh.v" Line 73: Result of 32-bit expression is truncated to fit in 4-bit target.

Elaborating module <lcd_dp>.

Elaborating module <clk_divider(div=50000)>.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <top>.
    Related source file is "/home/ise/Desktop/Keyboard/top.v".
        div = 50000
    Found 128-bit register for signal <data>.
    Summary:
    inferred 128 D-type flip-flop(s).
Unit <top> synthesized.

Synthesizing Unit <Keyboard2>.
    Related source file is "/home/ise/Desktop/Keyboard/Keyboard2.v".
    Found 11-bit register for signal <shr>.
    Found 4-bit register for signal <counter>.
    Found 8-bit register for signal <tmp>.
    Found 2-bit register for signal <temp>.
    Found 4-bit adder for signal <counter[3]_GND_2_o_add_4_OUT> created at line 37.
    Summary:
    inferred   1 Adder/Subtractor(s).
    inferred  25 D-type flip-flop(s).
    inferred   1 Multiplexer(s).
Unit <Keyboard2> synthesized.

Synthesizing Unit <decoder>.
    Related source file is "/home/ise/Desktop/Keyboard/decoder.v".
WARNING:Xst:647 - Input <data<7:7>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:2999 - Signal 'ROmem', unconnected in block 'decoder', is tied to its initial value.
WARNING:Xst:3035 - Index value(s) does not match array range for signal <ROmem>, simulation mismatch.
    Found 80x8-bit single-port Read Only RAM <Mram_ROmem> for signal <ROmem>.
    Found 8-bit register for signal <ascii>.
    Summary:
    inferred   1 RAM(s).
    inferred   8 D-type flip-flop(s).
Unit <decoder> synthesized.

Synthesizing Unit <LCD_driver>.
    Related source file is "/home/ise/Desktop/Keyboard/LCD_driver.v".
        div = 50000
    Summary:
    no macro.
Unit <LCD_driver> synthesized.

Synthesizing Unit <LCD_controller>.
    Related source file is "/home/ise/Desktop/Keyboard/LCD_controller.v".
    Summary:
    no macro.
Unit <LCD_controller> synthesized.

Synthesizing Unit <main_controller>.
    Related source file is "/home/ise/Desktop/Keyboard/main_controller.v".
    Set property "fsm_encoding = user" for signal <st>.
    Set property "fsm_encoding = user" for signal <nst>.
    Found 3-bit register for signal <st>.
    Found finite state machine <FSM_0> for signal <st>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 15                                             |
    | Inputs             | 2                                              |
    | Outputs            | 4                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | rst (positive)                                 |
    | Reset type         | asynchronous                                   |
    | Reset State        | 000                                            |
    | Encoding           | user                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Summary:
    inferred   1 Finite State Machine(s).
Unit <main_controller> synthesized.

Synthesizing Unit <write_cycle>.
    Related source file is "/home/ise/Desktop/Keyboard/write_cycle.v".
    Set property "fsm_encoding = user" for signal <st>.
    Set property "fsm_encoding = user" for signal <nst>.
    Found 2-bit register for signal <st>.
    Found finite state machine <FSM_1> for signal <st>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 9                                              |
    | Inputs             | 2                                              |
    | Outputs            | 2                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | rst (positive)                                 |
    | Reset type         | asynchronous                                   |
    | Reset State        | 00                                             |
    | Encoding           | user                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Summary:
    inferred   1 Finite State Machine(s).
Unit <write_cycle> synthesized.

Synthesizing Unit <lcd_init_refresh>.
    Related source file is "/home/ise/Desktop/Keyboard/lcd_init_refresh.v".
    Set property "fsm_encoding = user" for signal <st>.
    Set property "fsm_encoding = user" for signal <nst>.
    Found 2-bit register for signal <init_sel>.
    Found 2-bit register for signal <st>.
    Found 4-bit register for signal <mux_sel>.
    Found finite state machine <FSM_2> for signal <st>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 11                                             |
    | Inputs             | 4                                              |
    | Outputs            | 3                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | rst (positive)                                 |
    | Reset type         | asynchronous                                   |
    | Reset State        | 00                                             |
    | Encoding           | user                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 2-bit subtractor for signal <GND_8_o_GND_8_o_sub_14_OUT<1:0>> created at line 64.
    Found 4-bit subtractor for signal <GND_8_o_GND_8_o_sub_23_OUT<3:0>> created at line 73.
    Summary:
    inferred   2 Adder/Subtractor(s).
    inferred   6 D-type flip-flop(s).
    inferred   3 Multiplexer(s).
    inferred   1 Finite State Machine(s).
Unit <lcd_init_refresh> synthesized.

Synthesizing Unit <lcd_dp>.
    Related source file is "/home/ise/Desktop/Keyboard/lcd_dp.v".
    Found 8-bit 16-to-1 multiplexer for signal <counter_mux> created at line 43.
    Summary:
    inferred   3 Multiplexer(s).
Unit <lcd_dp> synthesized.

Synthesizing Unit <clk_divider>.
    Related source file is "/home/ise/Desktop/Keyboard/clk_divider.v".
        div = 50000
    Found 16-bit register for signal <cnt>.
    Found 1-bit register for signal <clk_slow>.
    Found 16-bit adder for signal <cnt[15]_GND_10_o_add_1_OUT> created at line 46.
    Summary:
    inferred   1 Adder/Subtractor(s).
    inferred  17 D-type flip-flop(s).
    inferred   1 Multiplexer(s).
Unit <clk_divider> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# RAMs                                                 : 1
 80x8-bit single-port Read Only RAM                    : 1
# Adders/Subtractors                                   : 4
 16-bit adder                                          : 1
 2-bit subtractor                                      : 1
 4-bit adder                                           : 1
 4-bit subtractor                                      : 1
# Registers                                            : 10
 1-bit register                                        : 1
 11-bit register                                       : 1
 128-bit register                                      : 1
 16-bit register                                       : 1
 2-bit register                                        : 2
 4-bit register                                        : 2
 8-bit register                                        : 2
# Multiplexers                                         : 8
 1-bit 2-to-1 multiplexer                              : 1
 16-bit 2-to-1 multiplexer                             : 1
 2-bit 2-to-1 multiplexer                              : 1
 4-bit 2-to-1 multiplexer                              : 2
 8-bit 16-to-1 multiplexer                             : 1
 8-bit 2-to-1 multiplexer                              : 2
# FSMs                                                 : 3

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

WARNING:Xst:2677 - Node <shr_0> of sequential type is unconnected in block <keyboardInstance>.

Synthesizing (advanced) Unit <Keyboard2>.
The following registers are absorbed into counter <counter>: 1 register on signal <counter>.
Unit <Keyboard2> synthesized (advanced).

Synthesizing (advanced) Unit <clk_divider>.
The following registers are absorbed into counter <cnt>: 1 register on signal <cnt>.
Unit <clk_divider> synthesized (advanced).

Synthesizing (advanced) Unit <decoder>.
INFO:Xst:3226 - The RAM <Mram_ROmem> will be implemented as a BLOCK RAM, absorbing the following register(s): <ascii>
    -----------------------------------------------------------------------
    | ram_type           | Block                               |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 80-word x 8-bit                     |          |
    |     mode           | write-first                         |          |
    |     clkA           | connected to signal <clk>           | rise     |
    |     enA            | connected to signal <ready>         | high     |
    |     weA            | connected to signal <GND>           | high     |
    |     addrA          | connected to signal <data>          |          |
    |     diA            | connected to signal <GND>           |          |
    |     doA            | connected to signal <ascii>         |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
Unit <decoder> synthesized (advanced).
WARNING:Xst:2677 - Node <shr_0> of sequential type is unconnected in block <Keyboard2>.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# RAMs                                                 : 1
 80x8-bit single-port block Read Only RAM              : 1
# Adders/Subtractors                                   : 2
 2-bit subtractor                                      : 1
 4-bit subtractor                                      : 1
# Counters                                             : 2
 16-bit up counter                                     : 1
 4-bit up counter                                      : 1
# Registers                                            : 155
 Flip-Flops                                            : 155
# Multiplexers                                         : 5
 2-bit 2-to-1 multiplexer                              : 1
 4-bit 2-to-1 multiplexer                              : 1
 8-bit 16-to-1 multiplexer                             : 1
 8-bit 2-to-1 multiplexer                              : 2
# FSMs                                                 : 3

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Optimizing FSM <FSM_0> on signal <st[1:3]> with user encoding.
-------------------
 State | Encoding
-------------------
 000   | 000
 001   | 001
 011   | 011
 111   | 111
 100   | 100
 110   | 110
-------------------
Optimizing FSM <FSM_1> on signal <st[1:2]> with user encoding.
-------------------
 State | Encoding
-------------------
 00    | 00
 01    | 01
 11    | 11
 10    | 10
-------------------
Optimizing FSM <lcdDriverInst/LcdContr_init/lcdIR_init/FSM_2> on signal <st[1:2]> with user encoding.
-------------------
 State | Encoding
-------------------
 00    | 00
 01    | 01
 11    | 11
 10    | 10
-------------------

Optimizing unit <top> ...

Optimizing unit <Keyboard2> ...

Optimizing unit <lcd_dp> ...

Optimizing unit <lcd_init_refresh> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block top, actual ratio is 13.

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 182
 Flip-Flops                                            : 182

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Design Summary                             *
=========================================================================

Top Level Output File Name         : top.ngc

Primitive and Black Box Usage:
------------------------------
# BELS                             : 171
#      GND                         : 1
#      INV                         : 2
#      LUT1                        : 15
#      LUT2                        : 20
#      LUT3                        : 4
#      LUT4                        : 9
#      LUT5                        : 10
#      LUT6                        : 53
#      MUXCY                       : 15
#      MUXF7                       : 17
#      MUXF8                       : 8
#      VCC                         : 1
#      XORCY                       : 16
# FlipFlops/Latches                : 182
#      FDC                         : 24
#      FDCE                        : 46
#      FDPE                        : 112
# RAMS                             : 1
#      RAMB8BWER                   : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 31
#      IBUF                        : 3
#      OBUF                        : 28

Device utilization summary:
---------------------------

Selected Device : xa6slx4csg225-3


Slice Logic Utilization:
 Number of Slice Registers:             182  out of   4800     3%
 Number of Slice LUTs:                  113  out of   2400     4%
    Number used as Logic:               113  out of   2400     4%

Slice Logic Distribution:
 Number of LUT Flip Flop pairs used:    225
   Number with an unused Flip Flop:      43  out of    225    19%
   Number with an unused LUT:           112  out of    225    49%
   Number of fully used LUT-FF pairs:    70  out of    225    31%
   Number of unique control sets:         9

IO Utilization:
 Number of IOs:                          32
 Number of bonded IOBs:                  32  out of    132    24%

Specific Feature Utilization:
 Number of Block RAM/FIFO:                1  out of     12     8%
    Number using Block RAM only:          1
 Number of BUFG/BUFGCTRLs:                1  out of     16     6%

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
Timing Report

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 183   |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -3

   Minimum period: 4.357ns (Maximum Frequency: 229.524MHz)
   Minimum input arrival time before clock: 3.689ns
   Maximum output required time after clock: 6.863ns
   Maximum combinational path delay: No path found

Timing Details:
---------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 4.357ns (frequency: 229.524MHz)
  Total number of paths / destination ports: 2343 / 346
-------------------------------------------------------------------------
Delay:               4.357ns (Levels of Logic = 2)
  Source:            keyboardInstance/counter_2 (FF)
  Destination:       data_0 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: keyboardInstance/counter_2 to data_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             4   0.447   0.931  keyboardInstance/counter_2 (keyboardInstance/counter_2)
     LUT4:I0->O           14   0.203   0.958  keyboardInstance/rdy<3>1 (TRIG_ARR_OBUF)
     LUT6:I5->O           32   0.205   1.291  TRIG_ARR_LED[7]_AND_2_o (TRIG_ARR_LED[7]_AND_2_o)
     FDCE:CE                   0.322          data_0
    ----------------------------------------
    Total                      4.357ns (1.177ns logic, 3.180ns route)
                                       (27.0% logic, 73.0% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 184 / 184
-------------------------------------------------------------------------
Offset:              3.689ns (Levels of Logic = 1)
  Source:            rst (PAD)
  Destination:       data_0 (FF)
  Destination Clock: clk rising

  Data Path: rst to data_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O           182   1.222   2.037  rst_IBUF (rst_IBUF)
     FDCE:CLR                  0.430          data_0
    ----------------------------------------
    Total                      3.689ns (1.652ns logic, 2.037ns route)
                                       (44.8% logic, 55.2% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 275 / 27
-------------------------------------------------------------------------
Offset:              6.863ns (Levels of Logic = 5)
  Source:            lcdDriverInst/LcdContr_init/lcdIR_init/mux_sel_1 (FF)
  Destination:       DB<7> (PAD)
  Source Clock:      clk rising

  Data Path: lcdDriverInst/LcdContr_init/lcdIR_init/mux_sel_1 to DB<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q            38   0.447   1.741  lcdDriverInst/LcdContr_init/lcdIR_init/mux_sel_1 (lcdDriverInst/LcdContr_init/lcdIR_init/mux_sel_1)
     LUT6:I0->O            1   0.203   0.000  lcdDriverInst/LcdDp_init/Mmux_counter_mux_4 (lcdDriverInst/LcdDp_init/Mmux_counter_mux_4)
     MUXF7:I1->O           1   0.140   0.000  lcdDriverInst/LcdDp_init/Mmux_counter_mux_3_f7 (lcdDriverInst/LcdDp_init/Mmux_counter_mux_3_f7)
     MUXF8:I1->O           1   0.152   0.827  lcdDriverInst/LcdDp_init/Mmux_counter_mux_2_f8 (lcdDriverInst/LcdDp_init/counter_mux<0>)
     LUT6:I2->O            1   0.203   0.579  lcdDriverInst/LcdDp_init/Mmux_out11 (DB_0_OBUF)
     OBUF:I->O                 2.571          DB_0_OBUF (DB<0>)
    ----------------------------------------
    Total                      6.863ns (3.716ns logic, 3.147ns route)
                                       (54.1% logic, 45.9% route)

=========================================================================

Cross Clock Domains Report:
--------------------------

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    4.357|         |         |         |
---------------+---------+---------+---------+---------+

=========================================================================


Total REAL time to Xst completion: 42.00 secs
Total CPU time to Xst completion: 39.67 secs

-->


Total memory usage is 482456 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    8 (   0 filtered)
Number of infos    :    1 (   0 filtered)