vga.sv 4 3032a

`include "../Headers/vga.svh"

module vga (

    input logic clk108MHz,  // Input clock
    input logic resetn,     // Global reset - active negative

    output logic hsync,
    output logic vsync,

    output logic red,
    output logic green,
    output logic blue

);


    // Video Enables
    logic video_en,
          horizontal_en,
          vertical_en;

    // Color Signals
    logic red_signal,
          green_signal,
          blue_signal;

    //Sync Counters
    logic `CNT_RNG h_cnt,
                   v_cnt;

    assign video_en = horizontal_en & vertical_en;

    always_ff @(posedge clk108MHz) begin

        // -----------------  Horizontal Sync ---------------

        // Horizontal Counter
        h_cnt <= !resetn || h_cnt == `WHOLE_LINE_PXLS - 1 ? '0 : h_cnt + 1'b1;

        // Generate Horizontal Data

        `ifdef RGB

            // Rows Of Red
            if (v_cnt >= 0 && v_cnt < `FIRST_HORIZ_BORDER_PXLS) begin
                red_signal   <= 1'b1;
                green_signal <= 1'b0;
                blue_signal  <= 1'b0;
            end;

            // Rows Of Green
            if (v_cnt >= `FIRST_HORIZ_BORDER_PXLS && v_cnt < `SECOND_HORIZ_BORDER_PXLS) begin
                red_signal   <= 1'b0;
                green_signal <= 1'b1;
                blue_signal  <= 1'b0;
            end;

            // Rows Of Blue
            if (v_cnt >= `SECOND_HORIZ_BORDER_PXLS && v_cnt <= `VISIBLE_FRAME_PXLS) begin
                red_signal   <= 1'b0;
                green_signal <= 1'b0;
                blue_signal  <= 1'b1;
            end;

        `else

            red_signal   <= 1'b1;
            green_signal <= 1'b1;
            blue_signal  <= 1'b1;

        `endif

        // Generate Horizontal Sync
        hsync <= h_cnt >= `HORIZ_SYNC_PRE_PXLS && h_cnt <= `HORIZ_SYNC_POST_PXLS;

        // -----------------  Vertical Sync ---------------

        // Reset Vertical Counter

        v_cnt <= !resetn ||
                 v_cnt == `VERT_FRAME_PXLS - 1'b1 &&
                 h_cnt == `WHOLE_LINE_PXLS - 1'b1 ? '0 :
                 h_cnt == `WHOLE_LINE_PXLS - 1'b1 ?
                 v_cnt + 1'b1 :
                 v_cnt;

        // Generate Vertical Sync
        vsync <= v_cnt > `VERT_SYNC_PRE_PXLS && v_cnt < `VERT_SYNC_POST_PXLS;

        // Generate Horizontal Enable
        horizontal_en <= h_cnt < `VISIBLE_LINE_PXLS;

        // Generate Vertical Enable
        vertical_en <= v_cnt < `VISIBLE_FRAME_PXLS;

        // Assign Physical Signals To VGA
        red   <= red_signal   & video_en;
        green <= green_signal & video_en;
        blue  <= blue_signal  & video_en;

    end // always_ff @(posedge clk108MHz) begin

endmodule : vga