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Jun 6th, 2017
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  1. /dts-v1/;
  2.  
  3. / {
  4. #address-cells = <0x1>;
  5. #size-cells = <0x1>;
  6. compatible = "rockchip,rk3288";
  7. rockchip,sram = <0x1>;
  8. interrupt-parent = <0x2>;
  9.  
  10. chosen {
  11. };
  12.  
  13. aliases {
  14. serial0 = "/serial@ff180000";
  15. serial1 = "/serial@ff190000";
  16. serial2 = "/serial@ff690000";
  17. serial3 = "/serial@ff1b0000";
  18. serial4 = "/serial@ff1c0000";
  19. i2c0 = "/i2c@ff650000";
  20. i2c1 = "/i2c@ff140000";
  21. i2c2 = "/i2c@ff660000";
  22. i2c3 = "/i2c@ff150000";
  23. i2c4 = "/i2c@ff160000";
  24. i2c5 = "/i2c@ff170000";
  25. lcdc0 = "/lcdc@ff930000";
  26. lcdc1 = "/lcdc@ff940000";
  27. spi0 = "/spi@ff110000";
  28. spi1 = "/spi@ff120000";
  29. spi2 = "/spi@ff130000";
  30. };
  31.  
  32. memory {
  33. device_type = "memory";
  34. reg = <0x0 0x0>;
  35. };
  36.  
  37. pinctrl@ff770000 {
  38. compatible = "rockchip,rk3288-pinctrl";
  39. reg = <0xff770000 0x140 0xff770140 0x80 0xff7701c0 0x80>;
  40. reg-names = "base", "pull", "drv";
  41. #address-cells = <0x1>;
  42. #size-cells = <0x1>;
  43. ranges;
  44. init-gpios = <0x3 0x1 0x0 0x4 0x9 0x0 0x5 0x8 0x0>;
  45.  
  46. gpio0@ff750000 {
  47. compatible = "rockchip,rk3288-gpio-bank0";
  48. reg = <0xff750000 0x100 0xff730084 0xc 0xff730064 0xc 0xff730070 0xc>;
  49. reg-names = "base", "mux_bank0", "pull_bank0", "drv_bank0";
  50. interrupts = <0x0 0x51 0x4>;
  51. clocks = <0x6 0x4>;
  52. gpio-controller;
  53. #gpio-cells = <0x2>;
  54. interrupt-controller;
  55. #interrupt-cells = <0x2>;
  56. linux,phandle = <0x95>;
  57. phandle = <0x95>;
  58. };
  59.  
  60. gpio1@ff780000 {
  61. compatible = "rockchip,gpio-bank";
  62. reg = <0xff780000 0x100>;
  63. interrupts = <0x0 0x52 0x4>;
  64. clocks = <0x7 0x1>;
  65. gpio-controller;
  66. #gpio-cells = <0x2>;
  67. interrupt-controller;
  68. #interrupt-cells = <0x2>;
  69. };
  70.  
  71. gpio2@ff790000 {
  72. compatible = "rockchip,gpio-bank";
  73. reg = <0xff790000 0x100>;
  74. interrupts = <0x0 0x53 0x4>;
  75. clocks = <0x7 0x2>;
  76. gpio-controller;
  77. #gpio-cells = <0x2>;
  78. interrupt-controller;
  79. #interrupt-cells = <0x2>;
  80. linux,phandle = <0x96>;
  81. phandle = <0x96>;
  82. };
  83.  
  84. gpio3@ff7a0000 {
  85. compatible = "rockchip,gpio-bank";
  86. reg = <0xff7a0000 0x100>;
  87. interrupts = <0x0 0x54 0x4>;
  88. clocks = <0x7 0x3>;
  89. gpio-controller;
  90. #gpio-cells = <0x2>;
  91. interrupt-controller;
  92. #interrupt-cells = <0x2>;
  93. };
  94.  
  95. gpio4@ff7b0000 {
  96. compatible = "rockchip,gpio-bank";
  97. reg = <0xff7b0000 0x100>;
  98. interrupts = <0x0 0x55 0x4>;
  99. clocks = <0x7 0x4>;
  100. gpio-controller;
  101. #gpio-cells = <0x2>;
  102. interrupt-controller;
  103. #interrupt-cells = <0x2>;
  104. linux,phandle = <0x5>;
  105. phandle = <0x5>;
  106. };
  107.  
  108. gpio5@ff7c0000 {
  109. compatible = "rockchip,gpio-bank";
  110. reg = <0xff7c0000 0x100>;
  111. interrupts = <0x0 0x56 0x4>;
  112. clocks = <0x7 0x5>;
  113. gpio-controller;
  114. #gpio-cells = <0x2>;
  115. interrupt-controller;
  116. #interrupt-cells = <0x2>;
  117. };
  118.  
  119. gpio6@ff7d0000 {
  120. compatible = "rockchip,gpio-bank";
  121. reg = <0xff7d0000 0x100>;
  122. interrupts = <0x0 0x57 0x4>;
  123. clocks = <0x7 0x6>;
  124. gpio-controller;
  125. #gpio-cells = <0x2>;
  126. interrupt-controller;
  127. #interrupt-cells = <0x2>;
  128. linux,phandle = <0x81>;
  129. phandle = <0x81>;
  130. };
  131.  
  132. gpio7@ff7e0000 {
  133. compatible = "rockchip,gpio-bank";
  134. reg = <0xff7e0000 0x100>;
  135. interrupts = <0x0 0x58 0x4>;
  136. clocks = <0x7 0x7>;
  137. gpio-controller;
  138. #gpio-cells = <0x2>;
  139. interrupt-controller;
  140. #interrupt-cells = <0x2>;
  141. linux,phandle = <0x4>;
  142. phandle = <0x4>;
  143. };
  144.  
  145. gpio8@ff7f0000 {
  146. compatible = "rockchip,gpio-bank";
  147. reg = <0xff7f0000 0x100>;
  148. interrupts = <0x0 0x59 0x4>;
  149. clocks = <0x7 0x8>;
  150. gpio-controller;
  151. #gpio-cells = <0x2>;
  152. interrupt-controller;
  153. #interrupt-cells = <0x2>;
  154. linux,phandle = <0x3>;
  155. phandle = <0x3>;
  156. };
  157.  
  158. gpio15@ff7f2000 {
  159. compatible = "rockchip,gpio-bank";
  160. reg = <0xff7f2000 0x100>;
  161. interrupts = <0x0 0x7f 0x4>;
  162. clocks = <0x7 0x8>;
  163. gpio-controller;
  164. #gpio-cells = <0x2>;
  165. interrupt-controller;
  166. #interrupt-cells = <0x2>;
  167. };
  168.  
  169. pcfg_pull_up {
  170. bias-pull-up;
  171. };
  172.  
  173. pcfg_pull_down {
  174. bias-pull-down;
  175. };
  176.  
  177. pcfg_pull_none {
  178. bias-disable;
  179. };
  180.  
  181. gpio4_uart0 {
  182.  
  183. uart0-xfer {
  184. rockchip,pins = <0x4c01 0x4c11>;
  185. rockchip,pull = <0x4>;
  186. rockchip,drive = <0x0>;
  187. linux,phandle = <0x9f>;
  188. phandle = <0x9f>;
  189. };
  190.  
  191. uart0-cts {
  192. rockchip,pins = <0x4c21>;
  193. rockchip,pull = <0x4>;
  194. rockchip,drive = <0x0>;
  195. linux,phandle = <0xa0>;
  196. phandle = <0xa0>;
  197. };
  198.  
  199. uart0-rts {
  200. rockchip,pins = <0x4c31>;
  201. rockchip,pull = <0x4>;
  202. rockchip,drive = <0x0>;
  203. linux,phandle = <0x112>;
  204. phandle = <0x112>;
  205. };
  206.  
  207. uart0-rts-gpio {
  208. rockchip,pins = <0x4c30>;
  209. rockchip,drive = <0x0>;
  210. linux,phandle = <0x113>;
  211. phandle = <0x113>;
  212. };
  213. };
  214.  
  215. gpio5_uart1 {
  216.  
  217. uart1-xfer {
  218. rockchip,pins = <0x5b01 0x5b11>;
  219. rockchip,pull = <0x4>;
  220. rockchip,drive = <0x0>;
  221. linux,phandle = <0xa2>;
  222. phandle = <0xa2>;
  223. };
  224.  
  225. uart1-cts {
  226. rockchip,pins = <0x5b21>;
  227. rockchip,pull = <0x4>;
  228. rockchip,drive = <0x0>;
  229. linux,phandle = <0xa3>;
  230. phandle = <0xa3>;
  231. };
  232.  
  233. uart1-rts {
  234. rockchip,pins = <0x5b31>;
  235. rockchip,pull = <0x4>;
  236. rockchip,drive = <0x0>;
  237. linux,phandle = <0xa4>;
  238. phandle = <0xa4>;
  239. };
  240.  
  241. uart1-rts-gpio {
  242. rockchip,pins = <0x5b30>;
  243. rockchip,drive = <0x0>;
  244. };
  245. };
  246.  
  247. gpio7_uart2 {
  248.  
  249. uart2-xfer {
  250. rockchip,pins = <0x7c61 0x7c71>;
  251. rockchip,pull = <0x4>;
  252. rockchip,drive = <0x0>;
  253. linux,phandle = <0xa8>;
  254. phandle = <0xa8>;
  255. };
  256. };
  257.  
  258. gpio7_uart3 {
  259.  
  260. uart3-xfer {
  261. rockchip,pins = <0x7a71 0x7b01>;
  262. rockchip,pull = <0x4>;
  263. rockchip,drive = <0x0>;
  264. linux,phandle = <0xaa>;
  265. phandle = <0xaa>;
  266. };
  267.  
  268. uart3-cts {
  269. rockchip,pins = <0x7b11>;
  270. rockchip,pull = <0x4>;
  271. rockchip,drive = <0x0>;
  272. linux,phandle = <0xab>;
  273. phandle = <0xab>;
  274. };
  275.  
  276. uart3-rts {
  277. rockchip,pins = <0x7b21>;
  278. rockchip,pull = <0x4>;
  279. rockchip,drive = <0x0>;
  280. linux,phandle = <0xac>;
  281. phandle = <0xac>;
  282. };
  283. };
  284.  
  285. gpio5_uart4 {
  286.  
  287. uart4-xfer {
  288. rockchip,pins = <0x5b73 0x5b63>;
  289. rockchip,pull = <0x4>;
  290. rockchip,drive = <0x0>;
  291. linux,phandle = <0xae>;
  292. phandle = <0xae>;
  293. };
  294.  
  295. uart4-cts {
  296. rockchip,pins = <0x5b43>;
  297. rockchip,pull = <0x4>;
  298. rockchip,drive = <0x0>;
  299. linux,phandle = <0xaf>;
  300. phandle = <0xaf>;
  301. };
  302.  
  303. uart4-rts {
  304. rockchip,pins = <0x5b53>;
  305. rockchip,pull = <0x4>;
  306. rockchip,drive = <0x0>;
  307. linux,phandle = <0xb0>;
  308. phandle = <0xb0>;
  309. };
  310. };
  311.  
  312. gpio0_i2c0 {
  313.  
  314. i2c0-sda {
  315. rockchip,pins = <0xb71>;
  316. rockchip,pull = <0x4>;
  317. rockchip,drive = <0x0>;
  318. linux,phandle = <0xb7>;
  319. phandle = <0xb7>;
  320. };
  321.  
  322. i2c0-scl {
  323. rockchip,pins = <0xc01>;
  324. rockchip,pull = <0x4>;
  325. rockchip,drive = <0x0>;
  326. linux,phandle = <0xb8>;
  327. phandle = <0xb8>;
  328. };
  329.  
  330. i2c0-gpio {
  331. rockchip,pins = <0xb70 0xc00>;
  332. rockchip,drive = <0x0>;
  333. linux,phandle = <0xb9>;
  334. phandle = <0xb9>;
  335. };
  336. };
  337.  
  338. gpio8_i2c1 {
  339.  
  340. i2c1-sda {
  341. rockchip,pins = <0x8a41>;
  342. rockchip,pull = <0x4>;
  343. rockchip,drive = <0x0>;
  344. linux,phandle = <0xba>;
  345. phandle = <0xba>;
  346. };
  347.  
  348. i2c1-scl {
  349. rockchip,pins = <0x8a51>;
  350. rockchip,pull = <0x4>;
  351. rockchip,drive = <0x0>;
  352. linux,phandle = <0xbb>;
  353. phandle = <0xbb>;
  354. };
  355.  
  356. i2c1-gpio {
  357. rockchip,pins = <0x8a40 0x8a50>;
  358. rockchip,drive = <0x0>;
  359. linux,phandle = <0xbc>;
  360. phandle = <0xbc>;
  361. };
  362. };
  363.  
  364. gpio6_i2c2 {
  365.  
  366. i2c2-sda {
  367. rockchip,pins = <0x6b11>;
  368. rockchip,pull = <0x4>;
  369. rockchip,drive = <0x0>;
  370. linux,phandle = <0xbd>;
  371. phandle = <0xbd>;
  372. };
  373.  
  374. i2c2-scl {
  375. rockchip,pins = <0x6b21>;
  376. rockchip,pull = <0x4>;
  377. rockchip,drive = <0x0>;
  378. linux,phandle = <0xbe>;
  379. phandle = <0xbe>;
  380. };
  381.  
  382. i2c2-gpio {
  383. rockchip,pins = <0x6b10 0x6b20>;
  384. rockchip,drive = <0x0>;
  385. linux,phandle = <0xbf>;
  386. phandle = <0xbf>;
  387. };
  388. };
  389.  
  390. gpio2_i2c3 {
  391.  
  392. i2c3-sda {
  393. rockchip,pins = <0x2c11>;
  394. rockchip,pull = <0x4>;
  395. rockchip,drive = <0x0>;
  396. linux,phandle = <0xc0>;
  397. phandle = <0xc0>;
  398. };
  399.  
  400. i2c3-scl {
  401. rockchip,pins = <0x2c01>;
  402. rockchip,pull = <0x4>;
  403. rockchip,drive = <0x0>;
  404. linux,phandle = <0xc1>;
  405. phandle = <0xc1>;
  406. };
  407.  
  408. i2c3-gpio {
  409. rockchip,pins = <0x2c10 0x2c00>;
  410. rockchip,drive = <0x0>;
  411. linux,phandle = <0xc2>;
  412. phandle = <0xc2>;
  413. };
  414. };
  415.  
  416. gpio7_i2c4 {
  417.  
  418. i2c4-sda {
  419. rockchip,pins = <0x7c11>;
  420. rockchip,pull = <0x4>;
  421. rockchip,drive = <0x0>;
  422. linux,phandle = <0xc3>;
  423. phandle = <0xc3>;
  424. };
  425.  
  426. i2c4-scl {
  427. rockchip,pins = <0x7c21>;
  428. rockchip,pull = <0x4>;
  429. rockchip,drive = <0x0>;
  430. linux,phandle = <0xc4>;
  431. phandle = <0xc4>;
  432. };
  433.  
  434. i2c4-gpio {
  435. rockchip,pins = <0x7c10 0x7c20>;
  436. rockchip,drive = <0x0>;
  437. linux,phandle = <0xc5>;
  438. phandle = <0xc5>;
  439. };
  440. };
  441.  
  442. gpio7_i2c5 {
  443.  
  444. i2c5-sda {
  445. rockchip,pins = <0x7c32>;
  446. rockchip,pull = <0x0>;
  447. rockchip,drive = <0x0>;
  448. linux,phandle = <0xc6>;
  449. phandle = <0xc6>;
  450. };
  451.  
  452. i2c5-scl {
  453. rockchip,pins = <0x7c42>;
  454. rockchip,pull = <0x0>;
  455. rockchip,drive = <0x0>;
  456. linux,phandle = <0xc7>;
  457. phandle = <0xc7>;
  458. };
  459.  
  460. i2c5-gpio {
  461. rockchip,pins = <0x7c30 0x7c40>;
  462. rockchip,drive = <0x0>;
  463. linux,phandle = <0xc8>;
  464. phandle = <0xc8>;
  465. };
  466. };
  467.  
  468. gpio5_spi0 {
  469.  
  470. spi0-txd {
  471. rockchip,pins = <0x5b61>;
  472. rockchip,pull = <0x4>;
  473. rockchip,drive = <0x0>;
  474. linux,phandle = <0x8b>;
  475. phandle = <0x8b>;
  476. };
  477.  
  478. spi0-rxd {
  479. rockchip,pins = <0x5b71>;
  480. rockchip,pull = <0x4>;
  481. rockchip,drive = <0x0>;
  482. linux,phandle = <0x8c>;
  483. phandle = <0x8c>;
  484. };
  485.  
  486. spi0-clk {
  487. rockchip,pins = <0x5b41>;
  488. rockchip,pull = <0x4>;
  489. rockchip,drive = <0x0>;
  490. linux,phandle = <0x8d>;
  491. phandle = <0x8d>;
  492. };
  493.  
  494. spi0-cs0 {
  495. rockchip,pins = <0x5b51>;
  496. rockchip,pull = <0x4>;
  497. rockchip,drive = <0x0>;
  498. linux,phandle = <0x8e>;
  499. phandle = <0x8e>;
  500. };
  501.  
  502. spi0-cs1 {
  503. rockchip,pins = <0x5c01>;
  504. rockchip,pull = <0x4>;
  505. rockchip,drive = <0x0>;
  506. linux,phandle = <0x8f>;
  507. phandle = <0x8f>;
  508. };
  509. };
  510.  
  511. gpio7_spi1 {
  512.  
  513. spi1-txd {
  514. rockchip,pins = <0x7b72>;
  515. rockchip,pull = <0x4>;
  516. rockchip,drive = <0x0>;
  517. linux,phandle = <0x91>;
  518. phandle = <0x91>;
  519. };
  520.  
  521. spi1-rxd {
  522. rockchip,pins = <0x7b62>;
  523. rockchip,pull = <0x4>;
  524. rockchip,drive = <0x0>;
  525. linux,phandle = <0x92>;
  526. phandle = <0x92>;
  527. };
  528.  
  529. spi1-clk {
  530. rockchip,pins = <0x7b42>;
  531. rockchip,pull = <0x4>;
  532. rockchip,drive = <0x0>;
  533. linux,phandle = <0x93>;
  534. phandle = <0x93>;
  535. };
  536.  
  537. spi1-cs0 {
  538. rockchip,pins = <0x7b52>;
  539. rockchip,pull = <0x4>;
  540. rockchip,drive = <0x0>;
  541. linux,phandle = <0x94>;
  542. phandle = <0x94>;
  543. };
  544. };
  545.  
  546. gpio8_spi2 {
  547.  
  548. spi2-txd {
  549. rockchip,pins = <0x8b11>;
  550. rockchip,pull = <0x4>;
  551. rockchip,drive = <0x0>;
  552. linux,phandle = <0x97>;
  553. phandle = <0x97>;
  554. };
  555.  
  556. spi2-rxd {
  557. rockchip,pins = <0x8b01>;
  558. rockchip,pull = <0x4>;
  559. rockchip,drive = <0x0>;
  560. linux,phandle = <0x98>;
  561. phandle = <0x98>;
  562. };
  563.  
  564. spi2-clk {
  565. rockchip,pins = <0x8a61>;
  566. rockchip,pull = <0x4>;
  567. rockchip,drive = <0x0>;
  568. linux,phandle = <0x99>;
  569. phandle = <0x99>;
  570. };
  571.  
  572. spi2-cs0 {
  573. rockchip,pins = <0x8a71>;
  574. rockchip,pull = <0x4>;
  575. rockchip,drive = <0x0>;
  576. linux,phandle = <0x9a>;
  577. phandle = <0x9a>;
  578. };
  579.  
  580. spi2-cs1 {
  581. rockchip,pins = <0x8a31>;
  582. rockchip,pull = <0x4>;
  583. rockchip,drive = <0x0>;
  584. linux,phandle = <0x9b>;
  585. phandle = <0x9b>;
  586. };
  587. };
  588.  
  589. gpio6_i2s {
  590.  
  591. i2s-mclk {
  592. rockchip,pins = <0x6b01>;
  593. rockchip,pull = <0x4>;
  594. rockchip,drive = <0x0>;
  595. linux,phandle = <0xd1>;
  596. phandle = <0xd1>;
  597. };
  598.  
  599. i2s-sclk {
  600. rockchip,pins = <0x6a01>;
  601. rockchip,pull = <0x4>;
  602. rockchip,drive = <0x0>;
  603. linux,phandle = <0xd2>;
  604. phandle = <0xd2>;
  605. };
  606.  
  607. i2s-lrckrx {
  608. rockchip,pins = <0x6a11>;
  609. rockchip,pull = <0x4>;
  610. rockchip,drive = <0x0>;
  611. linux,phandle = <0xd3>;
  612. phandle = <0xd3>;
  613. };
  614.  
  615. i2s-lrcktx {
  616. rockchip,pins = <0x6a21>;
  617. rockchip,pull = <0x4>;
  618. rockchip,drive = <0x0>;
  619. linux,phandle = <0xd4>;
  620. phandle = <0xd4>;
  621. };
  622.  
  623. i2s-sdo0 {
  624. rockchip,pins = <0x6a41>;
  625. rockchip,pull = <0x4>;
  626. rockchip,drive = <0x0>;
  627. linux,phandle = <0xd6>;
  628. phandle = <0xd6>;
  629. };
  630.  
  631. i2s-sdo1 {
  632. rockchip,pins = <0x6a51>;
  633. rockchip,pull = <0x4>;
  634. rockchip,drive = <0x0>;
  635. linux,phandle = <0xd7>;
  636. phandle = <0xd7>;
  637. };
  638.  
  639. i2s-sdo2 {
  640. rockchip,pins = <0x6a61>;
  641. rockchip,pull = <0x4>;
  642. rockchip,drive = <0x0>;
  643. linux,phandle = <0xd8>;
  644. phandle = <0xd8>;
  645. };
  646.  
  647. i2s-sdo3 {
  648. rockchip,pins = <0x6a71>;
  649. rockchip,pull = <0x4>;
  650. rockchip,drive = <0x0>;
  651. linux,phandle = <0xd9>;
  652. phandle = <0xd9>;
  653. };
  654.  
  655. i2s-sdi {
  656. rockchip,pins = <0x6a31>;
  657. rockchip,pull = <0x4>;
  658. rockchip,drive = <0x0>;
  659. linux,phandle = <0xd5>;
  660. phandle = <0xd5>;
  661. };
  662.  
  663. i2s-gpio {
  664. rockchip,pins = <0x6b00 0x6a00 0x6a10 0x6a20 0x6a40 0x6a50 0x6a60 0x6a70 0x6a30>;
  665. rockchip,drive = <0x0>;
  666. linux,phandle = <0xda>;
  667. phandle = <0xda>;
  668. };
  669. };
  670.  
  671. gpio1_lcdc0 {
  672.  
  673. lcdc0-lcdc {
  674. rockchip,pins = <0x1d31 0x1d21 0x1d01 0x1d11>;
  675. rockchip,pull = <0x4>;
  676. rockchip,drive = <0x0>;
  677. linux,phandle = <0xcd>;
  678. phandle = <0xcd>;
  679. };
  680.  
  681. lcdc0-gpio {
  682. rockchip,pins = <0x1d30 0x1d20 0x1d00 0x1d10>;
  683. rockchip,pull = <0x4>;
  684. rockchip,drive = <0x0>;
  685. linux,phandle = <0xce>;
  686. phandle = <0xce>;
  687. };
  688. };
  689.  
  690. gpio6_spdif {
  691.  
  692. spdif-tx {
  693. rockchip,pins = <0x6b31>;
  694. rockchip,pull = <0x4>;
  695. rockchip,drive = <0x0>;
  696. linux,phandle = <0xdb>;
  697. phandle = <0xdb>;
  698. };
  699.  
  700. spdif-gpio {
  701. rockchip,pins = <0x6b30>;
  702. rockchip,drive = <0x0>;
  703. linux,phandle = <0xdc>;
  704. phandle = <0xdc>;
  705. };
  706. };
  707.  
  708. gpio7_pwm {
  709.  
  710. vop0-pwm {
  711. rockchip,pins = <0x7a02>;
  712. rockchip,pull = <0x4>;
  713. rockchip,drive = <0x0>;
  714. linux,phandle = <0xde>;
  715. phandle = <0xde>;
  716. };
  717.  
  718. vop1-pwm {
  719. rockchip,pins = <0x7a03>;
  720. rockchip,pull = <0x4>;
  721. rockchip,drive = <0x0>;
  722. linux,phandle = <0xdd>;
  723. phandle = <0xdd>;
  724. };
  725.  
  726. pwm0 {
  727. rockchip,pins = <0x7a01>;
  728. rockchip,pull = <0x4>;
  729. rockchip,drive = <0x0>;
  730. linux,phandle = <0xdf>;
  731. phandle = <0xdf>;
  732. };
  733.  
  734. pwm1 {
  735. rockchip,pins = <0x7a11>;
  736. rockchip,pull = <0x4>;
  737. rockchip,drive = <0x0>;
  738. linux,phandle = <0xe0>;
  739. phandle = <0xe0>;
  740. };
  741.  
  742. pwm2 {
  743. rockchip,pins = <0x7c63>;
  744. rockchip,pull = <0x4>;
  745. rockchip,drive = <0x0>;
  746. linux,phandle = <0xe1>;
  747. phandle = <0xe1>;
  748. };
  749.  
  750. pwm3 {
  751. rockchip,pins = <0x7c73>;
  752. rockchip,pull = <0x4>;
  753. rockchip,drive = <0x0>;
  754. linux,phandle = <0xe2>;
  755. phandle = <0xe2>;
  756. };
  757. };
  758.  
  759. gpio3_emmc0 {
  760.  
  761. emmc0-clk {
  762. rockchip,pins = <0x3c22>;
  763. rockchip,pull = <0x4>;
  764. rockchip,drive = <0x2>;
  765. };
  766.  
  767. emmc0-cmd {
  768. rockchip,pins = <0x3c02>;
  769. rockchip,pull = <0x1>;
  770. rockchip,drive = <0x2>;
  771. };
  772.  
  773. emmc0-rstnout {
  774. rockchip,pins = <0x3c12>;
  775. rockchip,pull = <0x1>;
  776. rockchip,drive = <0x2>;
  777. };
  778.  
  779. emmc0-pwr {
  780. rockchip,pins = <0x3b12>;
  781. rockchip,pull = <0x4>;
  782. rockchip,drive = <0x0>;
  783. };
  784.  
  785. emmc0-bus-width1 {
  786. rockchip,pins = <0x3a02>;
  787. rockchip,pull = <0x1>;
  788. rockchip,drive = <0x2>;
  789. };
  790.  
  791. emmc0-bus-width4 {
  792. rockchip,pins = <0x3a02 0x3a12 0x3a22 0x3a32>;
  793. rockchip,pull = <0x1>;
  794. rockchip,drive = <0x2>;
  795. };
  796. };
  797.  
  798. gpio6_sdmmc0 {
  799.  
  800. sdmmc0-clk {
  801. rockchip,pins = <0x6c41>;
  802. rockchip,pull = <0x4>;
  803. rockchip,drive = <0x1>;
  804. linux,phandle = <0x7c>;
  805. phandle = <0x7c>;
  806. };
  807.  
  808. sdmmc0-cmd {
  809. rockchip,pins = <0x6c51>;
  810. rockchip,pull = <0x1>;
  811. rockchip,drive = <0x1>;
  812. linux,phandle = <0x7d>;
  813. phandle = <0x7d>;
  814. };
  815.  
  816. sdmmc0-dectn {
  817. rockchip,pins = <0x6c61>;
  818. rockchip,pull = <0x1>;
  819. rockchip,drive = <0x1>;
  820. linux,phandle = <0x7e>;
  821. phandle = <0x7e>;
  822. };
  823.  
  824. sdmmc0-bus-width1 {
  825. rockchip,pins = <0x6c01>;
  826. rockchip,pull = <0x1>;
  827. rockchip,drive = <0x1>;
  828. };
  829.  
  830. sdmmc0-bus-width4 {
  831. rockchip,pins = <0x6c01 0x6c11 0x6c21 0x6c31>;
  832. rockchip,pull = <0x1>;
  833. rockchip,drive = <0x1>;
  834. linux,phandle = <0x7f>;
  835. phandle = <0x7f>;
  836. };
  837.  
  838. sdmmc0_gpio {
  839. rockchip,pins = <0x6c40 0x6c50 0x6c60 0x6c00 0x6c10 0x6c20 0x6c30>;
  840. rockchip,pull = <0x1>;
  841. rockchip,drive = <0x1>;
  842. linux,phandle = <0x80>;
  843. phandle = <0x80>;
  844. };
  845. };
  846.  
  847. gpio4_sdio0 {
  848.  
  849. sdio0_clk {
  850. rockchip,pins = <0x4d11>;
  851. rockchip,pull = <0x4>;
  852. rockchip,drive = <0x1>;
  853. linux,phandle = <0x83>;
  854. phandle = <0x83>;
  855. };
  856.  
  857. sdio0_cmd {
  858. rockchip,pins = <0x4d01>;
  859. rockchip,pull = <0x1>;
  860. rockchip,drive = <0x1>;
  861. linux,phandle = <0x84>;
  862. phandle = <0x84>;
  863. };
  864.  
  865. sdio0-dectn {
  866. rockchip,pins = <0x4d21>;
  867. rockchip,pull = <0x1>;
  868. rockchip,drive = <0x0>;
  869. };
  870.  
  871. sdio0_wrprt {
  872. rockchip,pins = <0x4d31>;
  873. rockchip,pull = <0x1>;
  874. rockchip,drive = <0x0>;
  875. linux,phandle = <0x85>;
  876. phandle = <0x85>;
  877. };
  878.  
  879. sdio0-pwren {
  880. rockchip,pins = <0x4d41>;
  881. rockchip,pull = <0x1>;
  882. rockchip,drive = <0x0>;
  883. linux,phandle = <0x86>;
  884. phandle = <0x86>;
  885. };
  886.  
  887. sdio0-bkpwr {
  888. rockchip,pins = <0x4d51>;
  889. rockchip,pull = <0x1>;
  890. rockchip,drive = <0x0>;
  891. linux,phandle = <0x87>;
  892. phandle = <0x87>;
  893. };
  894.  
  895. sdio0-intn {
  896. rockchip,pins = <0x4d61>;
  897. rockchip,pull = <0x1>;
  898. rockchip,drive = <0x0>;
  899. linux,phandle = <0x88>;
  900. phandle = <0x88>;
  901. };
  902.  
  903. sdio0-bus-width1 {
  904. rockchip,pins = <0x4c41>;
  905. rockchip,pull = <0x1>;
  906. rockchip,drive = <0x1>;
  907. };
  908.  
  909. sdio0-bus-width4 {
  910. rockchip,pins = <0x4c41 0x4c51 0x4c61 0x4c71>;
  911. rockchip,pull = <0x1>;
  912. rockchip,drive = <0x1>;
  913. linux,phandle = <0x89>;
  914. phandle = <0x89>;
  915. };
  916.  
  917. sdio0-all-gpio {
  918. rockchip,pins = <0x4d10 0x4d00 0x4d20 0x4d30 0x4d40 0x4d50 0x4d60 0x4c40 0x4c50 0x4c60 0x4c70>;
  919. rockchip,pull = <0x1>;
  920. rockchip,drive = <0x1>;
  921. linux,phandle = <0x8a>;
  922. phandle = <0x8a>;
  923. };
  924. };
  925.  
  926. gpio2_gps {
  927.  
  928. gps-mag {
  929. rockchip,pins = <0x7a72>;
  930. rockchip,pull = <0x4>;
  931. rockchip,drive = <0x0>;
  932. };
  933.  
  934. gps-sig {
  935. rockchip,pins = <0x7b02>;
  936. rockchip,pull = <0x4>;
  937. rockchip,drive = <0x0>;
  938. };
  939.  
  940. gps-rfclk {
  941. rockchip,pins = <0x7b12>;
  942. rockchip,pull = <0x4>;
  943. rockchip,drive = <0x0>;
  944. };
  945. };
  946.  
  947. gpio4_gmac {
  948.  
  949. mac-clk {
  950. rockchip,pins = <0x4a33>;
  951. rockchip,pull = <0x4>;
  952. rockchip,drive = <0x3>;
  953. linux,phandle = <0xe6>;
  954. phandle = <0xe6>;
  955. };
  956.  
  957. mac-txpins {
  958. rockchip,pins = <0x3d43 0x3d53 0x3d03 0x3d13 0x4a43 0x4b13>;
  959. rockchip,pull = <0x4>;
  960. rockchip,drive = <0x3>;
  961. linux,phandle = <0xe7>;
  962. phandle = <0xe7>;
  963. };
  964.  
  965. mac-rxpins {
  966. rockchip,pins = <0x3d63 0x3d73 0x3d23 0x3d33 0x4a13 0x4a23 0x4a63 0x4b03>;
  967. rockchip,pull = <0x4>;
  968. rockchip,drive = <0x3>;
  969. linux,phandle = <0xe8>;
  970. phandle = <0xe8>;
  971. };
  972.  
  973. mac-crs {
  974. rockchip,pins = <0x4a73>;
  975. rockchip,pull = <0x4>;
  976. rockchip,drive = <0x3>;
  977. };
  978.  
  979. mac-mdpins {
  980. rockchip,pins = <0x4a53 0x4a03>;
  981. rockchip,pull = <0x4>;
  982. rockchip,drive = <0x3>;
  983. linux,phandle = <0xe9>;
  984. phandle = <0xe9>;
  985. };
  986. };
  987.  
  988. gpio7_cec {
  989.  
  990. hdmi-cec {
  991. rockchip,pins = <0x7c02>;
  992. rockchip,pull = <0x0>;
  993. rockchip,drive = <0x0>;
  994. linux,phandle = <0xcb>;
  995. phandle = <0xcb>;
  996. };
  997.  
  998. hdmi-cec-gpio {
  999. rockchip,pins = <0x7c00>;
  1000. rockchip,pull = <0x4>;
  1001. rockchip,drive = <0x0>;
  1002. };
  1003. };
  1004.  
  1005. vol_domain {
  1006.  
  1007. lcdc-vcc {
  1008. rockchip,pins = <0xfa00>;
  1009. rockchip,voltage = <0x0>;
  1010. linux,phandle = <0xf3>;
  1011. phandle = <0xf3>;
  1012. };
  1013.  
  1014. dvp-vcc {
  1015. rockchip,pins = <0xfa10>;
  1016. rockchip,voltage = <0x0>;
  1017. linux,phandle = <0xf6>;
  1018. phandle = <0xf6>;
  1019. };
  1020.  
  1021. flash0-vcc {
  1022. rockchip,pins = <0xfa20>;
  1023. rockchip,voltage = <0x0>;
  1024. linux,phandle = <0xf9>;
  1025. phandle = <0xf9>;
  1026. };
  1027.  
  1028. flash1-vcc {
  1029. rockchip,pins = <0xfa30>;
  1030. rockchip,voltage = <0x0>;
  1031. linux,phandle = <0xfc>;
  1032. phandle = <0xfc>;
  1033. };
  1034.  
  1035. wifi-vcc {
  1036. rockchip,pins = <0xfa40>;
  1037. rockchip,voltage = <0x0>;
  1038. linux,phandle = <0xff>;
  1039. phandle = <0xff>;
  1040. };
  1041.  
  1042. bb-vcc {
  1043. rockchip,pins = <0xfa50>;
  1044. rockchip,voltage = <0x0>;
  1045. linux,phandle = <0x102>;
  1046. phandle = <0x102>;
  1047. };
  1048.  
  1049. audio-vcc {
  1050. rockchip,pins = <0xfa60>;
  1051. rockchip,voltage = <0x0>;
  1052. linux,phandle = <0x105>;
  1053. phandle = <0x105>;
  1054. };
  1055.  
  1056. sdcard-vcc {
  1057. rockchip,pins = <0xfa70>;
  1058. rockchip,voltage = <0x0>;
  1059. linux,phandle = <0x10e>;
  1060. phandle = <0x10e>;
  1061. };
  1062.  
  1063. gpio30-vcc {
  1064. rockchip,pins = <0xfb00>;
  1065. rockchip,voltage = <0x0>;
  1066. linux,phandle = <0x108>;
  1067. phandle = <0x108>;
  1068. };
  1069.  
  1070. gpio1830-vcc {
  1071. rockchip,pins = <0xfb10>;
  1072. rockchip,voltage = <0x0>;
  1073. linux,phandle = <0x10b>;
  1074. phandle = <0x10b>;
  1075. };
  1076.  
  1077. lcdc-vcc-18 {
  1078. rockchip,pins = <0xfa00>;
  1079. rockchip,voltage = <0x1>;
  1080. linux,phandle = <0xf4>;
  1081. phandle = <0xf4>;
  1082. };
  1083.  
  1084. dvp-vcc-18 {
  1085. rockchip,pins = <0xfa10>;
  1086. rockchip,voltage = <0x1>;
  1087. linux,phandle = <0xf7>;
  1088. phandle = <0xf7>;
  1089. };
  1090.  
  1091. flash0-vcc-18 {
  1092. rockchip,pins = <0xfa20>;
  1093. rockchip,voltage = <0x1>;
  1094. linux,phandle = <0xfa>;
  1095. phandle = <0xfa>;
  1096. };
  1097.  
  1098. flash1-vcc-18 {
  1099. rockchip,pins = <0xfa30>;
  1100. rockchip,voltage = <0x1>;
  1101. linux,phandle = <0xfd>;
  1102. phandle = <0xfd>;
  1103. };
  1104.  
  1105. wifi-vcc-18 {
  1106. rockchip,pins = <0xfa40>;
  1107. rockchip,voltage = <0x1>;
  1108. linux,phandle = <0x100>;
  1109. phandle = <0x100>;
  1110. };
  1111.  
  1112. bb-vcc-18 {
  1113. rockchip,pins = <0xfa50>;
  1114. rockchip,voltage = <0x1>;
  1115. linux,phandle = <0x103>;
  1116. phandle = <0x103>;
  1117. };
  1118.  
  1119. audio-vcc-18 {
  1120. rockchip,pins = <0xfa60>;
  1121. rockchip,voltage = <0x1>;
  1122. linux,phandle = <0x106>;
  1123. phandle = <0x106>;
  1124. };
  1125.  
  1126. sdcard-vcc-18 {
  1127. rockchip,pins = <0xfa70>;
  1128. rockchip,voltage = <0x1>;
  1129. linux,phandle = <0x10f>;
  1130. phandle = <0x10f>;
  1131. };
  1132.  
  1133. gpio30-vcc-18 {
  1134. rockchip,pins = <0xfb00>;
  1135. rockchip,voltage = <0x1>;
  1136. linux,phandle = <0x109>;
  1137. phandle = <0x109>;
  1138. };
  1139.  
  1140. gpio1830-vcc-18 {
  1141. rockchip,pins = <0xfb10>;
  1142. rockchip,voltage = <0x1>;
  1143. linux,phandle = <0x10c>;
  1144. phandle = <0x10c>;
  1145. };
  1146.  
  1147. lcdc-vcc-33 {
  1148. rockchip,pins = <0xfa00>;
  1149. rockchip,voltage = <0x0>;
  1150. linux,phandle = <0xf5>;
  1151. phandle = <0xf5>;
  1152. };
  1153.  
  1154. dvp-vcc-33 {
  1155. rockchip,pins = <0xfa10>;
  1156. rockchip,voltage = <0x0>;
  1157. linux,phandle = <0xf8>;
  1158. phandle = <0xf8>;
  1159. };
  1160.  
  1161. flash0-vcc-33 {
  1162. rockchip,pins = <0xfa20>;
  1163. rockchip,voltage = <0x0>;
  1164. linux,phandle = <0xfb>;
  1165. phandle = <0xfb>;
  1166. };
  1167.  
  1168. flash1-vcc-33 {
  1169. rockchip,pins = <0xfa30>;
  1170. rockchip,voltage = <0x0>;
  1171. linux,phandle = <0xfe>;
  1172. phandle = <0xfe>;
  1173. };
  1174.  
  1175. wifi-vcc-33 {
  1176. rockchip,pins = <0xfa40>;
  1177. rockchip,voltage = <0x0>;
  1178. linux,phandle = <0x101>;
  1179. phandle = <0x101>;
  1180. };
  1181.  
  1182. bb-vcc-33 {
  1183. rockchip,pins = <0xfa50>;
  1184. rockchip,voltage = <0x0>;
  1185. linux,phandle = <0x104>;
  1186. phandle = <0x104>;
  1187. };
  1188.  
  1189. audio-vcc-33 {
  1190. rockchip,pins = <0xfa60>;
  1191. rockchip,voltage = <0x0>;
  1192. linux,phandle = <0x107>;
  1193. phandle = <0x107>;
  1194. };
  1195.  
  1196. sdcard-vcc-33 {
  1197. rockchip,pins = <0xfa70>;
  1198. rockchip,voltage = <0x0>;
  1199. linux,phandle = <0x110>;
  1200. phandle = <0x110>;
  1201. };
  1202.  
  1203. gpio30-vcc-33 {
  1204. rockchip,pins = <0xfb00>;
  1205. rockchip,voltage = <0x0>;
  1206. linux,phandle = <0x10a>;
  1207. phandle = <0x10a>;
  1208. };
  1209.  
  1210. gpio1830-vcc-33 {
  1211. rockchip,pins = <0xfb10>;
  1212. rockchip,voltage = <0x0>;
  1213. linux,phandle = <0x10d>;
  1214. phandle = <0x10d>;
  1215. };
  1216. };
  1217.  
  1218. isp_pin {
  1219.  
  1220. isp_mipi {
  1221. rockchip,pins = <0x2b31>;
  1222. rockchip,pull = <0x4>;
  1223. rockchip,drive = <0x0>;
  1224. linux,phandle = <0xec>;
  1225. phandle = <0xec>;
  1226. };
  1227.  
  1228. isp_dvp_d2d9 {
  1229. rockchip,pins = <0x2a01 0x2a11 0x2a21 0x2a31 0x2a41 0x2a51 0x2a61 0x2a71 0x2b01 0x2b11 0x2b21 0x2b31>;
  1230. rockchip,pull = <0x4>;
  1231. rockchip,drive = <0x0>;
  1232. linux,phandle = <0xed>;
  1233. phandle = <0xed>;
  1234. };
  1235.  
  1236. isp_d0d1 {
  1237. rockchip,pins = <0x2b41 0x2b51>;
  1238. rockchip,pull = <0x4>;
  1239. rockchip,drive = <0x0>;
  1240. linux,phandle = <0xee>;
  1241. phandle = <0xee>;
  1242. };
  1243.  
  1244. isp_d10d11 {
  1245. rockchip,pins = <0x2b61 0x2b71>;
  1246. rockchip,pull = <0x4>;
  1247. rockchip,drive = <0x0>;
  1248. linux,phandle = <0xef>;
  1249. phandle = <0xef>;
  1250. };
  1251.  
  1252. isp_d0d7 {
  1253. rockchip,pins = <0x2b41 0x2b51 0x2a01 0x2a11 0x2a21 0x2a31 0x2a41 0x2a51>;
  1254. rockchip,pull = <0x4>;
  1255. rockchip,drive = <0x0>;
  1256. linux,phandle = <0xf0>;
  1257. phandle = <0xf0>;
  1258. };
  1259.  
  1260. isp_shutter {
  1261. rockchip,pins = <0x7b41 0x7b71>;
  1262. rockchip,pull = <0x4>;
  1263. rockchip,drive = <0x0>;
  1264. };
  1265.  
  1266. isp_flash_trigger {
  1267. rockchip,pins = <0x7b51>;
  1268. rockchip,pull = <0x4>;
  1269. rockchip,drive = <0x0>;
  1270. linux,phandle = <0xf1>;
  1271. phandle = <0xf1>;
  1272. };
  1273.  
  1274. isp_prelight {
  1275. rockchip,pins = <0x7b61>;
  1276. rockchip,pull = <0x4>;
  1277. rockchip,drive = <0x0>;
  1278. linux,phandle = <0xf2>;
  1279. phandle = <0xf2>;
  1280. };
  1281.  
  1282. isp_hsadc {
  1283. rockchip,pins = <0x2a03 0x2a13 0x2a23 0x2a33 0x2a43 0x2a53 0x2a63 0x2a73 0x2b03 0x2b13 0x2b23 0x2b33>;
  1284. rockchip,pull = <0x1>;
  1285. rockchip,drive = <0x0>;
  1286. linux,phandle = <0x9c>;
  1287. phandle = <0x9c>;
  1288. };
  1289. };
  1290.  
  1291. gpio0_gpio {
  1292.  
  1293. gpio0-c2 {
  1294. rockchip,pins = <0xc20>;
  1295. rockchip,pull = <0x2>;
  1296. };
  1297. };
  1298.  
  1299. gpio7_gpio {
  1300.  
  1301. gpio7-b7 {
  1302. rockchip,pins = <0x7b70>;
  1303. rockchip,pull = <0x1>;
  1304. };
  1305. };
  1306. };
  1307.  
  1308. clocks {
  1309. compatible = "rockchip,rk-clocks";
  1310. #address-cells = <0x1>;
  1311. #size-cells = <0x1>;
  1312. ranges = <0x0 0xff760000 0x1b0>;
  1313.  
  1314. fixed_rate_cons {
  1315. compatible = "rockchip,rk-fixed-rate-cons";
  1316.  
  1317. xin24m {
  1318. compatible = "rockchip,rk-fixed-clock";
  1319. clock-output-names = "xin24m";
  1320. clock-frequency = <0x16e3600>;
  1321. #clock-cells = <0x0>;
  1322. linux,phandle = <0x8>;
  1323. phandle = <0x8>;
  1324. };
  1325.  
  1326. xin12m {
  1327. compatible = "rockchip,rk-fixed-clock";
  1328. clocks = <0x8>;
  1329. clock-output-names = "xin12m";
  1330. clock-frequency = <0xb71b00>;
  1331. #clock-cells = <0x0>;
  1332. linux,phandle = <0x1f>;
  1333. phandle = <0x1f>;
  1334. };
  1335.  
  1336. xin32k {
  1337. compatible = "rockchip,rk-fixed-clock";
  1338. clock-output-names = "xin32k";
  1339. clock-frequency = <0x7d00>;
  1340. #clock-cells = <0x0>;
  1341. linux,phandle = <0x17>;
  1342. phandle = <0x17>;
  1343. };
  1344.  
  1345. io_27m_in {
  1346. compatible = "rockchip,rk-fixed-clock";
  1347. clock-output-names = "io_27m_in";
  1348. clock-frequency = <0x19bfcc0>;
  1349. #clock-cells = <0x0>;
  1350. linux,phandle = <0x53>;
  1351. phandle = <0x53>;
  1352. };
  1353.  
  1354. dummy {
  1355. compatible = "rockchip,rk-fixed-clock";
  1356. clock-output-names = "dummy";
  1357. clock-frequency = <0x0>;
  1358. #clock-cells = <0x0>;
  1359. linux,phandle = <0x18>;
  1360. phandle = <0x18>;
  1361. };
  1362.  
  1363. dummy_cpll {
  1364. compatible = "rockchip,rk-fixed-clock";
  1365. clock-output-names = "dummy_cpll";
  1366. clock-frequency = <0x0>;
  1367. #clock-cells = <0x0>;
  1368. linux,phandle = <0x15>;
  1369. phandle = <0x15>;
  1370. };
  1371.  
  1372. i2s_clkin {
  1373. compatible = "rockchip,rk-fixed-clock";
  1374. clock-output-names = "i2s_clkin";
  1375. clock-frequency = <0x0>;
  1376. #clock-cells = <0x0>;
  1377. linux,phandle = <0x1e>;
  1378. phandle = <0x1e>;
  1379. };
  1380.  
  1381. edp_24m_clkin {
  1382. compatible = "rockchip,rk-fixed-clock";
  1383. #clock-cells = <0x0>;
  1384. clock-output-names = "edp_24m_clkin";
  1385. clock-frequency = <0x0>;
  1386. linux,phandle = <0x47>;
  1387. phandle = <0x47>;
  1388. };
  1389.  
  1390. gmac_clkin {
  1391. compatible = "rockchip,rk-fixed-clock";
  1392. #clock-cells = <0x0>;
  1393. clock-output-names = "gmac_clkin";
  1394. clock-frequency = <0x7735940>;
  1395. linux,phandle = <0x39>;
  1396. phandle = <0x39>;
  1397. };
  1398.  
  1399. clk_hsadc_ext {
  1400. compatible = "rockchip,rk-fixed-clock";
  1401. #clock-cells = <0x0>;
  1402. clock-output-names = "clk_hsadc_ext";
  1403. clock-frequency = <0x0>;
  1404. linux,phandle = <0x3b>;
  1405. phandle = <0x3b>;
  1406. };
  1407.  
  1408. jtag_clkin {
  1409. compatible = "rockchip,rk-fixed-clock";
  1410. #clock-cells = <0x0>;
  1411. clock-output-names = "jtag_clkin";
  1412. clock-frequency = <0x0>;
  1413. linux,phandle = <0x66>;
  1414. phandle = <0x66>;
  1415. };
  1416.  
  1417. pclkin_cif {
  1418. compatible = "rockchip,rk-fixed-clock";
  1419. #clock-cells = <0x0>;
  1420. clock-output-names = "pclkin_cif";
  1421. clock-frequency = <0x0>;
  1422. linux,phandle = <0x77>;
  1423. phandle = <0x77>;
  1424. };
  1425.  
  1426. pclkin_isp {
  1427. compatible = "rockchip,rk-fixed-clock";
  1428. #clock-cells = <0x0>;
  1429. clock-output-names = "pclkin_isp";
  1430. clock-frequency = <0x0>;
  1431. linux,phandle = <0x78>;
  1432. phandle = <0x78>;
  1433. };
  1434.  
  1435. hsadc_0_tsp {
  1436. compatible = "rockchip,rk-fixed-clock";
  1437. #clock-cells = <0x0>;
  1438. clock-output-names = "hsadc_0_tsp";
  1439. clock-frequency = <0x0>;
  1440. linux,phandle = <0x6a>;
  1441. phandle = <0x6a>;
  1442. };
  1443.  
  1444. hsadc_1_tsp {
  1445. compatible = "rockchip,rk-fixed-clock";
  1446. #clock-cells = <0x0>;
  1447. clock-output-names = "hsadc_1_tsp";
  1448. clock-frequency = <0x0>;
  1449. linux,phandle = <0x6b>;
  1450. phandle = <0x6b>;
  1451. };
  1452. };
  1453.  
  1454. fixed_factor_cons {
  1455. compatible = "rockchip,rk-fixed-factor-cons";
  1456.  
  1457. otgphy0_480m {
  1458. compatible = "rockchip,rk-fixed-factor-clock";
  1459. clocks = <0x9 0x4>;
  1460. clock-output-names = "otgphy0_480m";
  1461. clock-div = <0x1>;
  1462. clock-mult = <0x14>;
  1463. #clock-cells = <0x0>;
  1464. linux,phandle = <0x30>;
  1465. phandle = <0x30>;
  1466. };
  1467.  
  1468. otgphy1_480m {
  1469. compatible = "rockchip,rk-fixed-factor-clock";
  1470. clocks = <0x9 0x5>;
  1471. clock-output-names = "otgphy1_480m";
  1472. clock-div = <0x1>;
  1473. clock-mult = <0x14>;
  1474. #clock-cells = <0x0>;
  1475. linux,phandle = <0x2e>;
  1476. phandle = <0x2e>;
  1477. };
  1478.  
  1479. otgphy2_480m {
  1480. compatible = "rockchip,rk-fixed-factor-clock";
  1481. clocks = <0x9 0x6>;
  1482. clock-output-names = "otgphy2_480m";
  1483. clock-div = <0x1>;
  1484. clock-mult = <0x14>;
  1485. #clock-cells = <0x0>;
  1486. linux,phandle = <0x2f>;
  1487. phandle = <0x2f>;
  1488. };
  1489.  
  1490. clk_hsadc_inv {
  1491. compatible = "rockchip,rk-fixed-factor-clock";
  1492. clocks = <0xa>;
  1493. clock-output-names = "clk_hsadc_inv";
  1494. clock-div = <0x1>;
  1495. clock-mult = <0x1>;
  1496. #clock-cells = <0x0>;
  1497. linux,phandle = <0x3c>;
  1498. phandle = <0x3c>;
  1499. };
  1500.  
  1501. pclkin_cif_inv {
  1502. compatible = "rockchip,rk-fixed-factor-clock";
  1503. clocks = <0xb 0x0>;
  1504. clock-output-names = "pclkin_cif_inv";
  1505. clock-div = <0x1>;
  1506. clock-mult = <0x1>;
  1507. #clock-cells = <0x0>;
  1508. linux,phandle = <0x4a>;
  1509. phandle = <0x4a>;
  1510. };
  1511.  
  1512. pclkin_isp_inv {
  1513. compatible = "rockchip,rk-fixed-factor-clock";
  1514. clocks = <0xb 0x3>;
  1515. clock-output-names = "pclkin_isp_inv";
  1516. clock-div = <0x1>;
  1517. clock-mult = <0x1>;
  1518. #clock-cells = <0x0>;
  1519. linux,phandle = <0x49>;
  1520. phandle = <0x49>;
  1521. };
  1522.  
  1523. hclk_vepu {
  1524. compatible = "rockchip,rk-fixed-factor-clock";
  1525. clocks = <0xc>;
  1526. clock-output-names = "hclk_vepu";
  1527. clock-div = <0x4>;
  1528. clock-mult = <0x1>;
  1529. #clock-cells = <0x0>;
  1530. };
  1531.  
  1532. hclk_vdpu {
  1533. compatible = "rockchip,rk-fixed-factor-clock";
  1534. clocks = <0xd>;
  1535. clock-output-names = "hclk_vdpu";
  1536. clock-div = <0x4>;
  1537. clock-mult = <0x1>;
  1538. #clock-cells = <0x0>;
  1539. linux,phandle = <0xe3>;
  1540. phandle = <0xe3>;
  1541. };
  1542. };
  1543.  
  1544. pd_cons {
  1545. compatible = "rockchip,rk-pd-cons";
  1546.  
  1547. pd_gpu {
  1548. compatible = "rockchip,rk-pd-clock";
  1549. clock-output-names = "pd_gpu";
  1550. rockchip,pd-id = <0x8>;
  1551. #clock-cells = <0x0>;
  1552. };
  1553.  
  1554. pd_video {
  1555. compatible = "rockchip,rk-pd-clock";
  1556. clock-output-names = "pd_video";
  1557. rockchip,pd-id = <0xc>;
  1558. #clock-cells = <0x0>;
  1559. };
  1560.  
  1561. pd_vio {
  1562. compatible = "rockchip,rk-pd-clock";
  1563. clock-output-names = "pd_vio";
  1564. rockchip,pd-id = <0xd>;
  1565. #clock-cells = <0x0>;
  1566. linux,phandle = <0xe>;
  1567. phandle = <0xe>;
  1568. };
  1569.  
  1570. pd_hevc {
  1571. compatible = "rockchip,rk-pd-clock";
  1572. clock-output-names = "pd_hevc";
  1573. rockchip,pd-id = <0x9>;
  1574. #clock-cells = <0x0>;
  1575. };
  1576.  
  1577. pd_edp {
  1578. compatible = "rockchip,rk-pd-clock";
  1579. clocks = <0xe>;
  1580. clock-output-names = "pd_edp";
  1581. rockchip,pd-id = <0xff>;
  1582. #clock-cells = <0x0>;
  1583. };
  1584.  
  1585. pd_vop0 {
  1586. compatible = "rockchip,rk-pd-clock";
  1587. clocks = <0xe>;
  1588. clock-output-names = "pd_vop0";
  1589. rockchip,pd-id = <0xff>;
  1590. #clock-cells = <0x0>;
  1591. linux,phandle = <0xcc>;
  1592. phandle = <0xcc>;
  1593. };
  1594.  
  1595. pd_vop1 {
  1596. compatible = "rockchip,rk-pd-clock";
  1597. clocks = <0xe>;
  1598. clock-output-names = "pd_vop1";
  1599. rockchip,pd-id = <0xff>;
  1600. #clock-cells = <0x0>;
  1601. linux,phandle = <0xcf>;
  1602. phandle = <0xcf>;
  1603. };
  1604.  
  1605. pd_isp {
  1606. compatible = "rockchip,rk-pd-clock";
  1607. clocks = <0xe>;
  1608. clock-output-names = "pd_isp";
  1609. rockchip,pd-id = <0xff>;
  1610. #clock-cells = <0x0>;
  1611. linux,phandle = <0xeb>;
  1612. phandle = <0xeb>;
  1613. };
  1614.  
  1615. pd_iep {
  1616. compatible = "rockchip,rk-pd-clock";
  1617. clocks = <0xe>;
  1618. clock-output-names = "pd_iep";
  1619. rockchip,pd-id = <0xff>;
  1620. #clock-cells = <0x0>;
  1621. };
  1622.  
  1623. pd_rga {
  1624. compatible = "rockchip,rk-pd-clock";
  1625. clocks = <0xe>;
  1626. clock-output-names = "pd_rga";
  1627. rockchip,pd-id = <0xff>;
  1628. #clock-cells = <0x0>;
  1629. };
  1630.  
  1631. pd_mipicsi {
  1632. compatible = "rockchip,rk-pd-clock";
  1633. clocks = <0xe>;
  1634. clock-output-names = "pd_mipicsi";
  1635. rockchip,pd-id = <0xff>;
  1636. #clock-cells = <0x0>;
  1637. };
  1638.  
  1639. pd_mipidsi {
  1640. compatible = "rockchip,rk-pd-clock";
  1641. clocks = <0xe>;
  1642. clock-output-names = "pd_mipidsi";
  1643. rockchip,pd-id = <0xff>;
  1644. #clock-cells = <0x0>;
  1645. linux,phandle = <0xca>;
  1646. phandle = <0xca>;
  1647. };
  1648.  
  1649. pd_lvds {
  1650. compatible = "rockchip,rk-pd-clock";
  1651. clocks = <0xe>;
  1652. clock-output-names = "pd_lvds";
  1653. rockchip,pd-id = <0xff>;
  1654. #clock-cells = <0x0>;
  1655. };
  1656.  
  1657. pd_hdmi {
  1658. compatible = "rockchip,rk-pd-clock";
  1659. clocks = <0xe>;
  1660. clock-output-names = "pd_hdmi";
  1661. rockchip,pd-id = <0xff>;
  1662. #clock-cells = <0x0>;
  1663. };
  1664. };
  1665.  
  1666. clock_regs {
  1667. compatible = "rockchip,rk-clock-regs";
  1668. #address-cells = <0x1>;
  1669. #size-cells = <0x1>;
  1670. reg = <0x0 0x3ff>;
  1671. ranges;
  1672.  
  1673. pll_cons {
  1674. compatible = "rockchip,rk-pll-cons";
  1675. #address-cells = <0x1>;
  1676. #size-cells = <0x1>;
  1677. ranges;
  1678.  
  1679. pll-clk@0000 {
  1680. compatible = "rockchip,rk3188-pll-clk";
  1681. reg = <0x0 0x10>;
  1682. mode-reg = <0x50 0x0>;
  1683. status-reg = <0x284 0x6>;
  1684. clocks = <0x8>;
  1685. clock-output-names = "clk_apll";
  1686. rockchip,pll-type = <0x10>;
  1687. #clock-cells = <0x0>;
  1688. linux,phandle = <0x10>;
  1689. phandle = <0x10>;
  1690. };
  1691.  
  1692. pll-clk@0010 {
  1693. compatible = "rockchip,rk3188-pll-clk";
  1694. reg = <0x10 0x10>;
  1695. mode-reg = <0x50 0x4>;
  1696. status-reg = <0x284 0x5>;
  1697. clocks = <0x8>;
  1698. clock-output-names = "clk_dpll";
  1699. rockchip,pll-type = <0x4>;
  1700. #clock-cells = <0x0>;
  1701. linux,phandle = <0x40>;
  1702. phandle = <0x40>;
  1703. };
  1704.  
  1705. pll-clk@0020 {
  1706. compatible = "rockchip,rk3188-pll-clk";
  1707. reg = <0x20 0x10>;
  1708. mode-reg = <0x50 0x8>;
  1709. status-reg = <0x284 0x7>;
  1710. clocks = <0x8>;
  1711. clock-output-names = "clk_cpll";
  1712. rockchip,pll-type = <0x20>;
  1713. #clock-cells = <0x0>;
  1714. #clock-init-cells = <0x1>;
  1715. linux,phandle = <0x43>;
  1716. phandle = <0x43>;
  1717. };
  1718.  
  1719. pll-clk@0030 {
  1720. compatible = "rockchip,rk3188-pll-clk";
  1721. reg = <0x30 0x10>;
  1722. mode-reg = <0x50 0xc>;
  1723. status-reg = <0x284 0x8>;
  1724. clocks = <0x8>;
  1725. clock-output-names = "clk_gpll";
  1726. rockchip,pll-type = <0x4>;
  1727. #clock-cells = <0x0>;
  1728. #clock-init-cells = <0x1>;
  1729. linux,phandle = <0x16>;
  1730. phandle = <0x16>;
  1731. };
  1732.  
  1733. pll-clk@0040 {
  1734. compatible = "rockchip,rk3188-pll-clk";
  1735. reg = <0x40 0x10>;
  1736. mode-reg = <0x50 0xe>;
  1737. status-reg = <0x284 0x9>;
  1738. clocks = <0x8>;
  1739. clock-output-names = "clk_npll";
  1740. rockchip,pll-type = <0x4>;
  1741. #clock-cells = <0x0>;
  1742. #clock-init-cells = <0x1>;
  1743. linux,phandle = <0x25>;
  1744. phandle = <0x25>;
  1745. };
  1746. };
  1747.  
  1748. clk_sel_cons {
  1749. compatible = "rockchip,rk-sel-cons";
  1750. #address-cells = <0x1>;
  1751. #size-cells = <0x1>;
  1752. ranges;
  1753.  
  1754. sel-con@0060 {
  1755. compatible = "rockchip,rk3188-selcon";
  1756. reg = <0x60 0x4>;
  1757. #address-cells = <0x1>;
  1758. #size-cells = <0x1>;
  1759.  
  1760. aclk_core_m0_div {
  1761. compatible = "rockchip,rk3188-div-con";
  1762. rockchip,bits = <0x0 0x4>;
  1763. clocks = <0xf>;
  1764. clock-output-names = "aclk_core_m0";
  1765. rockchip,div-type = <0x0>;
  1766. #clock-cells = <0x0>;
  1767. rockchip,clkops-idx = <0xc>;
  1768. linux,phandle = <0x71>;
  1769. phandle = <0x71>;
  1770. };
  1771.  
  1772. aclk_core_mp_div {
  1773. compatible = "rockchip,rk3188-div-con";
  1774. rockchip,bits = <0x4 0x4>;
  1775. clocks = <0xf>;
  1776. clock-output-names = "aclk_core_mp";
  1777. rockchip,div-type = <0x0>;
  1778. #clock-cells = <0x0>;
  1779. rockchip,clkops-idx = <0xc>;
  1780. linux,phandle = <0x72>;
  1781. phandle = <0x72>;
  1782. };
  1783.  
  1784. clk_core_div {
  1785. compatible = "rockchip,rk3188-div-con";
  1786. rockchip,bits = <0x8 0x5>;
  1787. clocks = <0xf>;
  1788. clock-output-names = "clk_core";
  1789. rockchip,div-type = <0x0>;
  1790. #clock-cells = <0x0>;
  1791. rockchip,clkops-idx = <0xb>;
  1792. rockchip,flags = <0xc0>;
  1793. };
  1794.  
  1795. clk_core_mux {
  1796. compatible = "rockchip,rk3188-mux-con";
  1797. rockchip,bits = <0xf 0x1>;
  1798. clocks = <0x10 0x11 0x2>;
  1799. clock-output-names = "clk_core";
  1800. #clock-cells = <0x0>;
  1801. #clock-init-cells = <0x1>;
  1802. linux,phandle = <0xf>;
  1803. phandle = <0xf>;
  1804. };
  1805. };
  1806.  
  1807. sel-con@0064 {
  1808. compatible = "rockchip,rk3188-selcon";
  1809. reg = <0x64 0x4>;
  1810. #address-cells = <0x1>;
  1811. #size-cells = <0x1>;
  1812.  
  1813. aclk_bus_div {
  1814. compatible = "rockchip,rk3188-div-con";
  1815. rockchip,bits = <0x0 0x3>;
  1816. clocks = <0x12>;
  1817. clock-output-names = "aclk_bus";
  1818. rockchip,div-type = <0x0>;
  1819. #clock-cells = <0x0>;
  1820. #clock-init-cells = <0x1>;
  1821. linux,phandle = <0x14>;
  1822. phandle = <0x14>;
  1823. };
  1824.  
  1825. aclk_bus_src_div {
  1826. compatible = "rockchip,rk3188-div-con";
  1827. rockchip,bits = <0x3 0x5>;
  1828. clocks = <0x13>;
  1829. clock-output-names = "aclk_bus_src";
  1830. rockchip,div-type = <0x0>;
  1831. #clock-cells = <0x0>;
  1832. rockchip,clkops-idx = <0x1>;
  1833. rockchip,flags = <0x80>;
  1834. linux,phandle = <0x12>;
  1835. phandle = <0x12>;
  1836. };
  1837.  
  1838. hclk_bus_div {
  1839. compatible = "rockchip,rk3188-div-con";
  1840. rockchip,bits = <0x8 0x2>;
  1841. clocks = <0x14>;
  1842. clock-output-names = "hclk_bus";
  1843. rockchip,div-type = <0x80>;
  1844. rockchip,div-relations = <0x0 0x1 0x1 0x2 0x3 0x4>;
  1845. #clock-cells = <0x0>;
  1846. #clock-init-cells = <0x1>;
  1847. linux,phandle = <0x5c>;
  1848. phandle = <0x5c>;
  1849. };
  1850.  
  1851. pclk_bus_div {
  1852. compatible = "rockchip,rk3188-div-con";
  1853. rockchip,bits = <0xc 0x3>;
  1854. clocks = <0x14>;
  1855. clock-output-names = "pclk_bus";
  1856. rockchip,div-type = <0x0>;
  1857. #clock-cells = <0x0>;
  1858. #clock-init-cells = <0x1>;
  1859. linux,phandle = <0x5d>;
  1860. phandle = <0x5d>;
  1861. };
  1862.  
  1863. aclk_bus_src_mux {
  1864. compatible = "rockchip,rk3188-mux-con";
  1865. rockchip,bits = <0xf 0x1>;
  1866. clocks = <0x15 0x16>;
  1867. clock-output-names = "aclk_bus_src";
  1868. #clock-cells = <0x0>;
  1869. #clock-init-cells = <0x1>;
  1870. linux,phandle = <0x13>;
  1871. phandle = <0x13>;
  1872. };
  1873. };
  1874.  
  1875. sel-con@0068 {
  1876. compatible = "rockchip,rk3188-selcon";
  1877. reg = <0x68 0x4>;
  1878. #address-cells = <0x1>;
  1879. #size-cells = <0x1>;
  1880.  
  1881. clk_tsadc_div {
  1882. compatible = "rockchip,rk3188-div-con";
  1883. rockchip,bits = <0x0 0x6>;
  1884. clocks = <0x17>;
  1885. clock-output-names = "clk_tsadc";
  1886. rockchip,div-type = <0x0>;
  1887. #clock-cells = <0x0>;
  1888. linux,phandle = <0x60>;
  1889. phandle = <0x60>;
  1890. };
  1891.  
  1892. testout_div {
  1893. compatible = "rockchip,rk3188-div-con";
  1894. rockchip,bits = <0x8 0x5>;
  1895. clocks = <0x18>;
  1896. clock-output-names = "testout_div";
  1897. rockchip,div-type = <0x0>;
  1898. #clock-cells = <0x0>;
  1899. };
  1900. };
  1901.  
  1902. sel-con@006c {
  1903. compatible = "rockchip,rk3188-selcon";
  1904. reg = <0x6c 0x4>;
  1905. #address-cells = <0x1>;
  1906. #size-cells = <0x1>;
  1907.  
  1908. clk_uart4_div {
  1909. compatible = "rockchip,rk3188-div-con";
  1910. rockchip,bits = <0x0 0x7>;
  1911. clocks = <0x19>;
  1912. clock-output-names = "clk_uart4_div";
  1913. rockchip,div-type = <0x0>;
  1914. #clock-cells = <0x0>;
  1915. linux,phandle = <0x1a>;
  1916. phandle = <0x1a>;
  1917. };
  1918.  
  1919. uart4_mux {
  1920. compatible = "rockchip,rk3188-mux-con";
  1921. rockchip,bits = <0x8 0x2>;
  1922. clocks = <0x1a 0x1b 0x8 0x18>;
  1923. clock-output-names = "clk_uart4";
  1924. #clock-cells = <0x0>;
  1925. rockchip,clkops-idx = <0xe>;
  1926. rockchip,flags = <0x4>;
  1927. linux,phandle = <0xad>;
  1928. phandle = <0xad>;
  1929. };
  1930. };
  1931.  
  1932. sel-con@0070 {
  1933. compatible = "rockchip,rk3188-selcon";
  1934. reg = <0x70 0x4>;
  1935. #address-cells = <0x1>;
  1936. #size-cells = <0x1>;
  1937.  
  1938. i2s_pll_div {
  1939. compatible = "rockchip,rk3188-div-con";
  1940. rockchip,bits = <0x0 0x7>;
  1941. clocks = <0x1c>;
  1942. clock-output-names = "clk_i2s_pll";
  1943. rockchip,div-type = <0x0>;
  1944. #clock-cells = <0x0>;
  1945. rockchip,clkops-idx = <0x1>;
  1946. rockchip,flags = <0x80>;
  1947. };
  1948.  
  1949. i2s_mux {
  1950. compatible = "rockchip,rk3188-mux-con";
  1951. rockchip,bits = <0x8 0x2>;
  1952. clocks = <0x1c 0x1d 0x1e 0x1f>;
  1953. clock-output-names = "clk_i2s";
  1954. #clock-cells = <0x0>;
  1955. rockchip,clkops-idx = <0xe>;
  1956. rockchip,flags = <0x4>;
  1957. linux,phandle = <0x20>;
  1958. phandle = <0x20>;
  1959. };
  1960.  
  1961. i2s_outclk_mux {
  1962. compatible = "rockchip,rk3188-mux-con";
  1963. rockchip,bits = <0xc 0x1>;
  1964. clocks = <0x20 0x1f>;
  1965. clock-output-names = "clk_i2s_out";
  1966. #clock-cells = <0x0>;
  1967. linux,phandle = <0x63>;
  1968. phandle = <0x63>;
  1969. };
  1970.  
  1971. i2s_pll_mux {
  1972. compatible = "rockchip,rk3188-mux-con";
  1973. rockchip,bits = <0xf 0x1>;
  1974. clocks = <0x15 0x16>;
  1975. clock-output-names = "clk_i2s_pll";
  1976. #clock-cells = <0x0>;
  1977. #clock-init-cells = <0x1>;
  1978. linux,phandle = <0x1c>;
  1979. phandle = <0x1c>;
  1980. };
  1981. };
  1982.  
  1983. sel-con@0074 {
  1984. compatible = "rockchip,rk3188-selcon";
  1985. reg = <0x74 0x4>;
  1986. #address-cells = <0x1>;
  1987. #size-cells = <0x1>;
  1988.  
  1989. spdif_div {
  1990. compatible = "rockchip,rk3188-div-con";
  1991. rockchip,bits = <0x0 0x7>;
  1992. clocks = <0x21>;
  1993. clock-output-names = "spdif_div";
  1994. rockchip,div-type = <0x0>;
  1995. #clock-cells = <0x0>;
  1996. linux,phandle = <0x22>;
  1997. phandle = <0x22>;
  1998. };
  1999.  
  2000. spdif_mux {
  2001. compatible = "rockchip,rk3188-mux-con";
  2002. rockchip,bits = <0x8 0x2>;
  2003. clocks = <0x22 0x23 0x1f 0x18>;
  2004. clock-output-names = "clk_spdif";
  2005. #clock-cells = <0x0>;
  2006. rockchip,clkops-idx = <0xe>;
  2007. rockchip,flags = <0x4>;
  2008. linux,phandle = <0x64>;
  2009. phandle = <0x64>;
  2010. };
  2011.  
  2012. spdif_pll_mux {
  2013. compatible = "rockchip,rk3188-mux-con";
  2014. rockchip,bits = <0xf 0x1>;
  2015. clocks = <0x15 0x16>;
  2016. clock-output-names = "clk_spdif_pll";
  2017. #clock-cells = <0x0>;
  2018. #clock-init-cells = <0x1>;
  2019. linux,phandle = <0x21>;
  2020. phandle = <0x21>;
  2021. };
  2022. };
  2023.  
  2024. sel-con@0078 {
  2025. compatible = "rockchip,rk3188-selcon";
  2026. reg = <0x78 0x4>;
  2027. #address-cells = <0x1>;
  2028. #size-cells = <0x1>;
  2029.  
  2030. clk_isp_div {
  2031. compatible = "rockchip,rk3188-div-con";
  2032. rockchip,bits = <0x0 0x6>;
  2033. clocks = <0x24>;
  2034. clock-output-names = "clk_isp";
  2035. rockchip,div-type = <0x0>;
  2036. #clock-cells = <0x0>;
  2037. rockchip,clkops-idx = <0x1>;
  2038. };
  2039.  
  2040. clk_isp_mux {
  2041. compatible = "rockchip,rk3188-mux-con";
  2042. rockchip,bits = <0x6 0x2>;
  2043. clocks = <0x15 0x16 0x25>;
  2044. clock-output-names = "clk_isp";
  2045. #clock-cells = <0x0>;
  2046. #clock-init-cells = <0x1>;
  2047. linux,phandle = <0x24>;
  2048. phandle = <0x24>;
  2049. };
  2050.  
  2051. clk_isp_jpe_div {
  2052. compatible = "rockchip,rk3188-div-con";
  2053. rockchip,bits = <0x8 0x6>;
  2054. clocks = <0x26>;
  2055. clock-output-names = "clk_isp_jpe";
  2056. rockchip,div-type = <0x0>;
  2057. #clock-cells = <0x0>;
  2058. rockchip,clkops-idx = <0x1>;
  2059. };
  2060.  
  2061. clk_isp_jpe_mux {
  2062. compatible = "rockchip,rk3188-mux-con";
  2063. rockchip,bits = <0xe 0x2>;
  2064. clocks = <0x15 0x16 0x25>;
  2065. clock-output-names = "clk_isp_jpe";
  2066. #clock-cells = <0x0>;
  2067. #clock-init-cells = <0x1>;
  2068. linux,phandle = <0x26>;
  2069. phandle = <0x26>;
  2070. };
  2071. };
  2072.  
  2073. sel-con@007c {
  2074. compatible = "rockchip,rk3188-selcon";
  2075. reg = <0x7c 0x4>;
  2076. #address-cells = <0x1>;
  2077. #size-cells = <0x1>;
  2078.  
  2079. uart4_frac {
  2080. compatible = "rockchip,rk3188-frac-con";
  2081. clocks = <0x1a>;
  2082. clock-output-names = "uart4_frac";
  2083. rockchip,bits = <0x0 0x20>;
  2084. rockchip,clkops-idx = <0x5>;
  2085. #clock-cells = <0x0>;
  2086. linux,phandle = <0x1b>;
  2087. phandle = <0x1b>;
  2088. };
  2089. };
  2090.  
  2091. sel-con@0080 {
  2092. compatible = "rockchip,rk3188-selcon";
  2093. reg = <0x80 0x4>;
  2094. #address-cells = <0x1>;
  2095. #size-cells = <0x1>;
  2096.  
  2097. i2s_frac {
  2098. compatible = "rockchip,rk3188-frac-con";
  2099. clocks = <0x1c>;
  2100. clock-output-names = "i2s_frac";
  2101. rockchip,bits = <0x0 0x20>;
  2102. rockchip,clkops-idx = <0x5>;
  2103. #clock-cells = <0x0>;
  2104. linux,phandle = <0x1d>;
  2105. phandle = <0x1d>;
  2106. };
  2107. };
  2108.  
  2109. sel-con@0084 {
  2110. compatible = "rockchip,rk3188-selcon";
  2111. reg = <0x84 0x4>;
  2112. #address-cells = <0x1>;
  2113. #size-cells = <0x1>;
  2114.  
  2115. spdif_frac {
  2116. compatible = "rockchip,rk3188-frac-con";
  2117. clocks = <0x22>;
  2118. clock-output-names = "spdif_frac";
  2119. rockchip,bits = <0x0 0x20>;
  2120. rockchip,clkops-idx = <0x5>;
  2121. #clock-cells = <0x0>;
  2122. linux,phandle = <0x23>;
  2123. phandle = <0x23>;
  2124. };
  2125. };
  2126.  
  2127. sel-con@0088 {
  2128. compatible = "rockchip,rk3188-selcon";
  2129. reg = <0x88 0x4>;
  2130. #address-cells = <0x1>;
  2131. #size-cells = <0x1>;
  2132.  
  2133. aclk_peri_div {
  2134. compatible = "rockchip,rk3188-div-con";
  2135. rockchip,bits = <0x0 0x5>;
  2136. clocks = <0x27>;
  2137. clock-output-names = "aclk_peri";
  2138. rockchip,div-type = <0x0>;
  2139. #clock-cells = <0x0>;
  2140. rockchip,clkops-idx = <0x1>;
  2141. rockchip,flags = <0x80>;
  2142. };
  2143.  
  2144. hclk_peri_div {
  2145. compatible = "rockchip,rk3188-div-con";
  2146. rockchip,bits = <0x8 0x2>;
  2147. clocks = <0x27>;
  2148. clock-output-names = "hclk_peri";
  2149. rockchip,div-type = <0x80>;
  2150. rockchip,div-relations = <0x0 0x1 0x1 0x2 0x2 0x4>;
  2151. #clock-cells = <0x0>;
  2152. #clock-init-cells = <0x1>;
  2153. linux,phandle = <0x5e>;
  2154. phandle = <0x5e>;
  2155. };
  2156.  
  2157. pclk_peri_div {
  2158. compatible = "rockchip,rk3188-div-con";
  2159. rockchip,bits = <0xc 0x2>;
  2160. clocks = <0x27>;
  2161. clock-output-names = "pclk_peri";
  2162. rockchip,div-type = <0x80>;
  2163. rockchip,div-relations = <0x0 0x1 0x1 0x2 0x2 0x4 0x3 0x8>;
  2164. #clock-cells = <0x0>;
  2165. #clock-init-cells = <0x1>;
  2166. linux,phandle = <0x5f>;
  2167. phandle = <0x5f>;
  2168. };
  2169.  
  2170. aclk_peri_mux {
  2171. compatible = "rockchip,rk3188-mux-con";
  2172. rockchip,bits = <0xf 0x1>;
  2173. clocks = <0x15 0x16>;
  2174. clock-output-names = "aclk_peri";
  2175. #clock-cells = <0x0>;
  2176. #clock-init-cells = <0x1>;
  2177. linux,phandle = <0x27>;
  2178. phandle = <0x27>;
  2179. };
  2180. };
  2181.  
  2182. sel-con@008c {
  2183. compatible = "rockchip,rk3188-selcon";
  2184. reg = <0x8c 0x4>;
  2185. #address-cells = <0x1>;
  2186. #size-cells = <0x1>;
  2187.  
  2188. clk_sdmmc_div {
  2189. compatible = "rockchip,rk3188-div-con";
  2190. rockchip,bits = <0x0 0x6>;
  2191. clocks = <0x28>;
  2192. clock-output-names = "clk_sdmmc";
  2193. rockchip,div-type = <0x0>;
  2194. #clock-cells = <0x0>;
  2195. rockchip,clkops-idx = <0x3>;
  2196. };
  2197.  
  2198. clk_sdmmc_mux {
  2199. compatible = "rockchip,rk3188-mux-con";
  2200. rockchip,bits = <0x6 0x2>;
  2201. clocks = <0x15 0x16 0x8>;
  2202. clock-output-names = "clk_sdmmc";
  2203. #clock-cells = <0x0>;
  2204. linux,phandle = <0x28>;
  2205. phandle = <0x28>;
  2206. };
  2207.  
  2208. hsicphy_12m_div {
  2209. compatible = "rockchip,rk3188-div-con";
  2210. rockchip,bits = <0x8 0x6>;
  2211. clocks = <0x29>;
  2212. clock-output-names = "hsicphy_12m_div";
  2213. rockchip,div-type = <0x0>;
  2214. #clock-cells = <0x0>;
  2215. linux,phandle = <0x48>;
  2216. phandle = <0x48>;
  2217. };
  2218. };
  2219.  
  2220. sel-con@0090 {
  2221. compatible = "rockchip,rk3188-selcon";
  2222. reg = <0x90 0x4>;
  2223. #address-cells = <0x1>;
  2224. #size-cells = <0x1>;
  2225.  
  2226. clk_sdio0_div {
  2227. compatible = "rockchip,rk3188-div-con";
  2228. rockchip,bits = <0x0 0x6>;
  2229. clocks = <0x2a>;
  2230. clock-output-names = "clk_sdio0";
  2231. rockchip,div-type = <0x0>;
  2232. #clock-cells = <0x0>;
  2233. rockchip,clkops-idx = <0x3>;
  2234. };
  2235.  
  2236. clk_sdio0_mux {
  2237. compatible = "rockchip,rk3188-mux-con";
  2238. rockchip,bits = <0x6 0x2>;
  2239. clocks = <0x15 0x16 0x8>;
  2240. clock-output-names = "clk_sdio0";
  2241. #clock-cells = <0x0>;
  2242. linux,phandle = <0x2a>;
  2243. phandle = <0x2a>;
  2244. };
  2245.  
  2246. clk_emmc_div {
  2247. compatible = "rockchip,rk3188-div-con";
  2248. rockchip,bits = <0x8 0x6>;
  2249. clocks = <0x2b>;
  2250. clock-output-names = "clk_emmc";
  2251. rockchip,div-type = <0x0>;
  2252. #clock-cells = <0x0>;
  2253. rockchip,clkops-idx = <0x3>;
  2254. };
  2255.  
  2256. clk_emmc_mux {
  2257. compatible = "rockchip,rk3188-mux-con";
  2258. rockchip,bits = <0xe 0x2>;
  2259. clocks = <0x15 0x16 0x8>;
  2260. clock-output-names = "clk_emmc";
  2261. #clock-cells = <0x0>;
  2262. linux,phandle = <0x2b>;
  2263. phandle = <0x2b>;
  2264. };
  2265. };
  2266.  
  2267. sel-con@0094 {
  2268. compatible = "rockchip,rk3188-selcon";
  2269. reg = <0x94 0x4>;
  2270. #address-cells = <0x1>;
  2271. #size-cells = <0x1>;
  2272.  
  2273. clk_uart0_pll_div {
  2274. compatible = "rockchip,rk3188-div-con";
  2275. rockchip,bits = <0x0 0x7>;
  2276. clocks = <0x2c>;
  2277. clock-output-names = "clk_uart0_pll";
  2278. rockchip,div-type = <0x0>;
  2279. #clock-cells = <0x0>;
  2280. rockchip,clkops-idx = <0x1>;
  2281. };
  2282.  
  2283. uart0_mux {
  2284. compatible = "rockchip,rk3188-mux-con";
  2285. rockchip,bits = <0x8 0x2>;
  2286. clocks = <0x2c 0x2d 0x8 0x18>;
  2287. clock-output-names = "clk_uart0";
  2288. #clock-cells = <0x0>;
  2289. rockchip,clkops-idx = <0xe>;
  2290. rockchip,flags = <0x4>;
  2291. linux,phandle = <0x9e>;
  2292. phandle = <0x9e>;
  2293. };
  2294.  
  2295. usbphy_480m_mux {
  2296. compatible = "rockchip,rk3188-mux-con";
  2297. rockchip,bits = <0xb 0x2>;
  2298. clocks = <0x2e 0x2f 0x30>;
  2299. clock-output-names = "usbphy_480m";
  2300. #clock-cells = <0x0>;
  2301. rockchip,clkops-idx = <0xf>;
  2302. #clock-init-cells = <0x1>;
  2303. linux,phandle = <0x31>;
  2304. phandle = <0x31>;
  2305. };
  2306.  
  2307. clk_uart0_pll_mux {
  2308. compatible = "rockchip,rk3188-mux-con";
  2309. rockchip,bits = <0xd 0x2>;
  2310. clocks = <0x15 0x16 0x31 0x25>;
  2311. clock-output-names = "clk_uart0_pll";
  2312. #clock-cells = <0x0>;
  2313. linux,phandle = <0x2c>;
  2314. phandle = <0x2c>;
  2315. };
  2316.  
  2317. uart_pll_mux {
  2318. compatible = "rockchip,rk3188-mux-con";
  2319. rockchip,bits = <0xf 0x1>;
  2320. clocks = <0x15 0x16>;
  2321. clock-output-names = "uart_pll_mux";
  2322. #clock-cells = <0x0>;
  2323. #clock-init-cells = <0x1>;
  2324. linux,phandle = <0x19>;
  2325. phandle = <0x19>;
  2326. };
  2327. };
  2328.  
  2329. sel-con@0098 {
  2330. compatible = "rockchip,rk3188-selcon";
  2331. reg = <0x98 0x4>;
  2332. #address-cells = <0x1>;
  2333. #size-cells = <0x1>;
  2334.  
  2335. clk_uart1_div {
  2336. compatible = "rockchip,rk3188-div-con";
  2337. rockchip,bits = <0x0 0x7>;
  2338. clocks = <0x19>;
  2339. clock-output-names = "clk_uart1_div";
  2340. rockchip,div-type = <0x0>;
  2341. #clock-cells = <0x0>;
  2342. linux,phandle = <0x32>;
  2343. phandle = <0x32>;
  2344. };
  2345.  
  2346. uart1_mux {
  2347. compatible = "rockchip,rk3188-mux-con";
  2348. rockchip,bits = <0x8 0x2>;
  2349. clocks = <0x32 0x33 0x8 0x18>;
  2350. clock-output-names = "clk_uart1";
  2351. #clock-cells = <0x0>;
  2352. rockchip,clkops-idx = <0xe>;
  2353. rockchip,flags = <0x4>;
  2354. linux,phandle = <0xa1>;
  2355. phandle = <0xa1>;
  2356. };
  2357. };
  2358.  
  2359. sel-con@009c {
  2360. compatible = "rockchip,rk3188-selcon";
  2361. reg = <0x9c 0x4>;
  2362. #address-cells = <0x1>;
  2363. #size-cells = <0x1>;
  2364.  
  2365. clk_uart2_div {
  2366. compatible = "rockchip,rk3188-div-con";
  2367. rockchip,bits = <0x0 0x7>;
  2368. clocks = <0x19>;
  2369. clock-output-names = "clk_uart2_div";
  2370. rockchip,div-type = <0x0>;
  2371. #clock-cells = <0x0>;
  2372. linux,phandle = <0x34>;
  2373. phandle = <0x34>;
  2374. };
  2375.  
  2376. uart2_mux {
  2377. compatible = "rockchip,rk3188-mux-con";
  2378. rockchip,bits = <0x8 0x2>;
  2379. clocks = <0x34 0x35 0x8 0x18>;
  2380. clock-output-names = "clk_uart2";
  2381. #clock-cells = <0x0>;
  2382. rockchip,clkops-idx = <0xe>;
  2383. rockchip,flags = <0x4>;
  2384. linux,phandle = <0xa5>;
  2385. phandle = <0xa5>;
  2386. };
  2387. };
  2388.  
  2389. sel-con@00a0 {
  2390. compatible = "rockchip,rk3188-selcon";
  2391. reg = <0xa0 0x4>;
  2392. #address-cells = <0x1>;
  2393. #size-cells = <0x1>;
  2394.  
  2395. clk_uart3_div {
  2396. compatible = "rockchip,rk3188-div-con";
  2397. rockchip,bits = <0x0 0x7>;
  2398. clocks = <0x19>;
  2399. clock-output-names = "clk_uart3_div";
  2400. rockchip,div-type = <0x0>;
  2401. #clock-cells = <0x0>;
  2402. linux,phandle = <0x36>;
  2403. phandle = <0x36>;
  2404. };
  2405.  
  2406. uart3_mux {
  2407. compatible = "rockchip,rk3188-mux-con";
  2408. rockchip,bits = <0x8 0x2>;
  2409. clocks = <0x36 0x37 0x8 0x18>;
  2410. clock-output-names = "clk_uart3";
  2411. #clock-cells = <0x0>;
  2412. rockchip,clkops-idx = <0xe>;
  2413. rockchip,flags = <0x4>;
  2414. linux,phandle = <0xa9>;
  2415. phandle = <0xa9>;
  2416. };
  2417. };
  2418.  
  2419. sel-con@00a4 {
  2420. compatible = "rockchip,rk3188-selcon";
  2421. reg = <0xa4 0x4>;
  2422. #address-cells = <0x1>;
  2423. #size-cells = <0x1>;
  2424.  
  2425. uart0_frac {
  2426. compatible = "rockchip,rk3188-frac-con";
  2427. clocks = <0x2c>;
  2428. clock-output-names = "uart0_frac";
  2429. rockchip,bits = <0x0 0x20>;
  2430. rockchip,clkops-idx = <0x5>;
  2431. #clock-cells = <0x0>;
  2432. linux,phandle = <0x2d>;
  2433. phandle = <0x2d>;
  2434. };
  2435. };
  2436.  
  2437. sel-con@00a8 {
  2438. compatible = "rockchip,rk3188-selcon";
  2439. reg = <0xa8 0x4>;
  2440. #address-cells = <0x1>;
  2441. #size-cells = <0x1>;
  2442.  
  2443. uart1_frac {
  2444. compatible = "rockchip,rk3188-frac-con";
  2445. clocks = <0x32>;
  2446. clock-output-names = "uart1_frac";
  2447. rockchip,bits = <0x0 0x20>;
  2448. rockchip,clkops-idx = <0x5>;
  2449. #clock-cells = <0x0>;
  2450. linux,phandle = <0x33>;
  2451. phandle = <0x33>;
  2452. };
  2453. };
  2454.  
  2455. sel-con@00ac {
  2456. compatible = "rockchip,rk3188-selcon";
  2457. reg = <0xac 0x4>;
  2458. #address-cells = <0x1>;
  2459. #size-cells = <0x1>;
  2460.  
  2461. uart2_frac {
  2462. compatible = "rockchip,rk3188-frac-con";
  2463. clocks = <0x34>;
  2464. clock-output-names = "uart2_frac";
  2465. rockchip,bits = <0x0 0x20>;
  2466. rockchip,clkops-idx = <0x5>;
  2467. #clock-cells = <0x0>;
  2468. linux,phandle = <0x35>;
  2469. phandle = <0x35>;
  2470. };
  2471. };
  2472.  
  2473. sel-con@00b0 {
  2474. compatible = "rockchip,rk3188-selcon";
  2475. reg = <0xb0 0x4>;
  2476. #address-cells = <0x1>;
  2477. #size-cells = <0x1>;
  2478.  
  2479. uart3_frac {
  2480. compatible = "rockchip,rk3188-frac-con";
  2481. clocks = <0x36>;
  2482. clock-output-names = "uart3_frac";
  2483. rockchip,bits = <0x0 0x20>;
  2484. rockchip,clkops-idx = <0x5>;
  2485. #clock-cells = <0x0>;
  2486. linux,phandle = <0x37>;
  2487. phandle = <0x37>;
  2488. };
  2489. };
  2490.  
  2491. sel-con@00b4 {
  2492. compatible = "rockchip,rk3188-selcon";
  2493. reg = <0xb4 0x4>;
  2494. #address-cells = <0x1>;
  2495. #size-cells = <0x1>;
  2496.  
  2497. clk_mac_pll_mux {
  2498. compatible = "rockchip,rk3188-mux-con";
  2499. rockchip,bits = <0x0 0x2>;
  2500. clocks = <0x25 0x15 0x16>;
  2501. clock-output-names = "clk_mac_pll";
  2502. #clock-cells = <0x0>;
  2503. linux,phandle = <0x38>;
  2504. phandle = <0x38>;
  2505. };
  2506.  
  2507. clk_mac_mux {
  2508. compatible = "rockchip,rk3188-mux-con";
  2509. rockchip,bits = <0x4 0x1>;
  2510. clocks = <0x38 0x39>;
  2511. clock-output-names = "clk_mac";
  2512. #clock-cells = <0x0>;
  2513. rockchip,clkops-idx = <0xa>;
  2514. rockchip,flags = <0x4>;
  2515. #clock-init-cells = <0x1>;
  2516. linux,phandle = <0x67>;
  2517. phandle = <0x67>;
  2518. };
  2519.  
  2520. clk_mac_pll_div {
  2521. compatible = "rockchip,rk3188-div-con";
  2522. rockchip,bits = <0x8 0x5>;
  2523. clocks = <0x38>;
  2524. clock-output-names = "clk_mac_pll";
  2525. rockchip,div-type = <0x0>;
  2526. #clock-cells = <0x0>;
  2527. rockchip,clkops-idx = <0x1>;
  2528. };
  2529. };
  2530.  
  2531. sel-con@00b8 {
  2532. compatible = "rockchip,rk3188-selcon";
  2533. reg = <0xb8 0x4>;
  2534. #address-cells = <0x1>;
  2535. #size-cells = <0x1>;
  2536.  
  2537. clk_hsadc_pll_mux {
  2538. compatible = "rockchip,rk3188-mux-con";
  2539. rockchip,bits = <0x0 0x1>;
  2540. clocks = <0x15 0x16>;
  2541. clock-output-names = "clk_hsadc_pll";
  2542. #clock-cells = <0x0>;
  2543. linux,phandle = <0x3a>;
  2544. phandle = <0x3a>;
  2545. };
  2546.  
  2547. clk_hsadc_out {
  2548. compatible = "rockchip,rk3188-mux-con";
  2549. rockchip,bits = <0x4 0x1>;
  2550. clocks = <0x3a 0x3b>;
  2551. clock-output-names = "clk_hsadc_out";
  2552. #clock-cells = <0x0>;
  2553. rockchip,clkops-idx = <0x9>;
  2554. rockchip,flags = <0x4>;
  2555. linux,phandle = <0xa>;
  2556. phandle = <0xa>;
  2557. };
  2558.  
  2559. clk_hsadc {
  2560. compatible = "rockchip,rk3188-mux-con";
  2561. rockchip,bits = <0x7 0x1>;
  2562. clocks = <0xa 0x3c>;
  2563. clock-output-names = "clk_hsadc";
  2564. #clock-cells = <0x0>;
  2565. };
  2566.  
  2567. clk_hsadc_pll_div {
  2568. compatible = "rockchip,rk3188-div-con";
  2569. rockchip,bits = <0x8 0x8>;
  2570. clocks = <0x3a>;
  2571. clock-output-names = "clk_hsadc_pll";
  2572. rockchip,div-type = <0x0>;
  2573. #clock-cells = <0x0>;
  2574. rockchip,clkops-idx = <0x1>;
  2575. };
  2576. };
  2577.  
  2578. sel-con@00c0 {
  2579. compatible = "rockchip,rk3188-selcon";
  2580. reg = <0xc0 0x4>;
  2581. #address-cells = <0x1>;
  2582. #size-cells = <0x1>;
  2583.  
  2584. clk_saradc_div {
  2585. compatible = "rockchip,rk3188-div-con";
  2586. rockchip,bits = <0x8 0x8>;
  2587. clocks = <0x8>;
  2588. clock-output-names = "clk_saradc";
  2589. rockchip,div-type = <0x0>;
  2590. #clock-cells = <0x0>;
  2591. linux,phandle = <0x61>;
  2592. phandle = <0x61>;
  2593. };
  2594. };
  2595.  
  2596. sel-con@00c4 {
  2597. compatible = "rockchip,rk3188-selcon";
  2598. reg = <0xc4 0x4>;
  2599. #address-cells = <0x1>;
  2600. #size-cells = <0x1>;
  2601.  
  2602. clk_spi0_div {
  2603. compatible = "rockchip,rk3188-div-con";
  2604. rockchip,bits = <0x0 0x7>;
  2605. clocks = <0x3d>;
  2606. clock-output-names = "clk_spi0";
  2607. rockchip,div-type = <0x0>;
  2608. #clock-cells = <0x0>;
  2609. rockchip,clkops-idx = <0x1>;
  2610. };
  2611.  
  2612. clk_spi0_mux {
  2613. compatible = "rockchip,rk3188-mux-con";
  2614. rockchip,bits = <0x7 0x1>;
  2615. clocks = <0x15 0x16>;
  2616. clock-output-names = "clk_spi0";
  2617. #clock-cells = <0x0>;
  2618. linux,phandle = <0x3d>;
  2619. phandle = <0x3d>;
  2620. };
  2621.  
  2622. clk_spi1_div {
  2623. compatible = "rockchip,rk3188-div-con";
  2624. rockchip,bits = <0x8 0x7>;
  2625. clocks = <0x3e>;
  2626. clock-output-names = "clk_spi1";
  2627. rockchip,div-type = <0x0>;
  2628. #clock-cells = <0x0>;
  2629. rockchip,clkops-idx = <0x1>;
  2630. };
  2631.  
  2632. clk_spi1_mux {
  2633. compatible = "rockchip,rk3188-mux-con";
  2634. rockchip,bits = <0xf 0x1>;
  2635. clocks = <0x15 0x16>;
  2636. clock-output-names = "clk_spi1";
  2637. #clock-cells = <0x0>;
  2638. linux,phandle = <0x3e>;
  2639. phandle = <0x3e>;
  2640. };
  2641. };
  2642.  
  2643. sel-con@00c8 {
  2644. compatible = "rockchip,rk3188-selcon";
  2645. reg = <0xc8 0x4>;
  2646. #address-cells = <0x1>;
  2647. #size-cells = <0x1>;
  2648.  
  2649. ddr_div {
  2650. compatible = "rockchip,rk3188-div-con";
  2651. rockchip,bits = <0x0 0x2>;
  2652. clocks = <0x3f>;
  2653. clock-output-names = "clk_ddr";
  2654. rockchip,div-type = <0x80>;
  2655. rockchip,div-relations = <0x0 0x1 0x1 0x2 0x3 0x4>;
  2656. #clock-cells = <0x0>;
  2657. rockchip,flags = <0xc0>;
  2658. rockchip,clkops-idx = <0xd>;
  2659. };
  2660.  
  2661. ddr_clk_pll_mux {
  2662. compatible = "rockchip,rk3188-mux-con";
  2663. rockchip,bits = <0x2 0x1>;
  2664. clocks = <0x40 0x16>;
  2665. clock-output-names = "clk_ddr";
  2666. #clock-cells = <0x0>;
  2667. linux,phandle = <0x3f>;
  2668. phandle = <0x3f>;
  2669. };
  2670.  
  2671. crypto_div {
  2672. compatible = "rockchip,rk3188-div-con";
  2673. rockchip,bits = <0x6 0x2>;
  2674. clocks = <0x14>;
  2675. clock-output-names = "clk_crypto";
  2676. rockchip,div-type = <0x0>;
  2677. #clock-cells = <0x0>;
  2678. #clock-init-cells = <0x1>;
  2679. linux,phandle = <0x68>;
  2680. phandle = <0x68>;
  2681. };
  2682.  
  2683. clk_cif_pll_mux {
  2684. compatible = "rockchip,rk3188-mux-con";
  2685. rockchip,bits = <0x8 0x1>;
  2686. clocks = <0x15 0x16>;
  2687. clock-output-names = "clk_cif_pll";
  2688. #clock-cells = <0x0>;
  2689. linux,phandle = <0x42>;
  2690. phandle = <0x42>;
  2691. };
  2692.  
  2693. clk_cif_out_div {
  2694. compatible = "rockchip,rk3188-div-con";
  2695. rockchip,bits = <0x9 0x5>;
  2696. clocks = <0x41>;
  2697. clock-output-names = "clk_cif_out";
  2698. rockchip,div-type = <0x0>;
  2699. #clock-cells = <0x0>;
  2700. rockchip,clkops-idx = <0x1>;
  2701. };
  2702.  
  2703. clk_cif_out_mux {
  2704. compatible = "rockchip,rk3188-mux-con";
  2705. rockchip,bits = <0xf 0x1>;
  2706. clocks = <0x42 0x8>;
  2707. clock-output-names = "clk_cif_out";
  2708. #clock-cells = <0x0>;
  2709. linux,phandle = <0x41>;
  2710. phandle = <0x41>;
  2711. };
  2712. };
  2713.  
  2714. sel-con@00cc {
  2715. compatible = "rockchip,rk3188-selcon";
  2716. reg = <0xcc 0x4>;
  2717. #address-cells = <0x1>;
  2718. #size-cells = <0x1>;
  2719.  
  2720. dclk_lcdc0_mux {
  2721. compatible = "rockchip,rk3188-mux-con";
  2722. rockchip,bits = <0x0 0x2>;
  2723. clocks = <0x43 0x16 0x25>;
  2724. clock-output-names = "dclk_lcdc0";
  2725. #clock-cells = <0x0>;
  2726. linux,phandle = <0x44>;
  2727. phandle = <0x44>;
  2728. };
  2729.  
  2730. dclk_lcdc0_div {
  2731. compatible = "rockchip,rk3188-div-con";
  2732. rockchip,bits = <0x8 0x8>;
  2733. clocks = <0x44>;
  2734. clock-output-names = "dclk_lcdc0";
  2735. rockchip,div-type = <0x0>;
  2736. #clock-cells = <0x0>;
  2737. rockchip,clkops-idx = <0x10>;
  2738. rockchip,flags = <0x4>;
  2739. };
  2740. };
  2741.  
  2742. sel-con@00d0 {
  2743. compatible = "rockchip,rk3188-selcon";
  2744. reg = <0xd0 0x4>;
  2745. #address-cells = <0x1>;
  2746. #size-cells = <0x1>;
  2747.  
  2748. clk_edp_div {
  2749. compatible = "rockchip,rk3188-div-con";
  2750. rockchip,bits = <0x0 0x6>;
  2751. clocks = <0x45>;
  2752. clock-output-names = "clk_edp";
  2753. rockchip,div-type = <0x0>;
  2754. #clock-cells = <0x0>;
  2755. rockchip,clkops-idx = <0x1>;
  2756. };
  2757.  
  2758. clk_edp_mux {
  2759. compatible = "rockchip,rk3188-mux-con";
  2760. rockchip,bits = <0x6 0x2>;
  2761. clocks = <0x15 0x16 0x25>;
  2762. clock-output-names = "clk_edp";
  2763. #clock-cells = <0x0>;
  2764. #clock-init-cells = <0x1>;
  2765. linux,phandle = <0x45>;
  2766. phandle = <0x45>;
  2767. };
  2768.  
  2769. hclk_vio_div {
  2770. compatible = "rockchip,rk3188-div-con";
  2771. rockchip,bits = <0x8 0x5>;
  2772. clocks = <0x46>;
  2773. clock-output-names = "hclk_vio";
  2774. rockchip,div-type = <0x0>;
  2775. #clock-cells = <0x0>;
  2776. #clock-init-cells = <0x1>;
  2777. linux,phandle = <0x76>;
  2778. phandle = <0x76>;
  2779. };
  2780.  
  2781. edp_24m_mux {
  2782. compatible = "rockchip,rk3188-mux-con";
  2783. rockchip,bits = <0xf 0x1>;
  2784. clocks = <0x47 0x8>;
  2785. clock-output-names = "clk_edp_24m";
  2786. #clock-cells = <0x0>;
  2787. linux,phandle = <0x62>;
  2788. phandle = <0x62>;
  2789. };
  2790. };
  2791.  
  2792. sel-con@00d4 {
  2793. compatible = "rockchip,rk3188-selcon";
  2794. reg = <0xd4 0x4>;
  2795. #address-cells = <0x1>;
  2796. #size-cells = <0x1>;
  2797.  
  2798. hsicphy_480m_mux {
  2799. compatible = "rockchip,rk3188-mux-con";
  2800. rockchip,bits = <0x0 0x2>;
  2801. clocks = <0x15 0x16 0x31>;
  2802. clock-output-names = "hsicphy_480m";
  2803. #clock-cells = <0x0>;
  2804. linux,phandle = <0x29>;
  2805. phandle = <0x29>;
  2806. };
  2807.  
  2808. hsicphy_12m_mux {
  2809. compatible = "rockchip,rk3188-mux-con";
  2810. rockchip,bits = <0x2 0x1>;
  2811. clocks = <0x9 0x9 0x48>;
  2812. clock-output-names = "hsicphy_12m";
  2813. #clock-cells = <0x0>;
  2814. linux,phandle = <0xe5>;
  2815. phandle = <0xe5>;
  2816. };
  2817.  
  2818. clkin_isp {
  2819. compatible = "rockchip,rk3188-mux-con";
  2820. rockchip,bits = <0x3 0x1>;
  2821. clocks = <0xb 0x3 0x49>;
  2822. clock-output-names = "clkin_isp";
  2823. #clock-cells = <0x0>;
  2824. linux,phandle = <0xea>;
  2825. phandle = <0xea>;
  2826. };
  2827.  
  2828. clkin_cif {
  2829. compatible = "rockchip,rk3188-mux-con";
  2830. rockchip,bits = <0x4 0x1>;
  2831. clocks = <0xb 0x0 0x4a>;
  2832. clock-output-names = "clkin_cif";
  2833. #clock-cells = <0x0>;
  2834. };
  2835.  
  2836. dclk_lcdc1_mux {
  2837. compatible = "rockchip,rk3188-mux-con";
  2838. rockchip,bits = <0x6 0x2>;
  2839. clocks = <0x43 0x16 0x25>;
  2840. clock-output-names = "dclk_lcdc1";
  2841. #clock-cells = <0x0>;
  2842. linux,phandle = <0x4b>;
  2843. phandle = <0x4b>;
  2844. };
  2845.  
  2846. dclk_lcdc1_div {
  2847. compatible = "rockchip,rk3188-div-con";
  2848. rockchip,bits = <0x8 0x8>;
  2849. clocks = <0x4b>;
  2850. clock-output-names = "dclk_lcdc1";
  2851. rockchip,div-type = <0x0>;
  2852. #clock-cells = <0x0>;
  2853. rockchip,clkops-idx = <0x11>;
  2854. rockchip,flags = <0x4>;
  2855. };
  2856. };
  2857.  
  2858. sel-con@00d8 {
  2859. compatible = "rockchip,rk3188-selcon";
  2860. reg = <0xd8 0x4>;
  2861. #address-cells = <0x1>;
  2862. #size-cells = <0x1>;
  2863.  
  2864. aclk_rga_div {
  2865. compatible = "rockchip,rk3188-div-con";
  2866. rockchip,bits = <0x0 0x5>;
  2867. clocks = <0x4c>;
  2868. clock-output-names = "aclk_rga";
  2869. rockchip,div-type = <0x0>;
  2870. #clock-cells = <0x0>;
  2871. rockchip,clkops-idx = <0x1>;
  2872. };
  2873.  
  2874. aclk_rga_mux {
  2875. compatible = "rockchip,rk3188-mux-con";
  2876. rockchip,bits = <0x6 0x2>;
  2877. clocks = <0x15 0x16 0x31>;
  2878. clock-output-names = "aclk_rga";
  2879. #clock-cells = <0x0>;
  2880. #clock-init-cells = <0x1>;
  2881. linux,phandle = <0x4c>;
  2882. phandle = <0x4c>;
  2883. };
  2884.  
  2885. clk_rga_div {
  2886. compatible = "rockchip,rk3188-div-con";
  2887. rockchip,bits = <0x8 0x5>;
  2888. clocks = <0x4d>;
  2889. clock-output-names = "clk_rga";
  2890. rockchip,div-type = <0x0>;
  2891. #clock-cells = <0x0>;
  2892. rockchip,clkops-idx = <0x1>;
  2893. };
  2894.  
  2895. clk_rga_mux {
  2896. compatible = "rockchip,rk3188-mux-con";
  2897. rockchip,bits = <0xe 0x2>;
  2898. clocks = <0x15 0x16 0x31>;
  2899. clock-output-names = "clk_rga";
  2900. #clock-cells = <0x0>;
  2901. #clock-init-cells = <0x1>;
  2902. linux,phandle = <0x4d>;
  2903. phandle = <0x4d>;
  2904. };
  2905. };
  2906.  
  2907. sel-con@00dc {
  2908. compatible = "rockchip,rk3188-selcon";
  2909. reg = <0xdc 0x4>;
  2910. #address-cells = <0x1>;
  2911. #size-cells = <0x1>;
  2912.  
  2913. aclk_vio0_div {
  2914. compatible = "rockchip,rk3188-div-con";
  2915. rockchip,bits = <0x0 0x5>;
  2916. clocks = <0x46>;
  2917. clock-output-names = "aclk_vio0";
  2918. rockchip,div-type = <0x0>;
  2919. #clock-cells = <0x0>;
  2920. rockchip,clkops-idx = <0x1>;
  2921. rockchip,flags = <0x80>;
  2922. };
  2923.  
  2924. aclk_vio0_mux {
  2925. compatible = "rockchip,rk3188-mux-con";
  2926. rockchip,bits = <0x6 0x2>;
  2927. clocks = <0x43 0x16 0x31>;
  2928. clock-output-names = "aclk_vio0";
  2929. #clock-cells = <0x0>;
  2930. #clock-init-cells = <0x1>;
  2931. linux,phandle = <0x46>;
  2932. phandle = <0x46>;
  2933. };
  2934.  
  2935. aclk_vio1_div {
  2936. compatible = "rockchip,rk3188-div-con";
  2937. rockchip,bits = <0x8 0x5>;
  2938. clocks = <0x4e>;
  2939. clock-output-names = "aclk_vio1";
  2940. rockchip,div-type = <0x0>;
  2941. #clock-cells = <0x0>;
  2942. rockchip,clkops-idx = <0x1>;
  2943. rockchip,flags = <0x80>;
  2944. };
  2945.  
  2946. aclk_vio1_mux {
  2947. compatible = "rockchip,rk3188-mux-con";
  2948. rockchip,bits = <0xe 0x2>;
  2949. clocks = <0x43 0x16 0x31>;
  2950. clock-output-names = "aclk_vio1";
  2951. #clock-cells = <0x0>;
  2952. #clock-init-cells = <0x1>;
  2953. linux,phandle = <0x4e>;
  2954. phandle = <0x4e>;
  2955. };
  2956. };
  2957.  
  2958. sel-con@00e0 {
  2959. compatible = "rockchip,rk3188-selcon";
  2960. reg = <0xe0 0x4>;
  2961. #address-cells = <0x1>;
  2962. #size-cells = <0x1>;
  2963.  
  2964. clk_vepu_div {
  2965. compatible = "rockchip,rk3188-div-con";
  2966. rockchip,bits = <0x0 0x5>;
  2967. clocks = <0xc>;
  2968. clock-output-names = "clk_vepu";
  2969. rockchip,div-type = <0x0>;
  2970. #clock-cells = <0x0>;
  2971. rockchip,clkops-idx = <0x1>;
  2972. };
  2973.  
  2974. clk_vepu_mux {
  2975. compatible = "rockchip,rk3188-mux-con";
  2976. rockchip,bits = <0x6 0x2>;
  2977. clocks = <0x15 0x16 0x31>;
  2978. clock-output-names = "clk_vepu";
  2979. #clock-cells = <0x0>;
  2980. #clock-init-cells = <0x1>;
  2981. linux,phandle = <0xc>;
  2982. phandle = <0xc>;
  2983. };
  2984.  
  2985. clk_vdpu_div {
  2986. compatible = "rockchip,rk3188-div-con";
  2987. rockchip,bits = <0x8 0x5>;
  2988. clocks = <0xd>;
  2989. clock-output-names = "clk_vdpu";
  2990. rockchip,div-type = <0x0>;
  2991. #clock-cells = <0x0>;
  2992. rockchip,clkops-idx = <0x1>;
  2993. };
  2994.  
  2995. clk_vdpu_mux {
  2996. compatible = "rockchip,rk3188-mux-con";
  2997. rockchip,bits = <0xe 0x2>;
  2998. clocks = <0x15 0x16 0x31>;
  2999. clock-output-names = "clk_vdpu";
  3000. #clock-cells = <0x0>;
  3001. #clock-init-cells = <0x1>;
  3002. linux,phandle = <0xd>;
  3003. phandle = <0xd>;
  3004. };
  3005. };
  3006.  
  3007. sel-con@00e4 {
  3008. compatible = "rockchip,rk3188-selcon";
  3009. reg = <0xe4 0x4>;
  3010. #address-cells = <0x1>;
  3011. #size-cells = <0x1>;
  3012.  
  3013. pclk_pd_pmu_div {
  3014. compatible = "rockchip,rk3188-div-con";
  3015. rockchip,bits = <0x0 0x5>;
  3016. clocks = <0x16>;
  3017. clock-output-names = "pclk_pd_pmu";
  3018. rockchip,div-type = <0x0>;
  3019. #clock-cells = <0x0>;
  3020. #clock-init-cells = <0x1>;
  3021. linux,phandle = <0x69>;
  3022. phandle = <0x69>;
  3023. };
  3024.  
  3025. pclk_pd_alive {
  3026. compatible = "rockchip,rk3188-div-con";
  3027. rockchip,bits = <0x8 0x5>;
  3028. clocks = <0x16>;
  3029. clock-output-names = "pclk_pd_alive";
  3030. rockchip,div-type = <0x0>;
  3031. #clock-cells = <0x0>;
  3032. #clock-init-cells = <0x1>;
  3033. linux,phandle = <0x75>;
  3034. phandle = <0x75>;
  3035. };
  3036. };
  3037.  
  3038. sel-con@00e8 {
  3039. compatible = "rockchip,rk3188-selcon";
  3040. reg = <0xe8 0x4>;
  3041. #address-cells = <0x1>;
  3042. #size-cells = <0x1>;
  3043.  
  3044. clk_gpu_div {
  3045. compatible = "rockchip,rk3188-div-con";
  3046. rockchip,bits = <0x0 0x5>;
  3047. clocks = <0x4f>;
  3048. clock-output-names = "clk_gpu";
  3049. rockchip,div-type = <0x0>;
  3050. #clock-cells = <0x0>;
  3051. rockchip,clkops-idx = <0x1>;
  3052. rockchip,flags = <0x100>;
  3053. };
  3054.  
  3055. clk_gpu_mux {
  3056. compatible = "rockchip,rk3188-mux-con";
  3057. rockchip,bits = <0x6 0x2>;
  3058. clocks = <0x15 0x16 0x31 0x25>;
  3059. clock-output-names = "clk_gpu";
  3060. #clock-cells = <0x0>;
  3061. #clock-init-cells = <0x1>;
  3062. linux,phandle = <0x4f>;
  3063. phandle = <0x4f>;
  3064. };
  3065.  
  3066. clk_sdio1_div {
  3067. compatible = "rockchip,rk3188-div-con";
  3068. rockchip,bits = <0x8 0x6>;
  3069. clocks = <0x50>;
  3070. clock-output-names = "clk_sdio1";
  3071. rockchip,div-type = <0x0>;
  3072. #clock-cells = <0x0>;
  3073. rockchip,clkops-idx = <0x3>;
  3074. };
  3075.  
  3076. clk_sdio1_mux {
  3077. compatible = "rockchip,rk3188-mux-con";
  3078. rockchip,bits = <0xe 0x2>;
  3079. clocks = <0x15 0x16 0x8>;
  3080. clock-output-names = "clk_sdio1";
  3081. #clock-cells = <0x0>;
  3082. linux,phandle = <0x50>;
  3083. phandle = <0x50>;
  3084. };
  3085. };
  3086.  
  3087. sel-con@00ec {
  3088. compatible = "rockchip,rk3188-selcon";
  3089. reg = <0xec 0x4>;
  3090. #address-cells = <0x1>;
  3091. #size-cells = <0x1>;
  3092.  
  3093. clk_tsp_div {
  3094. compatible = "rockchip,rk3188-div-con";
  3095. rockchip,bits = <0x0 0x5>;
  3096. clocks = <0x51>;
  3097. clock-output-names = "clk_tsp";
  3098. rockchip,div-type = <0x0>;
  3099. #clock-cells = <0x0>;
  3100. rockchip,clkops-idx = <0x1>;
  3101. };
  3102.  
  3103. clk_tsp_mux {
  3104. compatible = "rockchip,rk3188-mux-con";
  3105. rockchip,bits = <0x6 0x2>;
  3106. clocks = <0x15 0x16 0x25>;
  3107. clock-output-names = "clk_tsp";
  3108. #clock-cells = <0x0>;
  3109. #clock-init-cells = <0x1>;
  3110. linux,phandle = <0x51>;
  3111. phandle = <0x51>;
  3112. };
  3113.  
  3114. clk_tspout_div {
  3115. compatible = "rockchip,rk3188-div-con";
  3116. rockchip,bits = <0x8 0x5>;
  3117. clocks = <0x52>;
  3118. clock-output-names = "clk_tspout";
  3119. rockchip,div-type = <0x0>;
  3120. #clock-cells = <0x0>;
  3121. rockchip,clkops-idx = <0x1>;
  3122. };
  3123.  
  3124. clk_tspout_mux {
  3125. compatible = "rockchip,rk3188-mux-con";
  3126. rockchip,bits = <0xe 0x2>;
  3127. clocks = <0x15 0x16 0x25 0x53>;
  3128. clock-output-names = "clk_tspout";
  3129. #clock-cells = <0x0>;
  3130. #clock-init-cells = <0x1>;
  3131. linux,phandle = <0x52>;
  3132. phandle = <0x52>;
  3133. };
  3134. };
  3135.  
  3136. sel-con@00f0 {
  3137. compatible = "rockchip,rk3188-selcon";
  3138. reg = <0xf0 0x4>;
  3139. #address-cells = <0x1>;
  3140. #size-cells = <0x1>;
  3141.  
  3142. clk_core0_div {
  3143. compatible = "rockchip,rk3188-div-con";
  3144. rockchip,bits = <0x0 0x3>;
  3145. clocks = <0xf>;
  3146. clock-output-names = "clk_core0";
  3147. rockchip,div-type = <0x0>;
  3148. #clock-cells = <0x0>;
  3149. rockchip,clkops-idx = <0xc>;
  3150. linux,phandle = <0x6c>;
  3151. phandle = <0x6c>;
  3152. };
  3153.  
  3154. clk_core1_div {
  3155. compatible = "rockchip,rk3188-div-con";
  3156. rockchip,bits = <0x4 0x3>;
  3157. clocks = <0xf>;
  3158. clock-output-names = "clk_core1";
  3159. rockchip,div-type = <0x0>;
  3160. #clock-cells = <0x0>;
  3161. rockchip,clkops-idx = <0xc>;
  3162. linux,phandle = <0x6d>;
  3163. phandle = <0x6d>;
  3164. };
  3165.  
  3166. clk_core2_div {
  3167. compatible = "rockchip,rk3188-div-con";
  3168. rockchip,bits = <0x8 0x3>;
  3169. clocks = <0xf>;
  3170. clock-output-names = "clk_core2";
  3171. rockchip,div-type = <0x0>;
  3172. #clock-cells = <0x0>;
  3173. rockchip,clkops-idx = <0xc>;
  3174. linux,phandle = <0x6e>;
  3175. phandle = <0x6e>;
  3176. };
  3177.  
  3178. clk_core3_div {
  3179. compatible = "rockchip,rk3188-div-con";
  3180. rockchip,bits = <0xc 0x3>;
  3181. clocks = <0xf>;
  3182. clock-output-names = "clk_core3";
  3183. rockchip,div-type = <0x0>;
  3184. #clock-cells = <0x0>;
  3185. rockchip,clkops-idx = <0xc>;
  3186. linux,phandle = <0x6f>;
  3187. phandle = <0x6f>;
  3188. };
  3189. };
  3190.  
  3191. sel-con@00f4 {
  3192. compatible = "rockchip,rk3188-selcon";
  3193. reg = <0xf4 0x4>;
  3194. #address-cells = <0x1>;
  3195. #size-cells = <0x1>;
  3196.  
  3197. clk_l2ram_div {
  3198. compatible = "rockchip,rk3188-div-con";
  3199. rockchip,bits = <0x0 0x3>;
  3200. clocks = <0xf>;
  3201. clock-output-names = "clk_l2ram";
  3202. rockchip,div-type = <0x0>;
  3203. #clock-cells = <0x0>;
  3204. rockchip,clkops-idx = <0xc>;
  3205. linux,phandle = <0x70>;
  3206. phandle = <0x70>;
  3207. };
  3208.  
  3209. atclk_core_div {
  3210. compatible = "rockchip,rk3188-div-con";
  3211. rockchip,bits = <0x4 0x5>;
  3212. clocks = <0xf>;
  3213. clock-output-names = "atclk_core";
  3214. rockchip,div-type = <0x0>;
  3215. #clock-cells = <0x0>;
  3216. rockchip,clkops-idx = <0xc>;
  3217. linux,phandle = <0x73>;
  3218. phandle = <0x73>;
  3219. };
  3220.  
  3221. pclk_core_dbg_div {
  3222. compatible = "rockchip,rk3188-div-con";
  3223. rockchip,bits = <0x9 0x5>;
  3224. clocks = <0xf>;
  3225. clock-output-names = "pclk_dbg_src";
  3226. rockchip,div-type = <0x0>;
  3227. #clock-cells = <0x0>;
  3228. rockchip,clkops-idx = <0xc>;
  3229. linux,phandle = <0x74>;
  3230. phandle = <0x74>;
  3231. };
  3232. };
  3233.  
  3234. sel-con@00f8 {
  3235. compatible = "rockchip,rk3188-selcon";
  3236. reg = <0xf8 0x4>;
  3237. #address-cells = <0x1>;
  3238. #size-cells = <0x1>;
  3239.  
  3240. clk_nandc0_div {
  3241. compatible = "rockchip,rk3188-div-con";
  3242. rockchip,bits = <0x0 0x5>;
  3243. clocks = <0x54>;
  3244. clock-output-names = "clk_nandc0";
  3245. rockchip,div-type = <0x0>;
  3246. #clock-cells = <0x0>;
  3247. rockchip,clkops-idx = <0x1>;
  3248. };
  3249.  
  3250. clk_nandc0_mux {
  3251. compatible = "rockchip,rk3188-mux-con";
  3252. rockchip,bits = <0x7 0x1>;
  3253. clocks = <0x15 0x16>;
  3254. clock-output-names = "clk_nandc0";
  3255. #clock-cells = <0x0>;
  3256. linux,phandle = <0x54>;
  3257. phandle = <0x54>;
  3258. };
  3259.  
  3260. clk_nandc1_div {
  3261. compatible = "rockchip,rk3188-div-con";
  3262. rockchip,bits = <0x8 0x5>;
  3263. clocks = <0x55>;
  3264. clock-output-names = "clk_nandc1";
  3265. rockchip,div-type = <0x0>;
  3266. #clock-cells = <0x0>;
  3267. rockchip,clkops-idx = <0x1>;
  3268. };
  3269.  
  3270. clk_nandc1_mux {
  3271. compatible = "rockchip,rk3188-mux-con";
  3272. rockchip,bits = <0xf 0x1>;
  3273. clocks = <0x15 0x16>;
  3274. clock-output-names = "clk_nandc1";
  3275. #clock-cells = <0x0>;
  3276. linux,phandle = <0x55>;
  3277. phandle = <0x55>;
  3278. };
  3279. };
  3280.  
  3281. sel-con@00fc {
  3282. compatible = "rockchip,rk3188-selcon";
  3283. reg = <0xfc 0x4>;
  3284. #address-cells = <0x1>;
  3285. #size-cells = <0x1>;
  3286.  
  3287. clk_spi2_div {
  3288. compatible = "rockchip,rk3188-div-con";
  3289. rockchip,bits = <0x0 0x7>;
  3290. clocks = <0x56>;
  3291. clock-output-names = "clk_spi2";
  3292. rockchip,div-type = <0x0>;
  3293. #clock-cells = <0x0>;
  3294. rockchip,clkops-idx = <0x1>;
  3295. };
  3296.  
  3297. clk_spi2_mux {
  3298. compatible = "rockchip,rk3188-mux-con";
  3299. rockchip,bits = <0x7 0x1>;
  3300. clocks = <0x15 0x16>;
  3301. clock-output-names = "clk_spi2";
  3302. #clock-cells = <0x0>;
  3303. linux,phandle = <0x56>;
  3304. phandle = <0x56>;
  3305. };
  3306.  
  3307. aclk_hevc_div {
  3308. compatible = "rockchip,rk3188-div-con";
  3309. rockchip,bits = <0x8 0x5>;
  3310. clocks = <0x57>;
  3311. clock-output-names = "aclk_hevc";
  3312. rockchip,div-type = <0x0>;
  3313. #clock-cells = <0x0>;
  3314. rockchip,clkops-idx = <0x1>;
  3315. rockchip,flags = <0x100>;
  3316. };
  3317.  
  3318. aclk_hevc_mux {
  3319. compatible = "rockchip,rk3188-mux-con";
  3320. rockchip,bits = <0xe 0x2>;
  3321. clocks = <0x15 0x16 0x25>;
  3322. clock-output-names = "aclk_hevc";
  3323. #clock-cells = <0x0>;
  3324. #clock-init-cells = <0x1>;
  3325. linux,phandle = <0x57>;
  3326. phandle = <0x57>;
  3327. };
  3328. };
  3329.  
  3330. sel-con@0100 {
  3331. compatible = "rockchip,rk3188-selcon";
  3332. reg = <0x100 0x4>;
  3333. #address-cells = <0x1>;
  3334. #size-cells = <0x1>;
  3335.  
  3336. spdif_8ch_div {
  3337. compatible = "rockchip,rk3188-div-con";
  3338. rockchip,bits = <0x0 0x7>;
  3339. clocks = <0x21>;
  3340. clock-output-names = "spdif_8ch_div";
  3341. rockchip,div-type = <0x0>;
  3342. #clock-cells = <0x0>;
  3343. linux,phandle = <0x58>;
  3344. phandle = <0x58>;
  3345. };
  3346.  
  3347. spdif_8ch_clk_mux {
  3348. compatible = "rockchip,rk3188-mux-con";
  3349. rockchip,bits = <0x8 0x2>;
  3350. clocks = <0x58 0x59 0x1f>;
  3351. clock-output-names = "clk_spdif_8ch";
  3352. #clock-cells = <0x0>;
  3353. rockchip,clkops-idx = <0xe>;
  3354. rockchip,flags = <0x4>;
  3355. linux,phandle = <0x65>;
  3356. phandle = <0x65>;
  3357. };
  3358.  
  3359. hclk_hevc_div {
  3360. compatible = "rockchip,rk3188-div-con";
  3361. rockchip,bits = <0xc 0x2>;
  3362. clocks = <0x57>;
  3363. clock-output-names = "hclk_hevc";
  3364. rockchip,div-type = <0x0>;
  3365. #clock-cells = <0x0>;
  3366. #clock-init-cells = <0x1>;
  3367. linux,phandle = <0xb1>;
  3368. phandle = <0xb1>;
  3369. };
  3370. };
  3371.  
  3372. sel-con@0104 {
  3373. compatible = "rockchip,rk3188-selcon";
  3374. reg = <0x104 0x4>;
  3375. #address-cells = <0x1>;
  3376. #size-cells = <0x1>;
  3377.  
  3378. spdif_8ch_frac {
  3379. compatible = "rockchip,rk3188-frac-con";
  3380. clocks = <0x58>;
  3381. clock-output-names = "spdif_8ch_frac";
  3382. rockchip,bits = <0x0 0x20>;
  3383. rockchip,clkops-idx = <0x5>;
  3384. #clock-cells = <0x0>;
  3385. linux,phandle = <0x59>;
  3386. phandle = <0x59>;
  3387. };
  3388. };
  3389.  
  3390. sel-con@0108 {
  3391. compatible = "rockchip,rk3188-selcon";
  3392. reg = <0x108 0x4>;
  3393. #address-cells = <0x1>;
  3394. #size-cells = <0x1>;
  3395.  
  3396. clk_hevc_cabac_div {
  3397. compatible = "rockchip,rk3188-div-con";
  3398. rockchip,bits = <0x0 0x5>;
  3399. clocks = <0x5a>;
  3400. clock-output-names = "clk_hevc_cabac";
  3401. rockchip,div-type = <0x0>;
  3402. #clock-cells = <0x0>;
  3403. rockchip,clkops-idx = <0x1>;
  3404. rockchip,flags = <0x100>;
  3405. };
  3406.  
  3407. clk_hevc_cabac_mux {
  3408. compatible = "rockchip,rk3188-mux-con";
  3409. rockchip,bits = <0x6 0x2>;
  3410. clocks = <0x15 0x16 0x25>;
  3411. clock-output-names = "clk_hevc_cabac";
  3412. #clock-cells = <0x0>;
  3413. #clock-init-cells = <0x1>;
  3414. linux,phandle = <0x5a>;
  3415. phandle = <0x5a>;
  3416. };
  3417.  
  3418. clk_hevc_core_div {
  3419. compatible = "rockchip,rk3188-div-con";
  3420. rockchip,bits = <0x8 0x5>;
  3421. clocks = <0x5b>;
  3422. clock-output-names = "clk_hevc_core";
  3423. rockchip,div-type = <0x0>;
  3424. #clock-cells = <0x0>;
  3425. rockchip,clkops-idx = <0x1>;
  3426. rockchip,flags = <0x100>;
  3427. };
  3428.  
  3429. clk_hevc_core_mux {
  3430. compatible = "rockchip,rk3188-mux-con";
  3431. rockchip,bits = <0xe 0x2>;
  3432. clocks = <0x15 0x16 0x25>;
  3433. clock-output-names = "clk_hevc_core";
  3434. #clock-cells = <0x0>;
  3435. #clock-init-cells = <0x1>;
  3436. linux,phandle = <0x5b>;
  3437. phandle = <0x5b>;
  3438. };
  3439. };
  3440. };
  3441.  
  3442. clk_gate_cons {
  3443. compatible = "rockchip,rk-gate-cons";
  3444. #address-cells = <0x1>;
  3445. #size-cells = <0x1>;
  3446. ranges;
  3447.  
  3448. gate-clk@0160 {
  3449. compatible = "rockchip,rk3188-gate-clk";
  3450. reg = <0x160 0x4>;
  3451. clocks = <0x18 0x10 0x16 0x14 0x5c 0x5d 0x18 0x14 0x40 0x16 0x16 0x43 0x8 0x18 0x18 0x18>;
  3452. clock-output-names = "reserved", "reserved", "clk_arm_gpll", "g_aclk_bus", "hclk_bus", "pclk_bus", "reserved", "aclk_bus_2pmu", "reserved", "reserved", "reserved", "reserved", "clk_acc_efuse", "reserved", "reserved", "reserved";
  3453. rockchip,suspend-clkgating-setting = <0xfff 0xfff>;
  3454. #clock-cells = <0x1>;
  3455. linux,phandle = <0x11>;
  3456. phandle = <0x11>;
  3457. };
  3458.  
  3459. gate-clk@0164 {
  3460. compatible = "rockchip,rk3188-gate-clk";
  3461. reg = <0x164 0x4>;
  3462. clocks = <0x8 0x8 0x8 0x8 0x8 0x8 0x18 0x18 0x2c 0x2d 0x32 0x33 0x34 0x35 0x36 0x37>;
  3463. clock-output-names = "clk_timer0", "clk_timer1", "clk_timer2", "clk_timer3", "clk_timer4", "clk_timer5", "reserved", "reserved", "clk_uart0_pll", "uart0_frac", "clk_uart1_div", "uart1_frac", "clk_uart2_div", "uart2_frac", "clk_uart3_div", "uart3_frac";
  3464. rockchip,suspend-clkgating-setting = <0x0 0x0>;
  3465. #clock-cells = <0x1>;
  3466. linux,phandle = <0xb3>;
  3467. phandle = <0xb3>;
  3468. };
  3469.  
  3470. gate-clk@0168 {
  3471. compatible = "rockchip,rk3188-gate-clk";
  3472. reg = <0x168 0x4>;
  3473. clocks = <0x27 0x27 0x5e 0x5f 0x18 0x38 0x3a 0x60 0x61 0x3d 0x3e 0x56 0x1a 0x1b 0x18 0x18>;
  3474. clock-output-names = "aclk_peri", "reserved", "hclk_peri", "pclk_peri", "reserved", "clk_mac_pll", "clk_hsadc_pll", "clk_tsadc", "clk_saradc", "clk_spi0", "clk_spi1", "clk_spi2", "clk_uart4_div", "uart4_frac", "reserved", "reserved";
  3475. rockchip,suspend-clkgating-setting = <0xf 0xf>;
  3476. #clock-cells = <0x1>;
  3477. linux,phandle = <0xb6>;
  3478. phandle = <0xb6>;
  3479. };
  3480.  
  3481. gate-clk@016c {
  3482. compatible = "rockchip,rk3188-gate-clk";
  3483. reg = <0x16c 0x4>;
  3484. clocks = <0x46 0x44 0x4e 0x4b 0x4d 0x4c 0x29 0x42 0x18 0xc 0x18 0xd 0x62 0x45 0x24 0x26>;
  3485. clock-output-names = "aclk_vio0", "dclk_lcdc0", "aclk_vio1", "dclk_lcdc1", "clk_rga", "aclk_rga", "hsicphy_480m", "clk_cif_pll", "reserved", "clk_vepu", "reserved", "clk_vdpu", "clk_edp_24m", "clk_edp", "clk_isp", "clk_isp_jpe";
  3486. rockchip,suspend-clkgating-setting = <0x0 0x0>;
  3487. #clock-cells = <0x1>;
  3488. };
  3489.  
  3490. gate-clk@0170 {
  3491. compatible = "rockchip,rk3188-gate-clk";
  3492. reg = <0x170 0x4>;
  3493. clocks = <0x63 0x1c 0x1d 0x20 0x22 0x23 0x64 0x58 0x59 0x65 0x51 0x52 0x3f 0x3f 0x66 0x18>;
  3494. clock-output-names = "clk_i2s_out", "clk_i2s_pll", "i2s_frac", "clk_i2s", "spdif_div", "spdif_frac", "clk_spdif", "spdif_8ch_div", "spdif_8ch_frac", "clk_spdif_8ch", "clk_tsp", "clk_tspout", "reserved", "reserved", "clk_jtag", "reserved";
  3495. rockchip,suspend-clkgating-setting = <0xf000 0xf000>;
  3496. #clock-cells = <0x1>;
  3497. };
  3498.  
  3499. gate-clk@0174 {
  3500. compatible = "rockchip,rk3188-gate-clk";
  3501. reg = <0x174 0x4>;
  3502. clocks = <0x67 0x67 0x67 0x67 0x68 0x54 0x55 0x4f 0x69 0x8 0x8 0x17 0x8 0x8 0x31 0x8>;
  3503. clock-output-names = "g_clk_mac_rx", "g_clk_mac_tx", "g_clk_mac_ref", "g_mac_refout", "clk_crypto", "clk_nandc0", "clk_nandc1", "clk_gpu", "pclk_pd_pmu", "g_clk_pvtm_core", "g_clk_pvtm_gpu", "g_hdmi_cec_clk", "g_hdmi_hdcp_clk", "g_ps2c_clk", "usbphy_480m", "g_mipidsi_24m";
  3504. rockchip,suspend-clkgating-setting = <0x100 0x100>;
  3505. #clock-cells = <0x1>;
  3506. linux,phandle = <0x79>;
  3507. phandle = <0x79>;
  3508. };
  3509.  
  3510. gate-clk@0178 {
  3511. compatible = "rockchip,rk3188-gate-clk";
  3512. reg = <0x178 0x4>;
  3513. clocks = <0x5e 0x5f 0x27 0x27 0x5f 0x5f 0x5f 0x5f 0x5f 0x5f 0x18 0x5f 0x5f 0x5f 0x5f 0x5f>;
  3514. clock-output-names = "g_hp_matrix", "g_pp_axi_matrix", "g_ap_axi_matrix", "g_aclk_dmac2", "g_pclk_spi0", "g_pclk_spi1", "g_pclk_spi2", "g_pclk_ps2c", "g_pclk_uart0", "g_pclk_uart1", "reserved", "g_pclk_uart3", "g_pclk_uart4", "g_pclk_i2c2", "g_pclk_i2c3", "g_pclk_i2c4";
  3515. rockchip,suspend-clkgating-setting = <0x3 0x3>;
  3516. #clock-cells = <0x1>;
  3517. linux,phandle = <0x90>;
  3518. phandle = <0x90>;
  3519. };
  3520.  
  3521. gate-clk@017c {
  3522. compatible = "rockchip,rk3188-gate-clk";
  3523. reg = <0x17c 0x4>;
  3524. clocks = <0x5f 0x5f 0x5f 0x5f 0x5e 0x5e 0x5e 0x5e 0x5e 0x5e 0x5e 0x27 0x5e 0x5e 0x5e 0x5e>;
  3525. clock-output-names = "g_pclk_i2c5", "g_pclk_saradc", "g_pclk_tsadc", "g_pclk_sim", "g_hclk_otg0", "g_pmu_hclk_otg0", "g_hclk_host0", "g_hclk_host1", "g_hclk_hsic", "g_hclk_usb_peri", "g_hp_ahb_arbi", "g_aclk_peri_niu", "g_h_emem_peri", "g_hclk_mem_peri", "g_hclk_nandc0", "g_hclk_nandc1";
  3526. rockchip,suspend-clkgating-setting = <0xc00 0xc000>;
  3527. #clock-cells = <0x1>;
  3528. linux,phandle = <0x7a>;
  3529. phandle = <0x7a>;
  3530. };
  3531.  
  3532. gate-clk@0180 {
  3533. compatible = "rockchip,rk3188-gate-clk";
  3534. reg = <0x180 0x4>;
  3535. clocks = <0x27 0x5f 0x27 0x5e 0x5e 0x5e 0x5e 0x5e 0x5e 0x6a 0x6b 0x53 0x27 0x18 0x18 0x18>;
  3536. clock-output-names = "g_aclk_gmac", "g_pclk_gmac", "g_hclk_gps", "g_hclk_sdmmc", "g_hclk_sdio0", "g_hclk_sdio1", "g_hclk_emmc", "g_hclk_hsadc", "g_hclk_tsp", "g_hsadc_0_tsp", "g_hsadc_1_tsp", "g_clk_27m_tsp", "g_aclk_peri_mmu", "reserved", "reserved", "reserved";
  3537. rockchip,suspend-clkgating-setting = <0x0 0x0>;
  3538. #clock-cells = <0x1>;
  3539. linux,phandle = <0x7b>;
  3540. phandle = <0x7b>;
  3541. };
  3542.  
  3543. gate-clk@0184 {
  3544. compatible = "rockchip,rk3188-gate-clk";
  3545. reg = <0x184 0x4>;
  3546. clocks = <0x18 0x18 0x18 0x18 0x18 0x18 0x18 0x18 0x18 0x18 0x18 0x18 0x18 0x18 0x18 0x18>;
  3547. clock-output-names = "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved";
  3548. rockchip,suspend-clkgating-setting = <0x0 0x0>;
  3549. #clock-cells = <0x1>;
  3550. };
  3551.  
  3552. gate-clk@0188 {
  3553. compatible = "rockchip,rk3188-gate-clk";
  3554. reg = <0x188 0x4>;
  3555. clocks = <0x5d 0x5d 0x5d 0x5d 0x14 0x14 0x14 0x14 0x5c 0x5c 0x5c 0x5c 0x14 0x14 0x5d 0x5d>;
  3556. clock-output-names = "g_pclk_pwm", "g_pclk_timer", "g_pclk_i2c0", "g_pclk_i2c1", "g_aclk_intmem", "g_clk_intmem0", "g_clk_intmem1", "g_clk_intmem2", "g_hclk_i2s", "g_hclk_rom", "g_hclk_spdif", "g_h_spdif_8ch", "g_aclk_dmac1", "g_aclk_strc_sys", "reserved", "reserved";
  3557. rockchip,suspend-clkgating-setting = <0xf2f1 0xf2f1>;
  3558. #clock-cells = <0x1>;
  3559. linux,phandle = <0xb4>;
  3560. phandle = <0xb4>;
  3561. };
  3562.  
  3563. gate-clk@018c {
  3564. compatible = "rockchip,rk3188-gate-clk";
  3565. reg = <0x18c 0x4>;
  3566. clocks = <0x5d 0x5d 0x5d 0x5d 0x18 0x18 0x14 0x5c 0x14 0x5d 0x5d 0x5d 0x18 0x18 0x18 0x18>;
  3567. clock-output-names = "reserved", "reserved", "g_p_efuse_1024", "g_pclk_tzpc", "reserved", "reserved", "g_aclk_crypto", "g_hclk_crypto", "g_aclk_ccp", "g_pclk_uart2", "g_p_efuse_256", "g_pclk_rkpwm", "reserved", "reserved", "reserved", "reserved";
  3568. rockchip,suspend-clkgating-setting = <0x833 0x833>;
  3569. #clock-cells = <0x1>;
  3570. linux,phandle = <0xa6>;
  3571. phandle = <0xa6>;
  3572. };
  3573.  
  3574. gate-clk@0190 {
  3575. compatible = "rockchip,rk3188-gate-clk";
  3576. reg = <0x190 0x4>;
  3577. clocks = <0x6c 0x6d 0x6e 0x6f 0x70 0x71 0x72 0x73 0x74 0x74 0x74 0x74 0x18 0x18 0x18 0x18>;
  3578. clock-output-names = "clk_core0", "clk_core1", "clk_core2", "clk_core3", "clk_l2ram", "aclk_core_m0", "aclk_core_mp", "atclk_core", "pclk_dbg_src", "g_dbg_core_clk", "g_cs_dbg_clk", "g_pclk_core_niu", "reserved", "reserved", "reserved", "reserved";
  3579. rockchip,suspend-clkgating-setting = <0xff1 0xff1>;
  3580. #clock-cells = <0x1>;
  3581. linux,phandle = <0xb2>;
  3582. phandle = <0xb2>;
  3583. };
  3584.  
  3585. gate-clk@0194 {
  3586. compatible = "rockchip,rk3188-gate-clk";
  3587. reg = <0x194 0x4>;
  3588. clocks = <0x28 0x2a 0x50 0x2b 0x8 0x8 0x8 0x17 0x13 0x1f 0x8 0x8 0x18 0x57 0x5a 0x5b>;
  3589. clock-output-names = "clk_sdmmc", "clk_sdio0", "clk_sdio1", "clk_emmc", "clk_otgphy0", "clk_otgphy1", "clk_otgphy2", "clk_otg_adp", "g_clk_c2c_host", "g_clk_hsic_12m", "g_clk_lcdc_pwm0", "g_clk_lcdc_pwm1", "g_clk_wifi", "aclk_hevc", "clk_hevc_cabac", "clk_hevc_core";
  3590. rockchip,suspend-clkgating-setting = <0x0 0x0>;
  3591. #clock-cells = <0x1>;
  3592. linux,phandle = <0x9>;
  3593. phandle = <0x9>;
  3594. };
  3595.  
  3596. gate-clk@0198 {
  3597. compatible = "rockchip,rk3188-gate-clk";
  3598. reg = <0x198 0x4>;
  3599. clocks = <0x18 0x75 0x75 0x75 0x75 0x75 0x75 0x75 0x75 0x18 0x18 0x75 0x75 0x18 0x18 0x18>;
  3600. clock-output-names = "reserved", "g_pclk_gpio1", "g_pclk_gpio2", "g_pclk_gpio3", "g_pclk_gpio4", "g_pclk_gpio5", "g_pclk_gpio6", "g_pclk_gpio7", "g_pclk_gpio8", "reserved", "reserved", "g_pclk_grf", "g_p_alive_niu", "reserved", "reserved", "reserved";
  3601. rockchip,suspend-clkgating-setting = <0x19fe 0x19fe>;
  3602. #clock-cells = <0x1>;
  3603. linux,phandle = <0x7>;
  3604. phandle = <0x7>;
  3605. };
  3606.  
  3607. gate-clk@019c {
  3608. compatible = "rockchip,rk3188-gate-clk";
  3609. reg = <0x19c 0x4>;
  3610. clocks = <0x4c 0x76 0x46 0x76 0x18 0x46 0x76 0x4e 0x76 0x76 0x76 0x46 0x4e 0x4c 0x46 0x76>;
  3611. clock-output-names = "reserved", "g_hclk_rga", "g_aclk_iep", "g_hclk_iep", "g_aclk_lcdc_iep", "g_aclk_lcdc0", "g_hclk_lcdc0", "g_aclk_lcdc1", "g_hclk_lcdc1", "g_h_vio_ahb", "g_hclk_vio_niu", "g_aclk_vio0_niu", "g_aclk_vio1_niu", "reserved", "g_aclk_vip", "g_hclk_vip";
  3612. rockchip,suspend-clkgating-setting = <0x0 0x0>;
  3613. #clock-cells = <0x1>;
  3614. linux,phandle = <0xb5>;
  3615. phandle = <0xb5>;
  3616. };
  3617.  
  3618. gate-clk@01a0 {
  3619. compatible = "rockchip,rk3188-gate-clk";
  3620. reg = <0x1a0 0x4>;
  3621. clocks = <0x77 0x76 0x4e 0x78 0x76 0x76 0x76 0x76 0x76 0x76 0x76 0x76 0x18 0x18 0x18 0x18>;
  3622. clock-output-names = "g_pclkin_cif", "g_hclk_isp", "g_aclk_isp", "g_pclkin_isp", "g_p_mipi_dsi0", "g_p_mipi_dsi1", "g_p_mipi_csi", "g_pclk_lvds_phy", "g_pclk_edp_ctrl", "g_p_hdmi_ctrl", "g_hclk_vio2_h2p", "g_pclk_vio2_h2p", "reserved", "reserved", "reserved", "reserved";
  3623. rockchip,suspend-clkgating-setting = <0x0 0x0>;
  3624. #clock-cells = <0x1>;
  3625. linux,phandle = <0xb>;
  3626. phandle = <0xb>;
  3627. };
  3628.  
  3629. gate-clk@01a4 {
  3630. compatible = "rockchip,rk3188-gate-clk";
  3631. reg = <0x1a4 0x4>;
  3632. clocks = <0x69 0x69 0x69 0x69 0x69 0x18 0x18 0x18 0x18 0x18 0x18 0x18 0x18 0x18 0x18 0x18>;
  3633. clock-output-names = "g_pclk_pmu", "g_pclk_intmem1", "g_pclk_pmu_niu", "g_pclk_sgrf", "g_pclk_gpio0", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved";
  3634. rockchip,suspend-clkgating-setting = <0x1f 0x1f>;
  3635. #clock-cells = <0x1>;
  3636. linux,phandle = <0x6>;
  3637. phandle = <0x6>;
  3638. };
  3639.  
  3640. gate-clk@01a8 {
  3641. compatible = "rockchip,rk3188-gate-clk";
  3642. reg = <0x1a8 0x4>;
  3643. clocks = <0x4f 0x18 0x18 0x18 0x18 0x18 0x18 0x18 0x18 0x18 0x18 0x18 0x18 0x18 0x18 0x18>;
  3644. clock-output-names = "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved";
  3645. rockchip,suspend-clkgating-setting = <0x0 0x0>;
  3646. #clock-cells = <0x1>;
  3647. };
  3648. };
  3649. };
  3650. };
  3651.  
  3652. cpus {
  3653. #address-cells = <0x1>;
  3654. #size-cells = <0x0>;
  3655.  
  3656. cpu@0 {
  3657. device_type = "cpu";
  3658. compatible = "arm,cortex-a15";
  3659. reg = <0x500>;
  3660. };
  3661.  
  3662. cpu@1 {
  3663. device_type = "cpu";
  3664. compatible = "arm,cortex-a15";
  3665. reg = <0x501>;
  3666. };
  3667.  
  3668. cpu@2 {
  3669. device_type = "cpu";
  3670. compatible = "arm,cortex-a15";
  3671. reg = <0x502>;
  3672. };
  3673.  
  3674. cpu@3 {
  3675. device_type = "cpu";
  3676. compatible = "arm,cortex-a15";
  3677. reg = <0x503>;
  3678. };
  3679. };
  3680.  
  3681. interrupt-controller@ffc01000 {
  3682. compatible = "arm,cortex-a15-gic";
  3683. interrupt-controller;
  3684. #interrupt-cells = <0x3>;
  3685. #address-cells = <0x0>;
  3686. reg = <0xffc01000 0x1000 0xffc02000 0x1000>;
  3687. linux,phandle = <0x2>;
  3688. phandle = <0x2>;
  3689. };
  3690.  
  3691. arm-pmu {
  3692. compatible = "arm,cortex-a12-pmu";
  3693. interrupts = <0x0 0x97 0x4 0x0 0x98 0x4 0x0 0x99 0x4 0x0 0x9a 0x4>;
  3694. };
  3695.  
  3696. cpu_axi_bus {
  3697. compatible = "rockchip,cpu_axi_bus";
  3698. #address-cells = <0x1>;
  3699. #size-cells = <0x1>;
  3700. ranges;
  3701.  
  3702. qos {
  3703. #address-cells = <0x1>;
  3704. #size-cells = <0x1>;
  3705. ranges;
  3706.  
  3707. cpup {
  3708. reg = <0xffa80000 0x20>;
  3709. };
  3710.  
  3711. cpum_r {
  3712. reg = <0xffa80080 0x20>;
  3713. };
  3714.  
  3715. cpum_w {
  3716. reg = <0xffa80100 0x20>;
  3717. };
  3718.  
  3719. bus_dmac {
  3720. reg = <0xffa90000 0x20>;
  3721. };
  3722.  
  3723. host {
  3724. reg = <0xffa90080 0x20>;
  3725. };
  3726.  
  3727. crypto {
  3728. reg = <0xffa90100 0x20>;
  3729. };
  3730.  
  3731. ccp {
  3732. reg = <0xffa90180 0x20>;
  3733. };
  3734.  
  3735. ccs {
  3736. reg = <0xffa90200 0x20>;
  3737. };
  3738.  
  3739. gpu_r {
  3740. reg = <0xffaa0000 0x20>;
  3741. };
  3742.  
  3743. gpu_w {
  3744. reg = <0xffaa0080 0x20>;
  3745. };
  3746.  
  3747. peri {
  3748. reg = <0xffab0000 0x20>;
  3749. };
  3750.  
  3751. vio1_vop {
  3752. reg = <0xffad0000 0x20>;
  3753. rockchip,priority = <0x2 0x2>;
  3754. };
  3755.  
  3756. vio1_isp_w0 {
  3757. reg = <0xffad0100 0x20>;
  3758. rockchip,priority = <0x2 0x2>;
  3759. };
  3760.  
  3761. vio1_isp_w1 {
  3762. reg = <0xffad0180 0x20>;
  3763. };
  3764.  
  3765. vio0_vop {
  3766. reg = <0xffad0400 0x20>;
  3767. rockchip,priority = <0x2 0x2>;
  3768. };
  3769.  
  3770. vio0_vip {
  3771. reg = <0xffad0480 0x20>;
  3772. };
  3773.  
  3774. vio0_iep {
  3775. reg = <0xffad0500 0x20>;
  3776. };
  3777.  
  3778. vio2_rga_r {
  3779. reg = <0xffad0800 0x20>;
  3780. };
  3781.  
  3782. vio2_rga_w {
  3783. reg = <0xffad0880 0x20>;
  3784. };
  3785.  
  3786. vio1_isp_r {
  3787. reg = <0xffad0900 0x20>;
  3788. };
  3789.  
  3790. video {
  3791. reg = <0xffae0000 0x20>;
  3792. };
  3793.  
  3794. hevc_r {
  3795. reg = <0xffaf0000 0x20>;
  3796. };
  3797.  
  3798. hevc_w {
  3799. reg = <0xffaf0080 0x20>;
  3800. };
  3801. };
  3802.  
  3803. msch {
  3804. #address-cells = <0x1>;
  3805. #size-cells = <0x1>;
  3806. ranges;
  3807.  
  3808. msch@0 {
  3809. reg = <0xffac0000 0x40>;
  3810. rockchip,read-latency = <0x34>;
  3811. };
  3812.  
  3813. msch@1 {
  3814. reg = <0xffac0080 0x40>;
  3815. rockchip,read-latency = <0x34>;
  3816. };
  3817. };
  3818. };
  3819.  
  3820. sram@ff710000 {
  3821. compatible = "mmio-sram";
  3822. reg = <0xff710000 0x8000>;
  3823. map-exec;
  3824. linux,phandle = <0x1>;
  3825. phandle = <0x1>;
  3826. };
  3827.  
  3828. timer {
  3829. compatible = "arm,armv7-timer";
  3830. interrupts = <0x1 0xd 0xf04 0x1 0xe 0xf04>;
  3831. clock-frequency = <0x16e3600>;
  3832. };
  3833.  
  3834. timer@ff810000 {
  3835. compatible = "rockchip,timer";
  3836. reg = <0xff810000 0x20>;
  3837. interrupts = <0x0 0x48 0x4>;
  3838. rockchip,broadcast = <0x1>;
  3839. };
  3840.  
  3841. wdt@2004c000 {
  3842. compatible = "rockchip,watch dog";
  3843. reg = <0xff800000 0x100>;
  3844. clocks = <0x75>;
  3845. clock-names = "pclk_wdt";
  3846. interrupts = <0x0 0x4f 0x4>;
  3847. rockchip,irq = <0x0>;
  3848. rockchip,timeout = <0x2>;
  3849. rockchip,atboot = <0x1>;
  3850. rockchip,debug = <0x0>;
  3851. status = "disabled";
  3852. };
  3853.  
  3854. amba {
  3855. #address-cells = <0x1>;
  3856. #size-cells = <0x1>;
  3857. compatible = "arm,amba-bus";
  3858. interrupt-parent = <0x2>;
  3859. ranges;
  3860.  
  3861. pdma@ffb20000 {
  3862. compatible = "arm,pl330", "arm,primecell";
  3863. reg = <0xffb20000 0x4000>;
  3864. interrupts = <0x0 0x0 0x4 0x0 0x1 0x4>;
  3865. #dma-cells = <0x1>;
  3866. linux,phandle = <0xa7>;
  3867. phandle = <0xa7>;
  3868. };
  3869.  
  3870. pdma@ff250000 {
  3871. compatible = "arm,pl330", "arm,primecell";
  3872. reg = <0xff250000 0x4000>;
  3873. interrupts = <0x0 0x2 0x4 0x0 0x3 0x4>;
  3874. #dma-cells = <0x1>;
  3875. linux,phandle = <0x9d>;
  3876. phandle = <0x9d>;
  3877. };
  3878. };
  3879.  
  3880. reset@ff7601b8 {
  3881. compatible = "rockchip,reset";
  3882. reg = <0xff7601b8 0x30>;
  3883. rockchip,reset-flag = <0x1>;
  3884. #reset-cells = <0x1>;
  3885. linux,phandle = <0xe4>;
  3886. phandle = <0xe4>;
  3887. };
  3888.  
  3889. nandc@0xff400000 {
  3890. compatible = "rockchip,rk-nandc";
  3891. reg = <0xff400000 0x4000>;
  3892. interrupts = <0x0 0x26 0x4>;
  3893. nandc_id = <0x0>;
  3894. clocks = <0x54 0x79 0x5 0x7a 0xe>;
  3895. clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
  3896. status = "okay";
  3897. };
  3898.  
  3899. nandc@0xff410000 {
  3900. compatible = "rockchip,rk-nandc";
  3901. reg = <0xff410000 0x4000>;
  3902. interrupts = <0x0 0x28 0x4>;
  3903. nandc_id = <0x1>;
  3904. clocks = <0x55 0x79 0x6 0x7a 0xf>;
  3905. clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
  3906. status = "disabled";
  3907. };
  3908.  
  3909. nandc0@0xff400000 {
  3910. compatible = "rockchip,rk-nandc";
  3911. reg = <0xff400000 0x4000>;
  3912. status = "disabled";
  3913. };
  3914.  
  3915. rksdmmc@ff0f0000 {
  3916. compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
  3917. reg = <0xff0f0000 0x4000>;
  3918. interrupts = <0x0 0x23 0x4>;
  3919. #address-cells = <0x1>;
  3920. #size-cells = <0x0>;
  3921. clocks = <0x2b 0x7b 0x6>;
  3922. clock-names = "clk_mmc", "hclk_mmc";
  3923. num-slots = <0x1>;
  3924. fifo-depth = <0x100>;
  3925. bus-width = <0x8>;
  3926. clock-frequency = <0x5f5e100>;
  3927. clock-freq-min-max = <0x61a80 0x5f5e100>;
  3928. supports-highspeed;
  3929. supports-emmc;
  3930. bootpart-no-access;
  3931. supports-DDR_MODE;
  3932. caps2-mmc-hs200;
  3933. ignore-pm-notify;
  3934. keep-power-in-suspend;
  3935. status = "okay";
  3936. };
  3937.  
  3938. rksdmmc@ff0c0000 {
  3939. compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
  3940. reg = <0xff0c0000 0x4000>;
  3941. interrupts = <0x0 0x20 0x4>;
  3942. #address-cells = <0x1>;
  3943. #size-cells = <0x0>;
  3944. pinctrl-names = "default", "idle";
  3945. pinctrl-0 = <0x7c 0x7d 0x7e 0x7f>;
  3946. pinctrl-1 = <0x80>;
  3947. cd-gpios = <0x81 0x16 0x0>;
  3948. clocks = <0x28 0x7b 0x3>;
  3949. clock-names = "clk_mmc", "hclk_mmc";
  3950. num-slots = <0x1>;
  3951. fifo-depth = <0x100>;
  3952. bus-width = <0x4>;
  3953. clock-frequency = <0x2faf080>;
  3954. lock-freq-min-max = <0x61a80 0x2faf080>;
  3955. supports-highspeed;
  3956. supports-sd;
  3957. broken-cd;
  3958. card-detect-delay = <0xc8>;
  3959. ignore-pm-notify;
  3960. keep-power-in-suspend;
  3961. vmmc-supply = <0x82>;
  3962. status = "okay";
  3963. };
  3964.  
  3965. rksdmmc@ff0d0000 {
  3966. compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
  3967. reg = <0xff0d0000 0x4000>;
  3968. interrupts = <0x0 0x21 0x4>;
  3969. #address-cells = <0x1>;
  3970. #size-cells = <0x0>;
  3971. pinctrl-names = "default", "idle";
  3972. pinctrl-0 = <0x83 0x84 0x85 0x86 0x87 0x88 0x89>;
  3973. pinctrl-1 = <0x8a>;
  3974. clocks = <0x2a 0x7b 0x4>;
  3975. clock-names = "clk_mmc", "hclk_mmc";
  3976. num-slots = <0x1>;
  3977. fifo-depth = <0x100>;
  3978. bus-width = <0x4>;
  3979. clock-frequency = <0x2faf080>;
  3980. clock-freq-min-max = <0x30d40 0x2faf080>;
  3981. supports-highspeed;
  3982. supports-sdio;
  3983. ignore-pm-notify;
  3984. keep-power-in-suspend;
  3985. status = "okay";
  3986. };
  3987.  
  3988. rksdmmc@ff0e0000 {
  3989. compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
  3990. reg = <0xff0e0000 0x4000>;
  3991. interrupts = <0x0 0x22 0x4>;
  3992. #address-cells = <0x1>;
  3993. #size-cells = <0x0>;
  3994. clocks = <0x50 0x7b 0x5>;
  3995. clock-names = "clk_mmc", "hclk_mmc";
  3996. num-slots = <0x1>;
  3997. fifo-depth = <0x100>;
  3998. bus-width = <0x4>;
  3999. status = "disabled";
  4000. };
  4001.  
  4002. spi@ff110000 {
  4003. compatible = "rockchip,rockchip-spi";
  4004. reg = <0xff110000 0x1000>;
  4005. interrupts = <0x0 0x2c 0x4>;
  4006. #address-cells = <0x1>;
  4007. #size-cells = <0x0>;
  4008. pinctrl-names = "default";
  4009. pinctrl-0 = <0x8b 0x8c 0x8d 0x8e 0x8f>;
  4010. rockchip,spi-src-clk = <0x0>;
  4011. num-cs = <0x2>;
  4012. clocks = <0x3d 0x90 0x4>;
  4013. clock-names = "spi", "pclk_spi0";
  4014. status = "disabled";
  4015. max-freq = <0x2dc6c00>;
  4016. };
  4017.  
  4018. spi@ff120000 {
  4019. compatible = "rockchip,rockchip-spi";
  4020. reg = <0xff120000 0x1000>;
  4021. interrupts = <0x0 0x2d 0x4>;
  4022. #address-cells = <0x1>;
  4023. #size-cells = <0x0>;
  4024. pinctrl-names = "default";
  4025. pinctrl-0 = <0x91 0x92 0x93 0x94>;
  4026. rockchip,spi-src-clk = <0x1>;
  4027. num-cs = <0x1>;
  4028. clocks = <0x3e 0x90 0x5>;
  4029. clock-names = "spi", "pclk_spi1";
  4030. status = "disabled";
  4031. max-freq = <0x2dc6c00>;
  4032.  
  4033. tstv-ctrl@00 {
  4034. compatible = "rockchip,dtv_spi_ctrl";
  4035. gpio-powerup = <0x95 0x1f 0x0>;
  4036. gpio-powerdown = <0x96 0xe 0x0>;
  4037. gpio-reset = <0x96 0xf 0x0>;
  4038. gpio-nreset = <0x96 0xc 0x0>;
  4039. spi-max-frequency = <0xb71b00>;
  4040. reg = <0x0>;
  4041. poll_mode = <0x0>;
  4042. type = <0x0>;
  4043. enable_dma = <0x0>;
  4044. };
  4045. };
  4046.  
  4047. spi@ff130000 {
  4048. compatible = "rockchip,rockchip-spi";
  4049. reg = <0xff130000 0x1000>;
  4050. interrupts = <0x0 0x2e 0x4>;
  4051. #address-cells = <0x1>;
  4052. #size-cells = <0x0>;
  4053. pinctrl-names = "default";
  4054. pinctrl-0 = <0x97 0x98 0x99 0x9a 0x9b>;
  4055. rockchip,spi-src-clk = <0x2>;
  4056. num-cs = <0x2>;
  4057. clocks = <0x56 0x90 0x6>;
  4058. clock-names = "spi", "pclk_spi2";
  4059. status = "disabled";
  4060. max-freq = <0x2dc6c00>;
  4061. };
  4062.  
  4063. rockchip-hsadc@ff080000 {
  4064. compatible = "rockchip-hsadc";
  4065. reg = <0xff080000 0x4000>;
  4066. interrupts = <0x0 0x1f 0x4>;
  4067. #address-cells = <0x1>;
  4068. #size-cells = <0x0>;
  4069. pinctrl-names = "default";
  4070. pinctrl-0 = <0x9c>;
  4071. clocks = <0x7b 0x7 0xa 0x3b>;
  4072. clock-names = "hclk_hsadc", "clk_hsadc_out", "clk_hsadc_ext";
  4073. dmas = <0x9d 0x0>;
  4074. dma-names = "data";
  4075. status = "disabled";
  4076. };
  4077.  
  4078. serial@ff180000 {
  4079. compatible = "rockchip,serial";
  4080. reg = <0xff180000 0x100>;
  4081. interrupts = <0x0 0x37 0x4>;
  4082. clock-frequency = <0x16e3600>;
  4083. clocks = <0x9e 0x90 0x8>;
  4084. clock-names = "sclk_uart", "pclk_uart";
  4085. reg-shift = <0x2>;
  4086. reg-io-width = <0x4>;
  4087. dmas = <0x9d 0x1 0x9d 0x2>;
  4088. #dma-cells = <0x2>;
  4089. pinctrl-names = "default";
  4090. pinctrl-0 = <0x9f 0xa0>;
  4091. status = "okay";
  4092. dma-names = "!tx", "!rx";
  4093. };
  4094.  
  4095. serial@ff190000 {
  4096. compatible = "rockchip,serial";
  4097. reg = <0xff190000 0x100>;
  4098. interrupts = <0x0 0x38 0x4>;
  4099. clock-frequency = <0x16e3600>;
  4100. clocks = <0xa1 0x90 0x9>;
  4101. clock-names = "sclk_uart", "pclk_uart";
  4102. reg-shift = <0x2>;
  4103. reg-io-width = <0x4>;
  4104. dmas = <0x9d 0x3 0x9d 0x4>;
  4105. #dma-cells = <0x2>;
  4106. pinctrl-names = "default";
  4107. pinctrl-0 = <0xa2 0xa3 0xa4>;
  4108. status = "disabled";
  4109. };
  4110.  
  4111. serial@ff690000 {
  4112. compatible = "rockchip,serial";
  4113. reg = <0xff690000 0x100>;
  4114. interrupts = <0x0 0x39 0x4>;
  4115. clock-frequency = <0x16e3600>;
  4116. clocks = <0xa5 0xa6 0x9>;
  4117. clock-names = "sclk_uart", "pclk_uart";
  4118. reg-shift = <0x2>;
  4119. reg-io-width = <0x4>;
  4120. dmas = <0xa7 0x4 0xa7 0x5>;
  4121. #dma-cells = <0x2>;
  4122. pinctrl-names = "default";
  4123. pinctrl-0 = <0xa8>;
  4124. status = "disabled";
  4125. };
  4126.  
  4127. serial@ff1b0000 {
  4128. compatible = "rockchip,serial";
  4129. reg = <0xff1b0000 0x100>;
  4130. interrupts = <0x0 0x3a 0x4>;
  4131. clock-frequency = <0x16e3600>;
  4132. clocks = <0xa9 0x90 0xb>;
  4133. clock-names = "sclk_uart", "pclk_uart";
  4134. current-speed = <0x1c200>;
  4135. reg-shift = <0x2>;
  4136. reg-io-width = <0x4>;
  4137. dmas = <0x9d 0x7 0x9d 0x8>;
  4138. #dma-cells = <0x2>;
  4139. pinctrl-names = "default";
  4140. pinctrl-0 = <0xaa 0xab 0xac>;
  4141. status = "disabled";
  4142. };
  4143.  
  4144. serial@ff1c0000 {
  4145. compatible = "rockchip,serial";
  4146. reg = <0xff1c0000 0x100>;
  4147. interrupts = <0x0 0x3b 0x4>;
  4148. clock-frequency = <0x16e3600>;
  4149. clocks = <0xad 0x90 0xc>;
  4150. clock-names = "sclk_uart", "pclk_uart";
  4151. reg-shift = <0x2>;
  4152. reg-io-width = <0x4>;
  4153. dmas = <0x9d 0x9 0x9d 0xa>;
  4154. #dma-cells = <0x2>;
  4155. pinctrl-names = "default";
  4156. pinctrl-0 = <0xae 0xaf 0xb0>;
  4157. status = "disabled";
  4158. };
  4159.  
  4160. fiq-debugger {
  4161. compatible = "rockchip,fiq-debugger";
  4162. rockchip,serial-id = <0x2>;
  4163. rockchip,signal-irq = <0x6a>;
  4164. rockchip,wake-irq = <0x0>;
  4165. status = "okay";
  4166. };
  4167.  
  4168. clocks-init {
  4169. compatible = "rockchip,clocks-init";
  4170. rockchip,clocks-init-parent = <0xf 0x10 0x13 0x16 0x27 0x16 0x19 0x16 0x1c 0x16 0x21 0x16 0x31 0x2f>;
  4171. rockchip,clocks-init-rate = <0xf 0xcdfe600 0x16 0x23c34600 0x43 0x1c52fa0 0x25 0x4a817c80 0x13 0x11e1a300 0x14 0x11e1a300 0x5c 0x8f0d180 0x5d 0x47868c0 0x68 0x8f0d180 0x27 0x11e1a300 0x5e 0x8f0d180 0x5f 0x47868c0 0x4f 0xbebc200 0x46 0x11e1a300 0x4e 0x11e1a300 0x76 0x47868c0 0x75 0x5f5e100 0x69 0x5f5e100 0x57 0x17d78400 0xb1 0xbebc200 0x5a 0x11e1a300 0x5b 0x11e1a300 0x4c 0x11e1a300 0x4d 0x11e1a300 0xc 0x11e1a300 0xd 0x11e1a300 0x45 0xbebc200 0x24 0xbebc200 0x26 0x17d78400 0x51 0x4c4b400 0x52 0x4c4b400 0x67 0x7735940>;
  4172. };
  4173.  
  4174. clocks-enable {
  4175. compatible = "rockchip,clocks-enable";
  4176. clocks = <0x11 0x2 0x6c 0x6d 0x6e 0x6f 0x70 0x71 0x72 0x73 0x74 0xb2 0x9 0xb2 0xa 0xb2 0xb 0x14 0x11 0x3 0x5c 0x5d 0x9 0x8 0x68 0x11 0x7 0xb3 0x0 0xb3 0x1 0xb3 0x2 0xb3 0x3 0xb3 0x4 0xb3 0x5 0x75 0x69 0x27 0x5e 0x5f 0xb4 0x5 0xb4 0x6 0xb4 0x7 0xb4 0xc 0xb4 0xd 0xb4 0x4 0xa6 0x6 0xa6 0x8 0xa6 0x7 0xb4 0x9 0xb4 0x1 0xb4 0x9 0xb4 0xd 0xb2 0x8 0x90 0x2 0x90 0x3 0x7a 0xb 0x7b 0xc 0x90 0x0 0x7a 0xa 0x7a 0xc 0x7a 0xd 0x90 0x1 0x7 0xb 0x7 0xc 0x6 0x0 0x6 0x1 0x6 0x2 0x6 0x3 0xb5 0x9 0xb5 0xa 0xb 0xa 0xb 0xb 0xb5 0xb 0xb5 0xc 0xa6 0x9 0xb6 0x6 0x7b 0x7 0x31>;
  4177. };
  4178.  
  4179. i2c@ff650000 {
  4180. compatible = "rockchip,rk30-i2c";
  4181. reg = <0xff650000 0x1000>;
  4182. interrupts = <0x0 0x3c 0x4>;
  4183. #address-cells = <0x1>;
  4184. #size-cells = <0x0>;
  4185. pinctrl-names = "default", "gpio";
  4186. pinctrl-0 = <0xb7 0xb8>;
  4187. pinctrl-1 = <0xb9>;
  4188. gpios = <0x95 0xf 0x1 0x95 0x10 0x1>;
  4189. clocks = <0xb4 0x2>;
  4190. rockchip,check-idle = <0x1>;
  4191. status = "okay";
  4192.  
  4193. rk808@1b {
  4194. reg = <0x1b>;
  4195. status = "okay";
  4196. compatible = "rockchip,rk808";
  4197. gpios = <0x95 0x4 0x0 0x95 0xb 0x1>;
  4198. rk808,system-power-controller;
  4199.  
  4200. regulators {
  4201. #address-cells = <0x1>;
  4202. #size-cells = <0x0>;
  4203.  
  4204. regulator@0 {
  4205. reg = <0x0>;
  4206. regulator-compatible = "rk_dcdc1";
  4207. regulator-min-microvolt = <0xaae60>;
  4208. regulator-max-microvolt = <0x16e360>;
  4209. regulator-initial-mode = <0x2>;
  4210. regulator-initial-state = <0x3>;
  4211. regulator-name = "vdd_arm";
  4212. regulator-always-on;
  4213. regulator-boot-on;
  4214.  
  4215. regulator-state-mem {
  4216. regulator-state-mode = <0x2>;
  4217. regulator-state-disabled;
  4218. regulator-state-uv = <0xdbba0>;
  4219. };
  4220. };
  4221.  
  4222. regulator@1 {
  4223. reg = <0x1>;
  4224. regulator-compatible = "rk_dcdc2";
  4225. regulator-min-microvolt = <0xaae60>;
  4226. regulator-max-microvolt = <0x16e360>;
  4227. regulator-initial-mode = <0x2>;
  4228. regulator-initial-state = <0x3>;
  4229. regulator-name = "vdd_gpu";
  4230. regulator-always-on;
  4231. regulator-boot-on;
  4232.  
  4233. regulator-state-mem {
  4234. regulator-state-mode = <0x2>;
  4235. regulator-state-disabled;
  4236. regulator-state-uv = <0xdbba0>;
  4237. };
  4238. };
  4239.  
  4240. regulator@2 {
  4241. reg = <0x2>;
  4242. regulator-compatible = "rk_dcdc3";
  4243. regulator-initial-mode = <0x2>;
  4244. regulator-initial-state = <0x3>;
  4245. regulator-name = "rk_dcdc3";
  4246. regulator-min-microvolt = <0x124f80>;
  4247. regulator-max-microvolt = <0x124f80>;
  4248. regulator-always-on;
  4249. regulator-boot-on;
  4250.  
  4251. regulator-state-mem {
  4252. regulator-state-mode = <0x2>;
  4253. regulator-state-enabled;
  4254. regulator-state-uv = <0x124f80>;
  4255. };
  4256. };
  4257.  
  4258. regulator@3 {
  4259. reg = <0x3>;
  4260. regulator-compatible = "rk_dcdc4";
  4261. regulator-initial-mode = <0x2>;
  4262. regulator-initial-state = <0x3>;
  4263. regulator-name = "vccio";
  4264. regulator-min-microvolt = <0x1b7740>;
  4265. regulator-max-microvolt = <0x325aa0>;
  4266. regulator-always-on;
  4267. regulator-boot-on;
  4268.  
  4269. regulator-state-mem {
  4270. regulator-state-mode = <0x2>;
  4271. regulator-state-enabled;
  4272. regulator-state-uv = <0x2ab980>;
  4273. };
  4274. };
  4275.  
  4276. regulator@4 {
  4277. reg = <0x4>;
  4278. regulator-compatible = "rk_ldo1";
  4279. regulator-initial-state = <0x3>;
  4280. regulator-name = "rk_ldo1";
  4281. regulator-min-microvolt = <0x325aa0>;
  4282. regulator-max-microvolt = <0x325aa0>;
  4283. regulator-always-on;
  4284. regulator-boot-on;
  4285.  
  4286. regulator-state-mem {
  4287. regulator-state-enabled;
  4288. regulator-state-uv = <0x325aa0>;
  4289. };
  4290. };
  4291.  
  4292. regulator@5 {
  4293. reg = <0x5>;
  4294. regulator-compatible = "rk_ldo2";
  4295. regulator-initial-state = <0x3>;
  4296. regulator-name = "rk_ldo2";
  4297. regulator-min-microvolt = <0x325aa0>;
  4298. regulator-max-microvolt = <0x325aa0>;
  4299. regulator-always-on;
  4300. regulator-boot-on;
  4301.  
  4302. regulator-state-mem {
  4303. regulator-state-enabled;
  4304. regulator-state-uv = <0x325aa0>;
  4305. };
  4306. };
  4307.  
  4308. regulator@6 {
  4309. reg = <0x6>;
  4310. regulator-compatible = "rk_ldo3";
  4311. regulator-initial-state = <0x3>;
  4312. regulator-name = "rk_ldo3";
  4313. regulator-min-microvolt = <0xf4240>;
  4314. regulator-max-microvolt = <0xf4240>;
  4315. regulator-always-on;
  4316. regulator-boot-on;
  4317.  
  4318. regulator-state-mem {
  4319. regulator-state-enabled;
  4320. regulator-state-uv = <0xf4240>;
  4321. };
  4322. };
  4323.  
  4324. regulator@7 {
  4325. reg = <0x7>;
  4326. regulator-compatible = "rk_ldo4";
  4327. regulator-initial-state = <0x3>;
  4328. regulator-name = "rk_ldo4";
  4329. regulator-min-microvolt = <0x1b7740>;
  4330. regulator-max-microvolt = <0x1b7740>;
  4331. regulator-always-on;
  4332. regulator-boot-on;
  4333.  
  4334. regulator-state-mem {
  4335. regulator-state-disabled;
  4336. regulator-state-uv = <0x1b7740>;
  4337. };
  4338. };
  4339.  
  4340. regulator@8 {
  4341. reg = <0x8>;
  4342. regulator-compatible = "rk_ldo5";
  4343. regulator-initial-state = <0x3>;
  4344. regulator-name = "rk_ldo5";
  4345. regulator-min-microvolt = <0x325aa0>;
  4346. regulator-max-microvolt = <0x325aa0>;
  4347. regulator-always-on;
  4348. regulator-boot-on;
  4349.  
  4350. regulator-state-mem {
  4351. regulator-state-enabled;
  4352. regulator-state-uv = <0x2ab980>;
  4353. };
  4354. };
  4355.  
  4356. regulator@9 {
  4357. reg = <0x9>;
  4358. regulator-compatible = "rk_ldo6";
  4359. regulator-initial-state = <0x3>;
  4360. regulator-name = "rk_ldo6";
  4361. regulator-min-microvolt = <0x1b7740>;
  4362. regulator-max-microvolt = <0x1b7740>;
  4363. regulator-always-on;
  4364. regulator-boot-on;
  4365.  
  4366. regulator-state-mem {
  4367. regulator-state-disabled;
  4368. regulator-state-uv = <0xf4240>;
  4369. };
  4370. };
  4371.  
  4372. regulator@10 {
  4373. reg = <0xa>;
  4374. regulator-compatible = "rk_ldo7";
  4375. regulator-initial-state = <0x3>;
  4376. regulator-name = "rk_ldo7";
  4377. regulator-min-microvolt = <0x1b7740>;
  4378. regulator-max-microvolt = <0x1b7740>;
  4379. regulator-always-on;
  4380. regulator-boot-on;
  4381.  
  4382. regulator-state-mem {
  4383. regulator-state-enabled;
  4384. regulator-state-uv = <0x1b7740>;
  4385. };
  4386. };
  4387.  
  4388. regulator@11 {
  4389. reg = <0xb>;
  4390. regulator-compatible = "rk_ldo8";
  4391. regulator-initial-state = <0x3>;
  4392. regulator-name = "rk_ldo8";
  4393. regulator-min-microvolt = <0x325aa0>;
  4394. regulator-max-microvolt = <0x325aa0>;
  4395. regulator-always-on;
  4396. regulator-boot-on;
  4397.  
  4398. regulator-state-mem {
  4399. regulator-state-enabled;
  4400. regulator-state-uv = <0x325aa0>;
  4401. };
  4402. };
  4403.  
  4404. regulator@12 {
  4405. reg = <0xc>;
  4406. regulator-compatible = "rk_ldo9";
  4407. regulator-initial-state = <0x3>;
  4408. regulator-name = "rk_ldo9";
  4409. regulator-always-on;
  4410. regulator-boot-on;
  4411.  
  4412. regulator-state-mem {
  4413. regulator-state-enabled;
  4414. };
  4415. };
  4416.  
  4417. regulator@13 {
  4418. reg = <0xd>;
  4419. regulator-compatible = "rk_ldo10";
  4420. regulator-initial-state = <0x3>;
  4421. regulator-name = "rk_ldo10";
  4422. regulator-always-on;
  4423. regulator-boot-on;
  4424.  
  4425. regulator-state-mem {
  4426. regulator-state-disabled;
  4427. };
  4428. };
  4429. };
  4430. };
  4431.  
  4432. syr827@40 {
  4433. compatible = "silergy,syr82x";
  4434. reg = <0x40>;
  4435. status = "okay";
  4436.  
  4437. regulators {
  4438. #address-cells = <0x1>;
  4439. #size-cells = <0x0>;
  4440.  
  4441. regulator@0 {
  4442. reg = <0x0>;
  4443. regulator-compatible = "syr82x_dcdc1";
  4444. regulator-name = "vdd_arm";
  4445. regulator-min-microvolt = <0xadf34>;
  4446. regulator-max-microvolt = <0x16e360>;
  4447. regulator-always-on;
  4448. regulator-boot-on;
  4449. regulator-initial-mode = <0x2>;
  4450. regulator-initial-state = <0x3>;
  4451.  
  4452. regulator-state-mem {
  4453. regulator-state-mode = <0x2>;
  4454. regulator-state-enabled;
  4455. regulator-state-uv = <0xdbba0>;
  4456. };
  4457. };
  4458. };
  4459. };
  4460.  
  4461. syr828@41 {
  4462. compatible = "silergy,syr82x";
  4463. reg = <0x41>;
  4464. status = "okay";
  4465.  
  4466. regulators {
  4467. #address-cells = <0x1>;
  4468. #size-cells = <0x0>;
  4469.  
  4470. regulator@0 {
  4471. reg = <0x0>;
  4472. regulator-compatible = "syr82x_dcdc1";
  4473. regulator-name = "vdd_gpu";
  4474. regulator-min-microvolt = <0xadf34>;
  4475. regulator-max-microvolt = <0x16e360>;
  4476. regulator-always-on;
  4477. regulator-boot-on;
  4478. regulator-initial-mode = <0x2>;
  4479. regulator-initial-state = <0x3>;
  4480.  
  4481. regulator-state-mem {
  4482. regulator-state-mode = <0x2>;
  4483. regulator-state-disabled;
  4484. regulator-state-uv = <0xdbba0>;
  4485. };
  4486. };
  4487. };
  4488. };
  4489.  
  4490. act8846@5a {
  4491. reg = <0x5a>;
  4492. status = "okay";
  4493. compatible = "act,act8846";
  4494. gpios = <0x4 0x1 0x1 0x95 0x2 0x1 0x95 0x1 0x1>;
  4495. act8846,system-power-controller;
  4496.  
  4497. regulators {
  4498. #address-cells = <0x1>;
  4499. #size-cells = <0x0>;
  4500.  
  4501. regulator@0 {
  4502. reg = <0x0>;
  4503. regulator-compatible = "act_dcdc1";
  4504. regulator-always-on;
  4505. regulator-boot-on;
  4506. regulator-name = "act_dcdc1";
  4507. regulator-min-microvolt = <0x124f80>;
  4508. regulator-max-microvolt = <0x124f80>;
  4509. };
  4510.  
  4511. regulator@1 {
  4512. reg = <0x1>;
  4513. regulator-compatible = "act_dcdc2";
  4514. regulator-always-on;
  4515. regulator-boot-on;
  4516. regulator-name = "vccio";
  4517. regulator-min-microvolt = <0x325aa0>;
  4518. regulator-max-microvolt = <0x325aa0>;
  4519. regulator-initial-state = <0x3>;
  4520.  
  4521. regulator-state-mem {
  4522. regulator-state-enabled;
  4523. regulator-state-uv = <0x325aa0>;
  4524. };
  4525. };
  4526.  
  4527. regulator@2 {
  4528. reg = <0x2>;
  4529. regulator-compatible = "act_dcdc3";
  4530. regulator-always-on;
  4531. regulator-boot-on;
  4532. regulator-name = "vdd_logic";
  4533. regulator-min-microvolt = <0xaae60>;
  4534. regulator-max-microvolt = <0x16e360>;
  4535. regulator-initial-state = <0x3>;
  4536.  
  4537. regulator-state-mem {
  4538. regulator-state-enabled;
  4539. regulator-state-uv = <0x124f80>;
  4540. };
  4541. };
  4542.  
  4543. regulator@3 {
  4544. reg = <0x3>;
  4545. regulator-compatible = "act_dcdc4";
  4546. regulator-always-on;
  4547. regulator-boot-on;
  4548. regulator-name = "act_dcdc4";
  4549. regulator-min-microvolt = <0x1e8480>;
  4550. regulator-max-microvolt = <0x1e8480>;
  4551. regulator-initial-state = <0x3>;
  4552.  
  4553. regulator-state-mem {
  4554. regulator-state-enabled;
  4555. regulator-state-uv = <0x1e8480>;
  4556. };
  4557. };
  4558.  
  4559. regulator@4 {
  4560. reg = <0x4>;
  4561. regulator-compatible = "act_ldo1";
  4562. regulator-always-on;
  4563. regulator-boot-on;
  4564. regulator-name = "vccio_sd";
  4565. regulator-min-microvolt = <0x1b7740>;
  4566. regulator-max-microvolt = <0x325aa0>;
  4567. linux,phandle = <0x82>;
  4568. phandle = <0x82>;
  4569. };
  4570.  
  4571. regulator@5 {
  4572. reg = <0x5>;
  4573. regulator-compatible = "act_ldo2";
  4574. regulator-boot-on;
  4575. regulator-name = "act_ldo2";
  4576. regulator-min-microvolt = <0x100590>;
  4577. regulator-max-microvolt = <0x100590>;
  4578. };
  4579.  
  4580. regulator@6 {
  4581. reg = <0x6>;
  4582. regulator-compatible = "act_ldo3";
  4583. regulator-boot-on;
  4584. regulator-name = "act_ldo3";
  4585. regulator-min-microvolt = <0x1b7740>;
  4586. regulator-max-microvolt = <0x1b7740>;
  4587. };
  4588.  
  4589. regulator@7 {
  4590. reg = <0x7>;
  4591. regulator-compatible = "act_ldo4";
  4592. regulator-boot-on;
  4593. regulator-name = "act_ldo4";
  4594. regulator-min-microvolt = <0x325aa0>;
  4595. regulator-max-microvolt = <0x325aa0>;
  4596. };
  4597.  
  4598. regulator@8 {
  4599. reg = <0x8>;
  4600. regulator-compatible = "act_ldo5";
  4601. regulator-always-on;
  4602. regulator-boot-on;
  4603. regulator-name = "act_ldo5";
  4604. regulator-min-microvolt = <0x325aa0>;
  4605. regulator-max-microvolt = <0x325aa0>;
  4606. };
  4607.  
  4608. regulator@9 {
  4609. reg = <0x9>;
  4610. regulator-compatible = "act_ldo6";
  4611. regulator-always-on;
  4612. regulator-boot-on;
  4613. regulator-name = "act_ldo6";
  4614. regulator-min-microvolt = <0x10c8e0>;
  4615. regulator-max-microvolt = <0x10c8e0>;
  4616. regulator-initial-state = <0x3>;
  4617.  
  4618. regulator-state-mem {
  4619. regulator-state-enabled;
  4620. };
  4621. };
  4622.  
  4623. regulator@10 {
  4624. reg = <0xa>;
  4625. regulator-compatible = "act_ldo7";
  4626. regulator-always-on;
  4627. regulator-boot-on;
  4628. regulator-name = "vcc_18";
  4629. regulator-min-microvolt = <0x1b7740>;
  4630. regulator-max-microvolt = <0x1b7740>;
  4631. regulator-initial-state = <0x3>;
  4632.  
  4633. regulator-state-mem {
  4634. regulator-state-enabled;
  4635. };
  4636. };
  4637.  
  4638. regulator@11 {
  4639. reg = <0xb>;
  4640. regulator-compatible = "act_ldo8";
  4641. regulator-boot-on;
  4642. regulator-name = "act_ldo8";
  4643. regulator-min-microvolt = <0x1c3a90>;
  4644. regulator-max-microvolt = <0x1c3a90>;
  4645. };
  4646. };
  4647. };
  4648.  
  4649. rtc@51 {
  4650. compatible = "rtc,hym8563";
  4651. reg = <0x51>;
  4652. irq_gpio = <0x95 0x4 0x2>;
  4653. };
  4654. };
  4655.  
  4656. i2c@ff140000 {
  4657. compatible = "rockchip,rk30-i2c";
  4658. reg = <0xff140000 0x1000>;
  4659. interrupts = <0x0 0x3e 0x4>;
  4660. #address-cells = <0x1>;
  4661. #size-cells = <0x0>;
  4662. pinctrl-names = "default", "gpio";
  4663. pinctrl-0 = <0xba 0xbb>;
  4664. pinctrl-1 = <0xbc>;
  4665. gpios = <0x3 0x4 0x1 0x3 0x5 0x1>;
  4666. clocks = <0xb4 0x3>;
  4667. rockchip,check-idle = <0x1>;
  4668. status = "okay";
  4669.  
  4670. lt8641ex@3f {
  4671. compatible = "tchip,lt8641ex";
  4672. gpio-sw = <0x4 0xa 0x1>;
  4673. reg = <0x3f>;
  4674. };
  4675.  
  4676. rtc@51 {
  4677. compatible = "nxp,pcf8563";
  4678. reg = <0x51>;
  4679. };
  4680. };
  4681.  
  4682. i2c@ff660000 {
  4683. compatible = "rockchip,rk30-i2c";
  4684. reg = <0xff660000 0x1000>;
  4685. interrupts = <0x0 0x3d 0x4>;
  4686. #address-cells = <0x1>;
  4687. #size-cells = <0x0>;
  4688. pinctrl-names = "default", "gpio";
  4689. pinctrl-0 = <0xbd 0xbe>;
  4690. pinctrl-1 = <0xbf>;
  4691. gpios = <0x81 0x9 0x1 0x81 0xa 0x1>;
  4692. clocks = <0x90 0xd>;
  4693. rockchip,check-idle = <0x1>;
  4694. status = "okay";
  4695. };
  4696.  
  4697. i2c@ff150000 {
  4698. compatible = "rockchip,rk30-i2c";
  4699. reg = <0xff150000 0x1000>;
  4700. interrupts = <0x0 0x3f 0x4>;
  4701. #address-cells = <0x1>;
  4702. #size-cells = <0x0>;
  4703. pinctrl-names = "default", "gpio";
  4704. pinctrl-0 = <0xc0 0xc1>;
  4705. pinctrl-1 = <0xc2>;
  4706. gpios = <0x96 0x11 0x1 0x96 0x10 0x1>;
  4707. clocks = <0x90 0xe>;
  4708. rockchip,check-idle = <0x1>;
  4709. status = "okay";
  4710. };
  4711.  
  4712. i2c@ff160000 {
  4713. compatible = "rockchip,rk30-i2c";
  4714. reg = <0xff160000 0x1000>;
  4715. interrupts = <0x0 0x40 0x4>;
  4716. #address-cells = <0x1>;
  4717. #size-cells = <0x0>;
  4718. pinctrl-names = "default", "gpio";
  4719. pinctrl-0 = <0xc3 0xc4>;
  4720. pinctrl-1 = <0xc5>;
  4721. gpios = <0x4 0x11 0x1 0x4 0x12 0x1>;
  4722. clocks = <0x90 0xf>;
  4723. rockchip,check-idle = <0x1>;
  4724. status = "okay";
  4725.  
  4726. rk1000_control@40 {
  4727. compatible = "rockchip,rk1000_control";
  4728. reg = <0x40>;
  4729. gpio-reset = <0x4 0x15 0x1>;
  4730. clocks = <0x20 0x63>;
  4731. clock-names = "i2s_clk", "i2s_mclk";
  4732. };
  4733.  
  4734. rk1000_tve@42 {
  4735. compatible = "rockchip,rk1000_tve";
  4736. reg = <0x42>;
  4737. rockchip,source = <0x0>;
  4738. rockchip,prop = <0x1>;
  4739. };
  4740.  
  4741. rk1000_codec@60 {
  4742. compatible = "rockchip,rk1000_codec";
  4743. reg = <0x60>;
  4744. spk_ctl_io = <0x4 0x5 0x1>;
  4745. boot_depop = <0x1>;
  4746. pa_enable_time = <0x1388>;
  4747. linux,phandle = <0x119>;
  4748. phandle = <0x119>;
  4749. };
  4750. };
  4751.  
  4752. i2c@ff170000 {
  4753. compatible = "rockchip,rk30-i2c";
  4754. reg = <0xff170000 0x1000>;
  4755. interrupts = <0x0 0x41 0x4>;
  4756. #address-cells = <0x1>;
  4757. #size-cells = <0x0>;
  4758. pinctrl-names = "default", "gpio";
  4759. pinctrl-0 = <0xc6 0xc7>;
  4760. pinctrl-1 = <0xc8>;
  4761. gpios = <0x4 0x13 0x1 0x4 0x14 0x1>;
  4762. clocks = <0x7a 0x0>;
  4763. rockchip,check-idle = <0x1>;
  4764. status = "disabled";
  4765. };
  4766.  
  4767. fb {
  4768. compatible = "rockchip,rk-fb";
  4769. rockchip,disp-mode = <0x2>;
  4770. };
  4771.  
  4772. rk_screen {
  4773. compatible = "rockchip,screen";
  4774. display-timings = <0xc9>;
  4775. };
  4776.  
  4777. mipi@ff960000 {
  4778. compatible = "rockchip,rk32-dsi";
  4779. rockchip,prop = <0x0>;
  4780. reg = <0xff960000 0x4000>;
  4781. interrupts = <0x0 0x13 0x4>;
  4782. clocks = <0x79 0xf 0xb 0x4 0xca>;
  4783. clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pd_mipi_dsi";
  4784. status = "disabled";
  4785. };
  4786.  
  4787. mipi@ff964000 {
  4788. compatible = "rockchip,rk32-dsi";
  4789. rockchip,prop = <0x1>;
  4790. reg = <0xff964000 0x4000>;
  4791. interrupts = <0x0 0x14 0x4>;
  4792. clocks = <0x79 0xf 0xb 0x5 0xca>;
  4793. clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pd_mipi_dsi";
  4794. status = "disabled";
  4795. };
  4796.  
  4797. lvds@ff96c000 {
  4798. compatible = "rockchip,rk32-lvds";
  4799. reg = <0xff96c000 0x4000>;
  4800. clocks = <0xb 0x7>;
  4801. clock-names = "pclk_lvds";
  4802. };
  4803.  
  4804. edp@ff970000 {
  4805. compatible = "rockchip,rk32-edp";
  4806. reg = <0xff970000 0x4000>;
  4807. interrupts = <0x0 0x62 0x4>;
  4808. clocks = <0x45 0x62 0xb 0x8>;
  4809. clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
  4810. };
  4811.  
  4812. hdmi@ff980000 {
  4813. compatible = "rockchip,rk3288-hdmi";
  4814. reg = <0xff980000 0x20000>;
  4815. interrupts = <0x0 0x67 0x4>;
  4816. pinctrl-names = "default", "gpio";
  4817. pinctrl-0 = <0xc6 0xc7 0xcb>;
  4818. pinctrl-1 = <0xc8>;
  4819. clocks = <0xb 0x9 0x79 0xc 0x79 0xb>;
  4820. clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
  4821. status = "okay";
  4822. rockchips,hdmi_audio_source = <0x0>;
  4823. hdmi_cec = <0x1>;
  4824. hdcp_enable = <0x0>;
  4825. };
  4826.  
  4827. lcdc@ff930000 {
  4828. compatible = "rockchip,rk3288-lcdc";
  4829. rockchip,prop = <0x1>;
  4830. rockchip,pwr18 = <0x0>;
  4831. rockchip,iommu-enabled = <0x1>;
  4832. reg = <0xff930000 0x10000>;
  4833. interrupts = <0x0 0xf 0x4>;
  4834. status = "okay";
  4835. clocks = <0xb5 0x5 0x44 0xb5 0x6 0xcc>;
  4836. clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "pd_lcdc";
  4837. };
  4838.  
  4839. lcdc@ff940000 {
  4840. compatible = "rockchip,rk3288-lcdc";
  4841. rockchip,prop = <0x2>;
  4842. rochchip,pwr18 = <0x0>;
  4843. rockchip,iommu-enabled = <0x1>;
  4844. reg = <0xff940000 0x10000>;
  4845. interrupts = <0x0 0x10 0x4>;
  4846. pinctrl-names = "default", "gpio";
  4847. pinctrl-0 = <0xcd>;
  4848. pinctrl-1 = <0xce>;
  4849. status = "disabled";
  4850. clocks = <0xb5 0x7 0x4b 0xb5 0x8 0xcf>;
  4851. clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "pd_lcdc";
  4852. };
  4853.  
  4854. adc@ff100000 {
  4855. compatible = "rockchip,saradc";
  4856. reg = <0xff100000 0x100>;
  4857. interrupts = <0x0 0x24 0x4>;
  4858. #io-channel-cells = <0x1>;
  4859. io-channel-ranges;
  4860. rockchip,adc-vref = <0x708>;
  4861. clock-frequency = <0xf4240>;
  4862. clocks = <0x61 0x7a 0x1>;
  4863. clock-names = "saradc", "pclk_saradc";
  4864. status = "okay";
  4865. linux,phandle = <0xd0>;
  4866. phandle = <0xd0>;
  4867.  
  4868. key {
  4869. compatible = "rockchip,key";
  4870. io-channels = <0xd0 0x1>;
  4871.  
  4872. power-key {
  4873. gpios = <0x95 0x5 0x1>;
  4874. linux,code = <0x74>;
  4875. label = "power";
  4876. gpio-key,wakeup;
  4877. };
  4878. };
  4879. };
  4880.  
  4881. rga@ff920000 {
  4882. compatible = "rockchip,rga";
  4883. reg = <0xff920000 0x1000>;
  4884. interrupts = <0x0 0x12 0x4>;
  4885. clocks = <0xb5 0x1 0x4c 0x4d>;
  4886. clock-names = "hclk_rga", "aclk_rga", "clk_rga";
  4887. };
  4888.  
  4889. rockchip-i2s@0xff890000 {
  4890. compatible = "rockchip-i2s";
  4891. reg = <0xff890000 0x10000>;
  4892. i2s-id = <0x0>;
  4893. clocks = <0x20 0x63 0xb4 0x8>;
  4894. clock-names = "i2s_clk", "i2s_mclk", "i2s_hclk";
  4895. interrupts = <0x0 0x35 0x4>;
  4896. dmas = <0xa7 0x0 0xa7 0x1>;
  4897. dma-names = "tx", "rx";
  4898. pinctrl-names = "default", "sleep";
  4899. pinctrl-0 = <0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xd8 0xd9>;
  4900. pinctrl-1 = <0xda>;
  4901. linux,phandle = <0x116>;
  4902. phandle = <0x116>;
  4903. };
  4904.  
  4905. rockchip-spdif@0xff8b0000 {
  4906. compatible = "rockchip-spdif";
  4907. reg = <0xff8b0000 0x10000>;
  4908. clocks = <0x64 0x65 0xb4 0xb>;
  4909. clock-names = "spdif_mclk", "spdif_8ch_mclk", "spdif_hclk";
  4910. interrupts = <0x0 0x56 0x4>;
  4911. dmas = <0xa7 0x3>;
  4912. dma-names = "tx";
  4913. pinctrl-names = "default", "sleep";
  4914. pinctrl-0 = <0xdb>;
  4915. pinctrl-1 = <0xdc>;
  4916. linux,phandle = <0x118>;
  4917. phandle = <0x118>;
  4918. };
  4919.  
  4920. pwm@ff9401a0 {
  4921. compatible = "rockchip,vop-pwm";
  4922. reg = <0xff9401a0 0x10>;
  4923. #pwm-cells = <0x2>;
  4924. pinctrl-names = "default";
  4925. pinctrl-0 = <0xdd>;
  4926. clocks = <0x9 0xb>;
  4927. clock-names = "pclk_pwm";
  4928. status = "disabled";
  4929. };
  4930.  
  4931. pwm@ff9301a0 {
  4932. compatible = "rockchip,vop-pwm";
  4933. ir-led-gpio = <0x3 0x3 0x1>;
  4934. reg = <0xff9301a0 0x10>;
  4935. #pwm-cells = <0x2>;
  4936. pinctrl-names = "default";
  4937. pinctrl-0 = <0xde>;
  4938. clocks = <0x9 0xa>;
  4939. clock-names = "pclk_pwm";
  4940. status = "disabled";
  4941. };
  4942.  
  4943. pwm@ff680000 {
  4944. compatible = "rockchip,rk-pwm0";
  4945. reg = <0xff680000 0x10>;
  4946. #pwm-cells = <0x2>;
  4947. pinctrl-names = "default";
  4948. pinctrl-0 = <0xdf>;
  4949. clocks = <0xa6 0xb>;
  4950. clock-names = "pclk_pwm";
  4951. status = "okay";
  4952. ir-emission-gpio = <0x95 0xa 0x1>;
  4953. interrupts = <0x0 0x4e 0x4>;
  4954. };
  4955.  
  4956. pwm@ff680010 {
  4957. compatible = "rockchip,rk-pwm";
  4958. reg = <0xff680010 0x10>;
  4959. #pwm-cells = <0x2>;
  4960. pinctrl-names = "default";
  4961. pinctrl-0 = <0xe0>;
  4962. clocks = <0xa6 0xb>;
  4963. clock-names = "pclk_pwm";
  4964. status = "disabled";
  4965. linux,phandle = <0x114>;
  4966. phandle = <0x114>;
  4967. };
  4968.  
  4969. pwm@ff680020 {
  4970. compatible = "rockchip,rk-pwm";
  4971. reg = <0xff680020 0x10>;
  4972. #pwm-cells = <0x2>;
  4973. pinctrl-names = "default";
  4974. pinctrl-0 = <0xe1>;
  4975. clocks = <0xa6 0xb>;
  4976. clock-names = "pclk_pwm";
  4977. status = "disabled";
  4978. };
  4979.  
  4980. pwm@ff680030 {
  4981. compatible = "rockchip,rk-pwm";
  4982. reg = <0xff680030 0x10>;
  4983. #pwm-cells = <0x2>;
  4984. pinctrl-names = "default";
  4985. pinctrl-0 = <0xe2>;
  4986. clocks = <0xa6 0xb>;
  4987. clock-names = "pclk_pwm";
  4988. status = "disabled";
  4989. };
  4990.  
  4991. dvfs {
  4992.  
  4993. vd_arm {
  4994. regulator_name = "vdd_arm";
  4995. suspend_volt = <0x3e8>;
  4996.  
  4997. pd_core {
  4998.  
  4999. clk_core {
  5000. operating-points = <0x4c2c0 0x10c8e0 0x7b0c0 0x10c8e0 0xc7380 0x10c8e0 0xf6180 0x10c8e0>;
  5001. channel = <0x0>;
  5002. temp-limit-enable = <0x1>;
  5003. target-temp = <0x5f>;
  5004. normal-temp-limit = <0x3 0x17700 0x6 0x23280 0x9 0x2ee00 0xf 0x5dc00>;
  5005. performance-temp-limit = <0x64 0xc7380>;
  5006. status = "okay";
  5007. support-pvtm = <0x0>;
  5008. pvtm-operating-points = <0x1ec30 0xdbba0 0x61a8 0x34bc0 0xdbba0 0x61a8 0x4c2c0 0xdbba0 0x61a8 0x639c0 0xdbba0 0x61a8 0x927c0 0xe7ef0 0xc350 0xa9ec0 0xe7ef0 0xc350 0xc7380 0xf4240 0xc350 0xf6180 0x100590 0x124f8 0x124f80 0x10c8e0 0x124f8 0x159b40 0x124f80 0x124f8 0x171240 0x13d620 0x124f8 0x188940 0x149970 0x124f8 0x1a0040 0x149970 0x124f8 0x1b7740 0x149970 0x124f8>;
  5009. };
  5010. };
  5011. };
  5012.  
  5013. vd_logic {
  5014. regulator_name = "vdd_logic";
  5015. suspend_volt = <0x3e8>;
  5016.  
  5017. pd_ddr {
  5018.  
  5019. clk_ddr {
  5020. operating-points = <0x30d40 0x106738 0xc15c0 0x149970>;
  5021. channel = <0x2>;
  5022. status = "okay";
  5023. freq-table = <0x1 0xc15c0 0x2 0x30d40 0x10 0xc15c0 0x2000 0xc15c0>;
  5024. auto-freq-table = <0x3a980 0x4f1a0 0x6f540 0x80e80>;
  5025. auto-freq = <0x0>;
  5026. };
  5027. };
  5028.  
  5029. pd_vio {
  5030.  
  5031. aclk_vio1 {
  5032. operating-points = <0x186a0 0x10c8e0 0x7a120 0x10c8e0>;
  5033. status = "okay";
  5034. };
  5035. };
  5036. };
  5037.  
  5038. vd_gpu {
  5039. regulator_name = "vdd_gpu";
  5040. suspend_volt = <0x3e8>;
  5041.  
  5042. pd_gpu {
  5043.  
  5044. clk_gpu {
  5045. operating-points = <0x30d40 0xdbba0 0x493e0 0xe7ef0 0x668a0 0x10c8e0 0x7a120 0x118c30 0x927c0 0x1312d0>;
  5046. channel = <0x1>;
  5047. status = "okay";
  5048. };
  5049. };
  5050. };
  5051. };
  5052.  
  5053. ion {
  5054. compatible = "rockchip,ion";
  5055. #address-cells = <0x1>;
  5056. #size-cells = <0x0>;
  5057.  
  5058. rockchip,ion-heap@3 {
  5059. rockchip,ion_heap = <0x3>;
  5060. };
  5061. };
  5062.  
  5063. vpu_service@ff9a0000 {
  5064. compatible = "vpu_service";
  5065. iommu_enabled = <0x1>;
  5066. reg = <0xff9a0000 0x800>;
  5067. interrupts = <0x0 0x9 0x4 0x0 0xa 0x4>;
  5068. interrupt-names = "irq_enc", "irq_dec";
  5069. clocks = <0xd 0xe3>;
  5070. clock-names = "aclk_vcodec", "hclk_vcodec";
  5071. };
  5072.  
  5073. hevc_service@ff9c0000 {
  5074. compatible = "rockchip,hevc_service";
  5075. iommu_enabled = <0x1>;
  5076. reg = <0xff9c0000 0x800>;
  5077. interrupts = <0x0 0xc 0x4>;
  5078. interrupt-names = "irq_dec";
  5079. clocks = <0x57 0xb1 0x5b 0x5a>;
  5080. clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac";
  5081. };
  5082.  
  5083. iep@ff900000 {
  5084. compatible = "rockchip,iep";
  5085. iommu_enabled = <0x1>;
  5086. reg = <0xff900000 0x800>;
  5087. interrupts = <0x0 0x11 0x4>;
  5088. clocks = <0xb5 0x2 0xb5 0x3>;
  5089. clock-names = "aclk_iep", "hclk_iep";
  5090. status = "okay";
  5091. };
  5092.  
  5093. dwc-control-usb@ff770284 {
  5094. compatible = "rockchip,rk3288-dwc-control-usb";
  5095. reg = <0xff770284 0x4 0xff770288 0x4 0xff7702cc 0x4 0xff7702d4 0x4 0xff770320 0x14 0xff770334 0x14 0xff770348 0x10 0xff770358 0x8 0xff770360 0x8>;
  5096. reg-names = "GRF_SOC_STATUS1", "GRF_SOC_STATUS2", "GRF_SOC_STATUS19", "GRF_SOC_STATUS21", "GRF_UOC0_BASE", "GRF_UOC1_BASE", "GRF_UOC2_BASE", "GRF_UOC3_BASE", "GRF_UOC4_BASE";
  5097. interrupts = <0x0 0x5d 0x4 0x0 0x5e 0x4 0x0 0x5f 0x4 0x0 0x60 0x4 0x0 0x61 0x4>;
  5098. interrupt-names = "otg_id", "otg_bvalid", "otg_linestate", "host0_linestate", "host1_linestate";
  5099. clocks = <0x7a 0x9 0x31 0x2e 0x2f>;
  5100. clock-names = "hclk_usb_peri", "usbphy_480m", "usbphy1_480m", "usbphy2_480m";
  5101.  
  5102. usb_bc {
  5103. compatible = "synopsys,phy";
  5104. rk_usb,bvalid = <0x288 0xe 0x1>;
  5105. rk_usb,iddig = <0x288 0x11 0x1>;
  5106. rk_usb,dcdenb = <0x328 0xe 0x1>;
  5107. rk_usb,vdatsrcenb = <0x328 0x7 0x1>;
  5108. rk_usb,vdatdetenb = <0x328 0x6 0x1>;
  5109. rk_usb,chrgsel = <0x328 0x5 0x1>;
  5110. rk_usb,chgdet = <0x2cc 0x17 0x1>;
  5111. rk_usb,fsvminus = <0x2cc 0x19 0x1>;
  5112. rk_usb,fsvplus = <0x2cc 0x18 0x1>;
  5113. };
  5114. };
  5115.  
  5116. usb@ff580000 {
  5117. compatible = "rockchip,rk3288_usb20_otg";
  5118. reg = <0xff580000 0x40000>;
  5119. interrupts = <0x0 0x17 0x4>;
  5120. clocks = <0x9 0x4 0x7a 0x4>;
  5121. clock-names = "clk_usbphy0", "hclk_usb0";
  5122. resets = <0xe4 0x84 0xe4 0x85 0xe4 0x86>;
  5123. reset-names = "otg_ahb", "otg_phy", "otg_controller";
  5124. rockchip,usb-mode = <0x1>;
  5125. };
  5126.  
  5127. usb@ff540000 {
  5128. compatible = "rockchip,rk3288_usb20_host";
  5129. reg = <0xff540000 0x40000>;
  5130. interrupts = <0x0 0x19 0x4>;
  5131. clocks = <0x9 0x6 0x7a 0x7 0x31>;
  5132. clock-names = "clk_usbphy1", "hclk_usb1", "usbphy_480m";
  5133. resets = <0xe4 0x8a 0xe4 0x8b 0xe4 0x8c>;
  5134. reset-names = "host1_ahb", "host1_phy", "host1_controller";
  5135. };
  5136.  
  5137. usb@ff500000 {
  5138. compatible = "rockchip,rk3288_rk_ehci_host";
  5139. reg = <0xff500000 0x20000>;
  5140. interrupts = <0x0 0x18 0x4>;
  5141. clocks = <0x9 0x5 0x7a 0x6>;
  5142. clock-names = "clk_usbphy2", "hclk_usb2";
  5143. resets = <0xe4 0x87 0xe4 0x88 0xe4 0x89 0xe4 0x48>;
  5144. reset-names = "ehci_ahb", "ehci_phy", "ehci_controller", "ehci";
  5145. };
  5146.  
  5147. usb@ff520000 {
  5148. compatible = "rockchip,rk3288_rk_ohci_host";
  5149. reg = <0xff520000 0x20000>;
  5150. interrupts = <0x0 0x29 0x4>;
  5151. clocks = <0x9 0x5 0x7a 0x6>;
  5152. clock-names = "clk_usbphy3", "hclk_usb3";
  5153. };
  5154.  
  5155. hsic@ff5c0000 {
  5156. compatible = "rockchip,rk3288_rk_hsic_host";
  5157. reg = <0xff5c0000 0x40000>;
  5158. interrupts = <0x0 0x1a 0x4>;
  5159. clocks = <0x29 0x7a 0x8 0xe5 0x31 0x2e 0x2f>;
  5160. clock-names = "hsicphy_480m", "hclk_hsic", "hsicphy_12m", "usbphy_480m", "hsic_usbphy1", "hsic_usbphy2";
  5161. resets = <0xe4 0x49 0xe4 0x4a 0xe4 0x4b>;
  5162. reset-names = "hsic_ahb", "hsic_aux", "hsic_phy";
  5163. };
  5164.  
  5165. eth@ff290000 {
  5166. compatible = "rockchip,rk3288-gmac";
  5167. reg = <0xff290000 0x10000>;
  5168. interrupts = <0x0 0x1b 0x4>;
  5169. interrupt-names = "macirq";
  5170. clocks = <0x67 0x79 0x0 0x79 0x1 0x79 0x2 0x79 0x3 0x7b 0x0 0x7b 0x1>;
  5171. clock-names = "clk_mac", "mac_clk_rx", "mac_clk_tx", "clk_mac_ref", "clk_mac_refout", "aclk_mac", "pclk_mac";
  5172. phy-mode = "rgmii";
  5173. pinctrl-names = "default";
  5174. pinctrl-0 = <0xe6 0xe7 0xe8 0xe9>;
  5175. reset-gpio = <0x5 0x8 0x1>;
  5176. clock_in_out = "input";
  5177. tx_delay = <0x30>;
  5178. rx_delay = <0x20>;
  5179. };
  5180.  
  5181. rockchip-tsp@0xff420000 {
  5182. compatible = "rockchip-tsp";
  5183. reg = <0xff420000 0x10000>;
  5184. i2s-id = <0x0>;
  5185. clocks = <0x20 0x63>;
  5186. clock-names = "i2s_clk", "i2s_mclk";
  5187. interrupts = <0x0 0x55 0x4>;
  5188. dmas = <0xa7 0x0 0xa7 0x1>;
  5189. dma-names = "tx", "rx";
  5190. pinctrl-names = "default", "sleep";
  5191. pinctrl-0 = <0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xd8 0xd9>;
  5192. pinctrl-1 = <0xda>;
  5193. };
  5194.  
  5195. gpu {
  5196. compatible = "arm,malit764", "arm,malit76x", "arm,malit7xx", "arm,mali-midgard";
  5197. reg = <0xffa30000 0x10000>;
  5198. interrupts = <0x0 0x6 0x4 0x0 0x7 0x4 0x0 0x8 0x4>;
  5199. interrupt-names = "JOB", "MMU", "GPU";
  5200. };
  5201.  
  5202. iep_mmu {
  5203. dbgname = "iep";
  5204. compatible = "rockchip,iep_mmu";
  5205. reg = <0xff900800 0x100>;
  5206. interrupts = <0x0 0x11 0x4>;
  5207. interrupt-names = "iep_mmu";
  5208. };
  5209.  
  5210. vip_mmu {
  5211. dbgname = "vip";
  5212. compatible = "rockchip,vip_mmu";
  5213. reg = <0xff950800 0x100>;
  5214. interrupts = <0x0 0xd 0x4>;
  5215. interrupt-names = "vip_mmu";
  5216. };
  5217.  
  5218. vopb_mmu {
  5219. dbgname = "vopb";
  5220. compatible = "rockchip,vopb_mmu";
  5221. reg = <0xff930300 0x100>;
  5222. interrupts = <0x0 0xf 0x4>;
  5223. interrupt-names = "vopb_mmu";
  5224. };
  5225.  
  5226. vopl_mmu {
  5227. dbgname = "vopl";
  5228. compatible = "rockchip,vopl_mmu";
  5229. reg = <0xff940300 0x100>;
  5230. interrupts = <0x0 0x10 0x4>;
  5231. interrupt-names = "vopl_mmu";
  5232. };
  5233.  
  5234. hevc_mmu {
  5235. dbgname = "hevc";
  5236. compatible = "rockchip,hevc_mmu";
  5237. reg = <0xff9c0440 0x40 0xff9c0480 0x40>;
  5238. interrupts = <0x0 0x6f 0x4>;
  5239. interrupt-names = "hevc_mmu";
  5240. };
  5241.  
  5242. vpu_mmu {
  5243. dbgname = "vpu";
  5244. compatible = "rockchip,vpu_mmu";
  5245. reg = <0xff9a0800 0x100>;
  5246. interrupts = <0x0 0xb 0x4>;
  5247. interrupt-names = "vpu_mmu";
  5248. };
  5249.  
  5250. isp_mmu {
  5251. dbgname = "isp_mmu";
  5252. compatible = "rockchip,isp_mmu";
  5253. reg = <0xff914000 0x100 0xff915000 0x100>;
  5254. interrupts = <0x0 0xe 0x4>;
  5255. interrupt-names = "isp_mmu";
  5256. };
  5257.  
  5258. rockchip_suspend {
  5259. rockchip,ctrbits = <0x40017>;
  5260. rockchip,pmic-gpios = <0x4000a00 0x1000a10>;
  5261. rockchip,pmic-suspend_gpios = <0x1007c30 0x1007c40>;
  5262. rockchip,pmic-resume_gpios = <0x2007c32 0x2007c42>;
  5263. };
  5264.  
  5265. isp@ff910000 {
  5266. compatible = "rockchip,isp";
  5267. reg = <0xff910000 0x10000>;
  5268. interrupts = <0x0 0xe 0x4>;
  5269. clocks = <0xb 0x2 0xb 0x1 0x24 0x26 0xea 0x41 0x79 0xf 0x42 0xeb 0xb 0x6>;
  5270. clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_cif_out", "clk_mipi_24m", "clk_cif_pll", "pd_isp", "hclk_mipiphy1";
  5271. pinctrl-names = "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl", "isp_mipi_fl_prefl";
  5272. pinctrl-0 = <0xec>;
  5273. pinctrl-1 = <0xec 0xed>;
  5274. pinctrl-2 = <0xec 0xed 0xee>;
  5275. pinctrl-3 = <0xec 0xed 0xee 0xef>;
  5276. pinctrl-4 = <0xec 0xf0>;
  5277. pinctrl-5 = <0xec 0xf1>;
  5278. pinctrl-6 = <0xec 0xf1 0xf2>;
  5279. rockchip,isp,mipiphy = <0x2>;
  5280. rockchip,isp,cifphy = <0x1>;
  5281. rockchip,isp,mipiphy1,reg = <0xff968000 0x4000>;
  5282. rockchip,gpios = <0x4 0xd 0x0>;
  5283. rockchip,isp,iommu_enable = <0x1>;
  5284. status = "okay";
  5285. };
  5286.  
  5287. tsadc@ff280000 {
  5288. compatible = "rockchip,tsadc";
  5289. reg = <0xff280000 0x100>;
  5290. interrupts = <0x0 0x25 0x4>;
  5291. #io-channel-cells = <0x1>;
  5292. io-channel-ranges;
  5293. clock-frequency = <0xc350>;
  5294. clocks = <0x60 0x7a 0x2>;
  5295. clock-names = "tsadc", "pclk_tsadc";
  5296. status = "okay";
  5297. };
  5298.  
  5299. lcdc-vdd-domain {
  5300. compatible = "rockchip,io_vol_domain";
  5301. pinctrl-names = "default", "1.8V", "3.3V";
  5302. pinctrl-0 = <0xf3>;
  5303. pinctrl-1 = <0xf4>;
  5304. pinctrl-2 = <0xf5>;
  5305. regulator-name = "vcc30_lcd";
  5306. };
  5307.  
  5308. dpio-vdd-domain {
  5309. compatible = "rockchip,io_vol_domain";
  5310. pinctrl-names = "default", "1.8V", "3.3V";
  5311. pinctrl-0 = <0xf6>;
  5312. pinctrl-1 = <0xf7>;
  5313. pinctrl-2 = <0xf8>;
  5314. regulator-name = "vcc18_cif";
  5315. };
  5316.  
  5317. flash0-vdd-domain {
  5318. compatible = "rockchip,io_vol_domain";
  5319. pinctrl-names = "default", "1.8V", "3.3V";
  5320. pinctrl-0 = <0xf9>;
  5321. pinctrl-1 = <0xfa>;
  5322. pinctrl-2 = <0xfb>;
  5323. regulator-name = "vcc_flash";
  5324. };
  5325.  
  5326. flash1-vdd-domain {
  5327. compatible = "rockchip,io_vol_domain";
  5328. pinctrl-names = "default", "1.8V", "3.3V";
  5329. pinctrl-0 = <0xfc>;
  5330. pinctrl-1 = <0xfd>;
  5331. pinctrl-2 = <0xfe>;
  5332. regulator-name = "vcc_flash";
  5333. };
  5334.  
  5335. apio3-vdd-domain {
  5336. compatible = "rockchip,io_vol_domain";
  5337. pinctrl-names = "default", "1.8V", "3.3V";
  5338. pinctrl-0 = <0xff>;
  5339. pinctrl-1 = <0x100>;
  5340. pinctrl-2 = <0x101>;
  5341. regulator-name = "vccio_wl";
  5342. };
  5343.  
  5344. apio5-vdd-domain {
  5345. compatible = "rockchip,io_vol_domain";
  5346. pinctrl-names = "default", "1.8V", "3.3V";
  5347. pinctrl-0 = <0x102>;
  5348. pinctrl-1 = <0x103>;
  5349. pinctrl-2 = <0x104>;
  5350. regulator-name = "vccio";
  5351. };
  5352.  
  5353. apio4-vdd-domain {
  5354. compatible = "rockchip,io_vol_domain";
  5355. pinctrl-names = "default", "1.8V", "3.3V";
  5356. pinctrl-0 = <0x105>;
  5357. pinctrl-1 = <0x106>;
  5358. pinctrl-2 = <0x107>;
  5359. regulator-name = "vccio";
  5360. };
  5361.  
  5362. apio0-vdd-domain {
  5363. compatible = "rockchip,io_vol_domain";
  5364. pinctrl-names = "default", "1.8V", "3.3V";
  5365. pinctrl-0 = <0x108>;
  5366. pinctrl-1 = <0x109>;
  5367. pinctrl-2 = <0x10a>;
  5368. regulator-name = "vccio";
  5369. };
  5370.  
  5371. apio2-vdd-domain {
  5372. compatible = "rockchip,io_vol_domain";
  5373. pinctrl-names = "default", "1.8V", "3.3V";
  5374. pinctrl-0 = <0x10b>;
  5375. pinctrl-1 = <0x10c>;
  5376. pinctrl-2 = <0x10d>;
  5377. regulator-name = "vccio";
  5378. };
  5379.  
  5380. sdmmc0-vdd-domain {
  5381. compatible = "rockchip,io_vol_domain";
  5382. pinctrl-names = "default", "1.8V", "3.3V";
  5383. pinctrl-0 = <0x10e>;
  5384. pinctrl-1 = <0x10f>;
  5385. pinctrl-2 = <0x110>;
  5386. regulator-name = "vcc_sd";
  5387. };
  5388.  
  5389. power_ctr {
  5390. };
  5391.  
  5392. display-timings {
  5393. native-mode = <0x111>;
  5394. linux,phandle = <0xc9>;
  5395. phandle = <0xc9>;
  5396.  
  5397. timing0 {
  5398. screen-type = <0x1>;
  5399. out-face = <0x0>;
  5400. clock-frequency = <0x46cf710>;
  5401. hactive = <0x500>;
  5402. vactive = <0x2d0>;
  5403. hback-porch = <0xdc>;
  5404. hfront-porch = <0x6e>;
  5405. vback-porch = <0x14>;
  5406. vfront-porch = <0x5>;
  5407. hsync-len = <0x28>;
  5408. vsync-len = <0x5>;
  5409. hsync-active = <0x1>;
  5410. vsync-active = <0x1>;
  5411. de-active = <0x0>;
  5412. pixelclk-active = <0x0>;
  5413. swap-rb = <0x0>;
  5414. swap-rg = <0x0>;
  5415. swap-gb = <0x0>;
  5416. };
  5417.  
  5418. timing1 {
  5419. screen-type = <0x1>;
  5420. out-face = <0x0>;
  5421. clock-frequency = <0x8d9ee20>;
  5422. hactive = <0x780>;
  5423. vactive = <0x438>;
  5424. hback-porch = <0x94>;
  5425. hfront-porch = <0x58>;
  5426. vback-porch = <0x24>;
  5427. vfront-porch = <0x4>;
  5428. hsync-len = <0x2c>;
  5429. vsync-len = <0x5>;
  5430. hsync-active = <0x1>;
  5431. vsync-active = <0x1>;
  5432. de-active = <0x0>;
  5433. pixelclk-active = <0x0>;
  5434. swap-rb = <0x0>;
  5435. swap-rg = <0x0>;
  5436. swap-gb = <0x0>;
  5437. linux,phandle = <0x111>;
  5438. phandle = <0x111>;
  5439. };
  5440.  
  5441. timing2 {
  5442. screen-type = <0x1>;
  5443. out-face = <0x0>;
  5444. clock-frequency = <0x11b3dc40>;
  5445. hactive = <0xf00>;
  5446. vactive = <0x870>;
  5447. hback-porch = <0x128>;
  5448. hfront-porch = <0xb0>;
  5449. vback-porch = <0x48>;
  5450. vfront-porch = <0x8>;
  5451. hsync-len = <0x58>;
  5452. vsync-len = <0xa>;
  5453. hsync-active = <0x1>;
  5454. vsync-active = <0x1>;
  5455. de-active = <0x0>;
  5456. pixelclk-active = <0x0>;
  5457. swap-rb = <0x0>;
  5458. swap-rg = <0x0>;
  5459. swap-gb = <0x0>;
  5460. };
  5461. };
  5462.  
  5463. wireless-wlan {
  5464. compatible = "wlan-platdata";
  5465. wifi_chip_type = "bcmwifi";
  5466. sdio_vref = <0x708>;
  5467. power_pmu_regulator = "act_ldo3";
  5468. power_pmu_enable_level = <0x1>;
  5469. vref_pmu_regulator = "act_ldo3";
  5470. vref_pmu_enable_level = <0x1>;
  5471. WIFI,poweren_gpio = <0x5 0x1c 0x0>;
  5472. WIFI,host_wake_irq = <0x5 0x1e 0x0>;
  5473. status = "okay";
  5474. };
  5475.  
  5476. wireless-bluetooth {
  5477. compatible = "bluetooth-platdata";
  5478. uart_rts_gpios = <0x5 0x13 0x1>;
  5479. pinctrl-names = "default", "rts_gpio";
  5480. pinctrl-0 = <0x112>;
  5481. pinctrl-1 = <0x113>;
  5482. BT,power_gpio = <0x5 0x1b 0x0>;
  5483. BT,reset_gpio = <0x5 0x1d 0x0>;
  5484. BT,wake_gpio = <0x5 0x1a 0x0>;
  5485. BT,wake_host_irq = <0x5 0x1f 0x0>;
  5486. status = "okay";
  5487. };
  5488.  
  5489. pwm_regulator {
  5490. compatible = "rockchip_pwm_regulator";
  5491. pwms = <0x114 0x0 0x7d0>;
  5492. rockchip,pwm_id = <0x1>;
  5493. rockchip,pwm_voltage_map = <0xe1d48 0xe7ef0 0xee098 0xf4240 0xfa3e8 0x100590 0x106738 0x10c8e0 0x112a88 0x118c30 0x11edd8 0x124f80 0x12b128 0x1312d0 0x137478 0x13d620 0x1437c8 0x149970 0x14fb18 0x155cc0>;
  5494. rockchip,pwm_voltage = <0x10c8e0>;
  5495. rockchip,pwm_min_voltage = <0xe1d48>;
  5496. rockchip,pwm_max_voltage = <0x155cc0>;
  5497. rockchip,pwm_suspend_voltage = <0xe7ef0>;
  5498. rockchip,pwm_coefficient = <0x1db>;
  5499.  
  5500. regulators {
  5501. #address-cells = <0x1>;
  5502. #size-cells = <0x0>;
  5503.  
  5504. regulator@0 {
  5505. regulator-compatible = "pwm_dcdc1";
  5506. regulator-name = "vdd_logic";
  5507. regulator-min-microvolt = <0xe1d48>;
  5508. regulator-max-microvolt = <0x155cc0>;
  5509. regulator-always-on;
  5510. regulator-boot-on;
  5511. };
  5512. };
  5513. };
  5514.  
  5515. codec-hdmi-i2s {
  5516. compatible = "hdmi-i2s";
  5517. linux,phandle = <0x115>;
  5518. phandle = <0x115>;
  5519. };
  5520.  
  5521. codec-hdmi-spdif {
  5522. compatible = "hdmi-spdif";
  5523. linux,phandle = <0x117>;
  5524. phandle = <0x117>;
  5525. };
  5526.  
  5527. rockchip-hdmi-i2s {
  5528. compatible = "rockchip-hdmi-i2s";
  5529.  
  5530. dais {
  5531.  
  5532. dai0 {
  5533. audio-codec = <0x115>;
  5534. i2s-controller = <0x116>;
  5535. format = "i2s";
  5536. };
  5537. };
  5538. };
  5539.  
  5540. rockchip-hdmi-spdif {
  5541. compatible = "rockchip-hdmi-spdif";
  5542.  
  5543. dais {
  5544.  
  5545. dai0 {
  5546. audio-codec = <0x117>;
  5547. i2s-controller = <0x118>;
  5548. };
  5549. };
  5550. };
  5551.  
  5552. rockchip-rk1000 {
  5553. compatible = "rockchip-rk1000";
  5554.  
  5555. dais {
  5556.  
  5557. dai0 {
  5558. audio-codec = <0x119>;
  5559. i2s-controller = <0x116>;
  5560. format = "i2s";
  5561. };
  5562. };
  5563. };
  5564.  
  5565. rkxx-remotectl {
  5566. compatible = "rockchip,remotectl";
  5567. module-gpios = <0x4 0x0 0x1>;
  5568. status = "okay";
  5569. };
  5570.  
  5571. usb_control {
  5572. compatible = "rockchip,rk3288-usb-control";
  5573. host_drv_gpio = <0x95 0xe 0x1>;
  5574. otg_drv_gpio = <0x95 0xc 0x1>;
  5575. rockchip,remote_wakeup;
  5576. rockchip,usb_irq_wakeup;
  5577. };
  5578.  
  5579. leds@fff16100 {
  5580. reg = <0xfff16100 0x10>;
  5581. compatible = "gpio-leds";
  5582.  
  5583. power {
  5584. label = "blue:power";
  5585. linux,default-trigger = "ir-click";
  5586. default-state = "on";
  5587. gpios = <0x3 0x3 0x1>;
  5588. };
  5589. };
  5590.  
  5591. ug_fan@fff16000 {
  5592. reg = <0xfff16000 0x10>;
  5593. compatible = "ug_fan";
  5594. fan-gpio = <0x3 0x9 0x0>;
  5595. fan-mode = <0x2>;
  5596. fan-on-temp = <0x46>;
  5597. fan-off-temp = <0x41>;
  5598. };
  5599. };
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