`timescale 1ns / 1ps

module delays_and_counter #
    (
        parameter N_WIDTH = 32,
        parameter delay_count_width = 32,
        parameter CE_count_width = 32,
        parameter delay_value = 50000,
        parameter number_of_half_periods = 51
    )

    (
        (* X_INTERFACE_PARAMETER = "FREQ_HZ 125000000" *)
        input clk,
        input wire valid,
        input wire signed [13:0] DDS_signal,
        input [N_WIDTH-1:0] signal_freq,
        input [31:0] gain,
        input [31:0] DDS_Phase,
        input signed [13:0] Raw_ADC,
        input signed [13:0] Raw_ADC_measurment,
        output wire cl_en,
        output wire res,
        output wire resDDS,
        output wire DDS_valid,
        output [31:0] gain_r,
        output signed [13:0] max_ADC,
        output signed [13:0] max_ADC_measurment
     );

    reg delay_counter_permission = 0;
    reg [delay_count_width-1:0] delay_counter = 0;
    reg [delay_count_width-1:0] delay_counter_past = 0;
    reg [CE_count_width-1:0] CE_permission_counter = 0;
    reg CE = 0;
    reg reset = 0;
    reg reset_DDS = 0;
    reg val_DDS = 0;
    reg signed [13:0] present_value = 1;
    reg signed [13:0] past_value = 1;
    reg [31:0] present_phase = 0;
    reg [31:0] past_phase = 0;
    reg [31:0] counter_of_half_periods = 0;
    reg [31:0] past_counter_of_half_periods = 0;
    reg [31:0] gain_register = 0;
    reg signed [13:0] present_value_ADC = 0;
    reg signed [13:0] max_value_ADC = 0;
    reg signed [13:0] max_value_ADC_measurment = 0;


    always @(posedge clk)
    begin
        if (signal_freq == 0)
            begin
                delay_counter <= 0;
                reset <= 1;
                reset_DDS <= 0;
                counter_of_half_periods <= 0;
                CE <= 0;
                val_DDS <= 0;

            end
        else
            begin
                delay_counter <= delay_counter + 1;
                reset <= 0;
                reset_DDS <= 1;
                val_DDS <= 1;
                past_value <= present_value;
                present_value <= DDS_signal;
                past_phase <= present_phase;
                present_phase <= DDS_Phase;
                 if (delay_counter > delay_value)
                    begin
                       if(present_value[13] != past_value[13])
                           begin
                               counter_of_half_periods = counter_of_half_periods + 1;
                           end
                       if((counter_of_half_periods >= 1) & (counter_of_half_periods < number_of_half_periods))
                           begin
                               CE <= 1;
                           end
                       else
                           begin
                               CE <= 0;
                           end
                       end
                   else
                       begin
                           counter_of_half_periods <= 0;
            end
    end


    always @(posedge clk)
    begin
        if (CE == 1)
        begin
            if ($signed(Raw_ADC) > $signed(max_value_ADC))
                max_value_ADC <= Raw_ADC;
            else
                max_value_ADC <= max_value_ADC;
            end
        else
            if (signal_freq == 0)
            begin
                max_value_ADC <= 0;
            end
        end


    always @(posedge clk)
    begin
        if (CE == 1)
        begin
            if ($signed(Raw_ADC_measurment) > $signed(max_value_ADC_measurment))
                max_value_ADC_measurment <= Raw_ADC_measurment;
            else
                max_value_ADC_measurment <= max_value_ADC_measurment;
            end
        else
            if (signal_freq == 0)
            begin
                max_value_ADC_measurment <= 0;
            end
    end


    always @(posedge clk)
    begin
        if (valid == 1)
        begin
            gain_register <= gain;
        end
    end

    assign gain_r = gain_register;
    assign cl_en = CE;
    assign res = reset;
    assign resDDS = reset_DDS;
    assign DDS_valid = val_DDS;
    assign max_ADC = max_value_ADC;
    assign max_ADC_measurment = max_value_ADC_measurment;

endmodule