module random_gen(
  input  clk,
  input  rst_n,

  output logic [2:0] data
);

logic [31:0] data_internal;
wire feedback = data_internal[31]^data_internal[21]^data_internal[1]^data_internal[0];


always_ff @(posedge clk)
begin
  if (~rst_n)
    data_internal <= 32'h036f5b6c;
  else
    data_internal <= {data_internal[30:0], feedback};

end
always_comb
begin
if(data_internal[2:0] != 3'd0)
    data = data_internal[2:0];
else
    data = 3'd7;
end


endmodule