from migen.fhdl.std import *
from migen.fhdl import verilog


class FreqCounter(Module):
    # measured_sig: Signal to measure frequency
    # ref_clk: counts up to a gate_time number of cycles. It should be at least
    # twice as fast as the maximum frequency of the measured signal to avoid
    # samples being missed.
    # storage: should be an already instantiated (a)synchronous FIFO
    # posedge: If true, edge transitions from low to high count as a frequency event.
    # Otherwise, high to low transitions count.
    def __init__(self, measured_sig, ref_clk, gate_time=50000000, storage, posedge=True):
        self.clock_domains.cd_ref_clk = ClockDomain()

        event = Signal(1)
        prev_sig = Signal(1)
        gate_count = Signal(max=gate_time)
        freq_count = Signal(max=gate_time)
        storage_strobe = Signal(1)

        self.sync.ref_clk += [prev_sig.eq(measured_sig)]

        if posedge:
            self.comb += [event.eq(measured_sig & ~prev_sig)]
        else:
            self.comb += [event.eq(~measured_sig & prev_sig)]

        self.sync.ref_clk += [storage_strobe.eq(0),
            If(gate_count == gate_time - 1,
                gate_count.eq(0), storage_strobe.eq(1),
                freq_count.eq(0)).
            Else(
                # TODO: We should probably count an edge transition detected
                # on the leading edge just before the gate_count resets.
                If(event,
                    freq_count.eq(freq_count + 1))
                )]

# print(verilog.convert(Fre