module test_ep4ce6 (
    input wire clk,
    input wire a,
    input wire b,
    output reg y = 1'bx
  );

  reg [1023:0] x0;
  reg [1023:0] x1;
  reg [511:0] y0;
  reg [127:0] y1;
  reg [31:0] y2;
  reg [7:0] y3;
  reg [1:0] y4;
  integer i;

  always @* begin
    for (i = 0; i < 512; i = i + 1) begin
      y0[i] = (x0[i * 2] == x1[i * 2]) && (x0[i * 2 + 1] == x1[i * 2 + 1]);
    end
    for (i = 0; i < 128; i = i + 1) begin
      y1[i] = (y0[i * 4] && y0[i * 4 + 1] && y0[i * 4 + 2] && y0[i * 4 + 3]);
    end
    for (i = 0; i < 32; i = i + 1) begin
      y2[i] = (y1[i * 4] && y1[i * 4 + 1] && y1[i * 4 + 2] && y1[i * 4 + 3]);
    end
    for (i = 0; i < 8; i = i + 1) begin
      y3[i] = (y2[i * 4] && y2[i * 4 + 1] && y2[i * 4 + 2] && y2[i * 4 + 3]);
    end
    for (i = 0; i < 2; i = i + 1) begin
      y4[i] = (y3[i * 4] && y3[i * 4 + 1] && y3[i * 4 + 2] && y3[i * 4 + 3]);
    end
  end

  always @(posedge clk) begin
    x0 <= {x0[1022:0], a};
    x1 <= {x1[1022:0], b};
     //y <= x0 == x1; // А так оказывается чуть быстрее.
    y <= y4[0] || y4[1];
  end
endmodule