/----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2019  Clifford Wolf <[email protected]>           |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9+1706 (git sha1 2bda51ac, clang 6.0.0-1ubuntu2 -fPIC -Os)


-- Running command `debug read_verilog s27_newgen.v ; debug proc; dump; debug opt; debug fsm -nomap; debug fsm_export -o lol.kiss2; debug log -stdout loggger.txt' --

1. Executing Verilog-2005 frontend: s27_newgen.v
Parsing Verilog input from `s27_newgen.v' to AST representation.
Generating RTLIL representation for module `\ISCAS89_s27'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$s27_newgen.v:24$21 in module ISCAS89_s27.
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 0 assignments to connections.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\ISCAS89_s27.$proc$s27_newgen.v:24$21'.
     1/1: $0\state[2:0]

2.7. Executing PROC_DLATCH pass (convert process syncs to latches).

2.8. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\ISCAS89_s27.\state' using process `\ISCAS89_s27.$proc$s27_newgen.v:24$21'.
  created $dff cell `$procdff$26' with positive edge clock.

2.9. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\ISCAS89_s27.$proc$s27_newgen.v:24$21'.
Removing empty process `ISCAS89_s27.$proc$s27_newgen.v:24$21'.
Cleaned up 1 empty switch.

autoidx 27

attribute \cells_not_processed 1
attribute \src "s27_newgen.v:3"
module \ISCAS89_s27

  wire width 3 $procmux$24_Y

  wire $procmux$25_CMP

  attribute \src "s27_newgen.v:25"
  wire $eq$s27_newgen.v:25$22_Y

  attribute \src "s27_newgen.v:24"
  wire width 3 $0\state[2:0]

  attribute \src "s27_newgen.v:23"
  wire $and$s27_newgen.v:23$20_Y

  attribute \src "s27_newgen.v:23"
  wire $not$s27_newgen.v:23$19_Y

  attribute \src "s27_newgen.v:23"
  wire $not$s27_newgen.v:23$18_Y

  attribute \src "s27_newgen.v:22"
  wire $and$s27_newgen.v:22$17_Y

  attribute \src "s27_newgen.v:22"
  wire $not$s27_newgen.v:22$16_Y

  attribute \src "s27_newgen.v:22"
  wire $not$s27_newgen.v:22$15_Y

  attribute \src "s27_newgen.v:21"
  wire $and$s27_newgen.v:21$14_Y

  attribute \src "s27_newgen.v:21"
  wire $not$s27_newgen.v:21$13_Y

  attribute \src "s27_newgen.v:21"
  wire $not$s27_newgen.v:21$12_Y

  attribute \src "s27_newgen.v:20"
  wire $and$s27_newgen.v:20$11_Y

  attribute \src "s27_newgen.v:20"
  wire $not$s27_newgen.v:20$10_Y

  attribute \src "s27_newgen.v:20"
  wire $not$s27_newgen.v:20$9_Y

  attribute \src "s27_newgen.v:19"
  wire $or$s27_newgen.v:19$8_Y

  attribute \src "s27_newgen.v:19"
  wire $not$s27_newgen.v:19$7_Y

  attribute \src "s27_newgen.v:19"
  wire $not$s27_newgen.v:19$6_Y

  attribute \src "s27_newgen.v:18"
  wire $or$s27_newgen.v:18$5_Y

  attribute \src "s27_newgen.v:17"
  wire $or$s27_newgen.v:17$4_Y

  attribute \src "s27_newgen.v:16"
  wire $and$s27_newgen.v:16$3_Y

  attribute \src "s27_newgen.v:15"
  wire $not$s27_newgen.v:15$2_Y

  attribute \src "s27_newgen.v:14"
  wire $not$s27_newgen.v:14$1_Y

  attribute \src "s27_newgen.v:12"
  wire \n22

  attribute \src "s27_newgen.v:12"
  wire \n17

  attribute \src "s27_newgen.v:12"
  wire \n12

  attribute \src "s27_newgen.v:12"
  wire \new_G12_

  attribute \src "s27_newgen.v:12"
  wire \new_G9_

  attribute \src "s27_newgen.v:12"
  wire \new_G16_

  attribute \src "s27_newgen.v:12"
  wire \new_G15_

  attribute \src "s27_newgen.v:12"
  wire \new_G8_

  attribute \src "s27_newgen.v:12"
  wire \new_G14_

  attribute \src "s27_newgen.v:10"
  wire width 3 \state

  attribute \src "s27_newgen.v:9"
  wire \G7

  attribute \src "s27_newgen.v:9"
  wire \G6

  attribute \src "s27_newgen.v:9"
  wire \G5

  attribute \src "s27_newgen.v:8"
  wire output 6 \G17

  attribute \src "s27_newgen.v:7"
  wire input 5 \G3

  attribute \src "s27_newgen.v:7"
  wire input 4 \G2

  attribute \src "s27_newgen.v:7"
  wire input 3 \G1

  attribute \src "s27_newgen.v:7"
  wire input 2 \G0

  attribute \src "s27_newgen.v:6"
  wire input 7 \rst

  attribute \src "s27_newgen.v:6"
  wire input 1 \clk

  attribute \src "s27_newgen.v:24"
  cell $dff $procdff$26
    parameter \CLK_POLARITY 1'1
    parameter \WIDTH 3
    connect \CLK \clk
    connect \Q \state
    connect \D $procmux$24_Y
  end

  attribute \full_case 1
  attribute \src "s27_newgen.v:25"
  cell $mux $procmux$24
    parameter \WIDTH 3
    connect \Y $procmux$24_Y
    connect \S $procmux$25_CMP
    connect \B 3'000
    connect \A { \n12 \n17 \n22 }
  end

  attribute \src "s27_newgen.v:25"
  cell $eq $eq$s27_newgen.v:25$22
    parameter \Y_WIDTH 1
    parameter \B_WIDTH 1
    parameter \A_WIDTH 1
    parameter \B_SIGNED 0
    parameter \A_SIGNED 0
    connect \Y $eq$s27_newgen.v:25$22_Y
    connect \B 1'1
    connect \A \rst
  end

  attribute \src "s27_newgen.v:23"
  cell $and $and$s27_newgen.v:23$20
    parameter \Y_WIDTH 1
    parameter \B_WIDTH 1
    parameter \A_WIDTH 1
    parameter \B_SIGNED 0
    parameter \A_SIGNED 0
    connect \Y $and$s27_newgen.v:23$20_Y
    connect \B $not$s27_newgen.v:23$19_Y
    connect \A $not$s27_newgen.v:23$18_Y
  end

  attribute \src "s27_newgen.v:23"
  cell $not $not$s27_newgen.v:23$19
    parameter \Y_WIDTH 1
    parameter \A_WIDTH 1
    parameter \A_SIGNED 0
    connect \Y $not$s27_newgen.v:23$19_Y
    connect \A \new_G12_
  end

  attribute \src "s27_newgen.v:23"
  cell $not $not$s27_newgen.v:23$18
    parameter \Y_WIDTH 1
    parameter \A_WIDTH 1
    parameter \A_SIGNED 0
    connect \Y $not$s27_newgen.v:23$18_Y
    connect \A \G2
  end

  attribute \src "s27_newgen.v:22"
  cell $and $and$s27_newgen.v:22$17
    parameter \Y_WIDTH 1
    parameter \B_WIDTH 1
    parameter \A_WIDTH 1
    parameter \B_SIGNED 0
    parameter \A_SIGNED 0
    connect \Y $and$s27_newgen.v:22$17_Y
    connect \B $not$s27_newgen.v:22$16_Y
    connect \A $not$s27_newgen.v:22$15_Y
  end

  attribute \src "s27_newgen.v:22"
  cell $not $not$s27_newgen.v:22$16
    parameter \Y_WIDTH 1
    parameter \A_WIDTH 1
    parameter \A_SIGNED 0
    connect \Y $not$s27_newgen.v:22$16_Y
    connect \A \G7
  end

  attribute \src "s27_newgen.v:22"
  cell $not $not$s27_newgen.v:22$15
    parameter \Y_WIDTH 1
    parameter \A_WIDTH 1
    parameter \A_SIGNED 0
    connect \Y $not$s27_newgen.v:22$15_Y
    connect \A \G1
  end

  attribute \src "s27_newgen.v:21"
  cell $and $and$s27_newgen.v:21$14
    parameter \Y_WIDTH 1
    parameter \B_WIDTH 1
    parameter \A_WIDTH 1
    parameter \B_SIGNED 0
    parameter \A_SIGNED 0
    connect \Y $and$s27_newgen.v:21$14_Y
    connect \B $not$s27_newgen.v:21$13_Y
    connect \A $not$s27_newgen.v:21$12_Y
  end

  attribute \src "s27_newgen.v:21"
  cell $not $not$s27_newgen.v:21$13
    parameter \Y_WIDTH 1
    parameter \A_WIDTH 1
    parameter \A_SIGNED 0
    connect \Y $not$s27_newgen.v:21$13_Y
    connect \A \new_G9_
  end

  attribute \src "s27_newgen.v:21"
  cell $not $not$s27_newgen.v:21$12
    parameter \Y_WIDTH 1
    parameter \A_WIDTH 1
    parameter \A_SIGNED 0
    connect \Y $not$s27_newgen.v:21$12_Y
    connect \A \G5
  end

  attribute \src "s27_newgen.v:20"
  cell $and $and$s27_newgen.v:20$11
    parameter \Y_WIDTH 1
    parameter \B_WIDTH 1
    parameter \A_WIDTH 1
    parameter \B_SIGNED 0
    parameter \A_SIGNED 0
    connect \Y $and$s27_newgen.v:20$11_Y
    connect \B $not$s27_newgen.v:20$10_Y
    connect \A $not$s27_newgen.v:20$9_Y
  end

  attribute \src "s27_newgen.v:20"
  cell $not $not$s27_newgen.v:20$10
    parameter \Y_WIDTH 1
    parameter \A_WIDTH 1
    parameter \A_SIGNED 0
    connect \Y $not$s27_newgen.v:20$10_Y
    connect \A \n17
  end

  attribute \src "s27_newgen.v:20"
  cell $not $not$s27_newgen.v:20$9
    parameter \Y_WIDTH 1
    parameter \A_WIDTH 1
    parameter \A_SIGNED 0
    connect \Y $not$s27_newgen.v:20$9_Y
    connect \A \new_G14_
  end

  attribute \src "s27_newgen.v:19"
  cell $or $or$s27_newgen.v:19$8
    parameter \Y_WIDTH 1
    parameter \B_WIDTH 1
    parameter \A_WIDTH 1
    parameter \B_SIGNED 0
    parameter \A_SIGNED 0
    connect \Y $or$s27_newgen.v:19$8_Y
    connect \B $not$s27_newgen.v:19$7_Y
    connect \A $not$s27_newgen.v:19$6_Y
  end

  attribute \src "s27_newgen.v:19"
  cell $not $not$s27_newgen.v:19$7
    parameter \Y_WIDTH 1
    parameter \A_WIDTH 1
    parameter \A_SIGNED 0
    connect \Y $not$s27_newgen.v:19$7_Y
    connect \A \new_G15_
  end

  attribute \src "s27_newgen.v:19"
  cell $not $not$s27_newgen.v:19$6
    parameter \Y_WIDTH 1
    parameter \A_WIDTH 1
    parameter \A_SIGNED 0
    connect \Y $not$s27_newgen.v:19$6_Y
    connect \A \new_G16_
  end

  attribute \src "s27_newgen.v:18"
  cell $or $or$s27_newgen.v:18$5
    parameter \Y_WIDTH 1
    parameter \B_WIDTH 1
    parameter \A_WIDTH 1
    parameter \B_SIGNED 0
    parameter \A_SIGNED 0
    connect \Y $or$s27_newgen.v:18$5_Y
    connect \B \new_G8_
    connect \A \G3
  end

  attribute \src "s27_newgen.v:17"
  cell $or $or$s27_newgen.v:17$4
    parameter \Y_WIDTH 1
    parameter \B_WIDTH 1
    parameter \A_WIDTH 1
    parameter \B_SIGNED 0
    parameter \A_SIGNED 0
    connect \Y $or$s27_newgen.v:17$4_Y
    connect \B \new_G8_
    connect \A \new_G12_
  end

  attribute \src "s27_newgen.v:16"
  cell $and $and$s27_newgen.v:16$3
    parameter \Y_WIDTH 1
    parameter \B_WIDTH 1
    parameter \A_WIDTH 1
    parameter \B_SIGNED 0
    parameter \A_SIGNED 0
    connect \Y $and$s27_newgen.v:16$3_Y
    connect \B \G6
    connect \A \new_G14_
  end

  attribute \src "s27_newgen.v:15"
  cell $not $not$s27_newgen.v:15$2
    parameter \Y_WIDTH 1
    parameter \A_WIDTH 1
    parameter \A_SIGNED 0
    connect \Y $not$s27_newgen.v:15$2_Y
    connect \A \n17
  end

  attribute \src "s27_newgen.v:14"
  cell $not $not$s27_newgen.v:14$1
    parameter \Y_WIDTH 1
    parameter \A_WIDTH 1
    parameter \A_SIGNED 0
    connect \Y $not$s27_newgen.v:14$1_Y
    connect \A \G0
  end

  connect { \G5 \G6 \G7 } \state
  connect \new_G14_ $not$s27_newgen.v:14$1_Y
  connect \G17 $not$s27_newgen.v:15$2_Y
  connect \new_G8_ $and$s27_newgen.v:16$3_Y
  connect \new_G15_ $or$s27_newgen.v:17$4_Y
  connect \new_G16_ $or$s27_newgen.v:18$5_Y
  connect \new_G9_ $or$s27_newgen.v:19$8_Y
  connect \n12 $and$s27_newgen.v:20$11_Y
  connect \n17 $and$s27_newgen.v:21$14_Y
  connect \new_G12_ $and$s27_newgen.v:22$17_Y
  connect \n22 $and$s27_newgen.v:23$20_Y
  connect $procmux$25_CMP $eq$s27_newgen.v:25$22_Y
  connect $0\state[2:0] $procmux$24_Y
end

3. Executing OPT pass (performing simple optimizations).

3.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module ISCAS89_s27.
Replacing $not cell `$not$s27_newgen.v:20$9' (double_invert) in module `\ISCAS89_s27' with constant driver `$not$s27_newgen.v:20$9_Y = \G0'.
Replacing $eq cell `$eq$s27_newgen.v:25$22' (1) in module `\ISCAS89_s27' with constant driver `$eq$s27_newgen.v:25$22_Y = \rst'.

3.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\ISCAS89_s27'.
  Cell `$not$s27_newgen.v:15$2' is identical to cell `$not$s27_newgen.v:20$10'.
    Redirecting output \Y: $not$s27_newgen.v:15$2_Y = $not$s27_newgen.v:20$10_Y
    Removing $not cell `$not$s27_newgen.v:15$2' from module `\ISCAS89_s27'.
Removed a total of 1 cells.

3.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \ISCAS89_s27..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
    Root of a mux tree: $procmux$24 (pure)
  Analyzing evaluation results.
Removed 0 multiplexer ports.

3.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \ISCAS89_s27.
Performed a total of 0 changes.

3.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\ISCAS89_s27'.
Removed a total of 0 cells.

3.6. Executing OPT_RMDFF pass (remove dff with constant values).

3.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \ISCAS89_s27..
  removing unused non-port wire $not$s27_newgen.v:14$1_Y.
  removing unused non-port wire $not$s27_newgen.v:15$2_Y.
  removing unused non-port wire $and$s27_newgen.v:16$3_Y.
  removing unused non-port wire $or$s27_newgen.v:17$4_Y.
  removing unused non-port wire $or$s27_newgen.v:18$5_Y.
  removing unused non-port wire $or$s27_newgen.v:19$8_Y.
  removing unused non-port wire $not$s27_newgen.v:20$9_Y.
  removing unused non-port wire $not$s27_newgen.v:20$10_Y.
  removing unused non-port wire $and$s27_newgen.v:20$11_Y.
  removing unused non-port wire $and$s27_newgen.v:21$14_Y.
  removing unused non-port wire $and$s27_newgen.v:22$17_Y.
  removing unused non-port wire $and$s27_newgen.v:23$20_Y.
  removing unused non-port wire $eq$s27_newgen.v:25$22_Y.
  removing unused non-port wire $procmux$25_CMP.
  removing unused non-port wire $procmux$24_Y.
Removed 0 unused cells and 15 unused wires.

3.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module ISCAS89_s27.

3.9. Finished OPT passes. (There is nothing left to do.)

4. Executing FSM pass (extract and optimize FSM).

4.1. Executing FSM_DETECT pass (finding FSMs in design).

4.2. Executing FSM_EXTRACT pass (extracting FSM from design).

4.3. Executing FSM_OPT pass (simple optimizations of FSMs).

4.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \ISCAS89_s27..

4.5. Executing FSM_OPT pass (simple optimizations of FSMs).

4.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).

4.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

5. Executing FSM_EXPORT pass (exporting FSMs in KISS2 file format).
loggger.txt
loggger.txt

End of script. Logfile hash: 411a50581e, CPU: user 0.02s system 0.00s, MEM: 9.12 MB peak
Yosys 0.9+1706 (git sha1 2bda51ac, clang 6.0.0-1ubuntu2 -fPIC -Os)
Time spent: 31% 2x read_verilog (0 sec), 14% 2x opt_expr (0 sec), ...