`timescale 1ns / 1ps

module wrapper_uart_loader(
    input clk_i, // clock
    input uart_signal_i // data wire UART [RX]
    );


reg  [3:0] state;

wire  [7:0] uart_o;
wire        recieve_rdy_uart;
reg         resieve_rdy_present;
reg         resieve_rdy_present_2;
reg         uart_rdy_clr;

 uart CPA_uart(.clk_50m(clk_i),//пїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅ пїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅ UART
                .rx(uart_signal_i),
                .rdy(recieve_rdy_uart),
                .rdy_clr(uart_rdy_clr),
                .dout(uart_o));

    always @(posedge clk_i)
        begin
          if( ~reset_n_i ) uart_rdy_clr <= 1'b0;
          else if (recieve_rdy_uart && ~resieve_rdy_present) uart_rdy_clr <= 1'b1;
             else uart_rdy_clr <= 1'b0;
        end

    always @(posedge clk_i)
        begin
          if( ~reset_n_i ) resieve_rdy_present <= 1'b0;
          else resieve_rdy_present <= recieve_rdy_uart;
        end

    always @(posedge clk_i)
        begin
          if( ~reset_n_i ) resieve_rdy_present_2 <= 1'b0;
          else resieve_rdy_present_2 <= resieve_rdy_present;
        end
    // FSM


endmodule