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  1. `timescale 1ns / 1ps
  2.  
  3. module wrapper_uart_loader(
  4.     input clk_i, // clock
  5.     input uart_signal_i // data wire UART [RX]
  6.     );
  7.      
  8.  
  9. reg  [3:0] state;
  10.  
  11. wire  [7:0] uart_o;
  12. wire        recieve_rdy_uart;
  13. reg         resieve_rdy_present;
  14. reg         resieve_rdy_present_2;
  15. reg         uart_rdy_clr;
  16.  
  17.  uart CPA_uart(.clk_50m(clk_i),//пїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅ пїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅпїЅ UART
  18.                 .rx(uart_signal_i),
  19.                 .rdy(recieve_rdy_uart),
  20.                 .rdy_clr(uart_rdy_clr),
  21.                 .dout(uart_o));
  22.  
  23.     always @(posedge clk_i)
  24.         begin
  25.           if( ~reset_n_i ) uart_rdy_clr <= 1'b0;
  26.           else if (recieve_rdy_uart && ~resieve_rdy_present) uart_rdy_clr <= 1'b1;
  27.              else uart_rdy_clr <= 1'b0;
  28.         end
  29.                        
  30.     always @(posedge clk_i)
  31.         begin
  32.           if( ~reset_n_i ) resieve_rdy_present <= 1'b0;
  33.           else resieve_rdy_present <= recieve_rdy_uart;
  34.         end
  35.  
  36.     always @(posedge clk_i)
  37.         begin
  38.           if( ~reset_n_i ) resieve_rdy_present_2 <= 1'b0;
  39.           else resieve_rdy_present_2 <= resieve_rdy_present;
  40.         end
  41.     // FSM
  42.    
  43.    
  44. endmodule
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