.cseg
.ORG $000 rjmp init
.ORG $002 rjmp SUB_INT0
.ORG $004 rjmp SUB_INT1
.ORG $006 reti
.ORG $008 rjmp TIMER2_delay
.ORG $00A reti
.ORG $00C reti
.ORG $00E reti
.ORG $010 reti
.ORG $012 reti
.ORG $014 rjmp TIMER0_COMP
.ORG $016 reti
.ORG $018 reti
.ORG $01A reti
.ORG $01C reti
.ORG $01E reti
.ORG $020 reti
.ORG $022 reti
.ORG $024 reti
.ORG $026 reti
.ORG $028 reti

.def    num_of_mode = R21
.def    kol_in_timer = r1
.def    flag_200ms = r2
.def    flag_100ms = r3
.def    _200_ms = r4
.def    _100_ms = r5
.def    sreg1 = r6
.def    sreg2 = r7
.def    flag_minus = r8
.def    hb = r9
.def    ba = R10
.def    pa = R11
.def    dc = R12
.def    inc_or_dec = R13
.def    port_b = R14
.def    port_c = R15


.equ    first_mode = 0x01
.equ    second_mode = 0x02
.equ    b = 0x7C
.equ    h = 0x74
.equ    d = 0x5E
.equ    p = 0x73


mass:
    .db 0x3F, 0x06, 0x5B, 0x4F, 0x66, 0x6D, 0x7D, 0x07, 0x7F, 0x6F, 0x77, 0x7C, 0x39, 0x5E, 0x79, 0x71  ; 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, b, C, d, E, F

freq:
    .db 0x64, 0x32, 0x21, 0x19, 0x14, 0x10, 0x0e, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06, 0x05, 0x00  ; 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 раз в 2 сек

init:

    ser r16
    out DDRA, r16
    out DDRB, r16
    out DDRC, r16
    com r16
    out DDRD, r16

    ldi r16, high(RAMEND)
    out SPH, r16
    ldi r16, low(RAMEND)
    out SPL, r16

    ldi r16, 0x0A
    out MCUCR, r16
    ldi r16, 0xC0
    out GICR, r16

    ldi r17, b //b
    ldi r18, 0xF7 //a
    clr ba
    inc ba
    mov r19, ba
    clr hb
    inc hb
    clr pa
    inc pa
    clr dc
    clr port_b
    inc port_b
    clr port_c
    inc port_c
    clr inc_or_dec

    clr flag_minus

    ldi r20, 0x01 // bb = bc = 1
    ldi num_of_mode, first_mode //Номер режима

    ldi r26, 0x7f

    sei

/*-------------------main-----------------------------------*/
main:

    mov r19, ba
    mov r22, port_c
    mov r18, port_b

    in r16, SREG
    andi r16, 0xFE

    mov sreg1, r16
    mov sreg2, r16
    mov _100_ms, r16

    cpi num_of_mode, first_mode

    breq mode_1_a

    ldi r17, b // b
    ldi r18, 0xF7 //a
    rjmp mode_2_a

rjmp main

/*-------------------------------mode 1---------------------*/
mode_1_a:
    clr r2
    clr r3
    call timer_delay_ini
    ldi r25, 0x0f
    out TCCR2, r25
mode_1:
    mov r24, kol_in_timer
    cpi r24, 0x0b
    breq qwer
asd:
    call get_r24_for_b
    cp r24, r2
    breq qwerty
asd_2:
    cpi num_of_mode, second_mode
    breq main

rjmp mode_1

main_1:
    rjmp main

/*-------------------------------mode 2---------------------*/
mode_2_a:
    clr r2
    call timer_delay_ini
    ldi r25, 0x0f
    out TCCR2, r25
mode_2:

    call get_r22
    call get_r19

    mov r25, r2
    cpi r25, 0x0f
    brge print

hah:
    ldi r24, 0x01
    ldi r16, 0x01
    out PORTA, r16
    out PORTC, r22
    call delay
    lsl r16

    out PORTA, r16
    out PORTC, r19
    call delay
    lsl r16

    ldi r24, 0x01
    out PORTA, r16
    lsl r16
    out PORTC, r18
    call delay

    out PORTA, r16
    out PORTC, r17
    call delay

    cpi num_of_mode, first_mode
    breq main_1

    sbis PIND, 0
    rjmp next2
    inc inc_or_dec
    rjmp next_my

    next2:
    sbis PIND, 1
    rjmp next3
    inc inc_or_dec
    inc inc_or_dec

next_my:
    call incr_decr
next3:

rjmp mode_2


qwerty:
    out PORTA, r19
    out SREG, sreg2
    ror r19
    in r16, SREG
    mov sreg2, r16
    clr r2
rjmp asd_2


qwer:
    out PORTB, r18
    out PORTC, r22
    clr kol_in_timer
    call sreg_and_ror
    call left_or_right
rjmp asd

print:
    ldi r22, 0x00
    ldi r19, 0x00
    mov r25, r2
    cpi r25, 0x1e
    brge print_2
rjmp hah

print_2:
    clr r2
rjmp hah


/*-----------------------delay--------------------------------*/
delay:
    call timer_delay_ini
    ldi r25, 0x0d
    out TCCR2, r25
while:
   mov r28, kol_in_timer

   cp r28, r24
   breq hi
rjmp while
hi:
 clr r25
 out TCCR2, r25
 out TIMSK, r25
ret

/*-----------------------delay_1--------------------------------*
delay_1:

    call timer_delay_ini
while:
   mov r28, kol_in_timer

   cp r28, r24
   breq hi
rjmp while
hi:
 clr r25
 out TCCR2, r25
 out TIMSK, r25
ret */

/*---------------------------timer for button------------------------------*/
TIMER0_COMP:

  inc kol_in_timer
  mov r20, kol_in_timer

  cpi r20, 0x64
  breq each_200_ms

  cpi r20, 0xC8
  breq each_100_ms

  mov r20, flag_200ms
  cpi r20, 0x01
  breq each_200_ms

  mov r20, flag_100ms
  cpi r20, 0x01
  breq each_100_ms
  rjmp end_itr

  each_200_ms:

     inc _200_ms
     ldi r20, 0x01
     mov flag_200ms, r20
     clr r20
     mov flag_100ms, r20
     mov r20, _200_ms
     cpi r20, 0x0A
     breq obnul_200

  rjmp end_itr

   each_100_ms:

     inc _100_ms
     ldi r20, 0x01
     mov flag_100ms, r20
     clr r20
     mov flag_200ms, r20
     mov r20, _100_ms
     cpi r20, 0x05
     breq obnul_100
  rjmp end_itr

  obnul_200:
    clr r20
    mov _200_ms, r20
    cpi r17, b
    breq _1

    cpi r17, h
    breq _2

    cpi r17, p
    breq _4

    _1:
       mov r20, inc_or_dec
       cpi r20, 0x02
       breq the_dec
         inc ba
    rjmp end_itr

       the_dec:
       dec ba

    rjmp end_itr

    _2:
         call smth_hb
    rjmp end_itr

    _4:
        call smth_pa
    rjmp end_itr

  obnul_100:
    clr r20
    mov _100_ms, r20
    cpi r17, b
    breq _1

    cpi r17, h
    breq _2

    cpi r17, p
    breq _4

    end_itr:

reti

/*---------------------------timer for delay------------------------------*/
TIMER2_delay:

inc kol_in_timer
inc r2

reti

/*---------------------------Modes--------------------------------------*/

Mode__1:
ldi r17, b //b
ldi r18, 0xF7 //a
mov r19, ba
rjmp end

Mode__2:
ldi r17, h //h
ldi r18, 0xFC //b
mov r19, hb
rjmp end

Mode__3:
ldi r17, d //d
ldi r18, 0xB9 //c
mov r19, dc
rjmp end

Mode__4:
ldi r17, p //p
ldi r18, 0xF7 //a
mov r19, pa
rjmp end

/*-----------------------------------int0-------------------------*/
SUB_INT0:

    cpi num_of_mode, first_mode
    breq tw

    ldi num_of_mode, first_mode
    rjmp ed

    tw:
    ldi num_of_mode, second_mode

    ed:
reti

/*----------------------------------int1---------------------------*/
SUB_INT1:

    cpi r17, b
    breq Mode__2

    cpi r17, h
    breq Mode__3

    cpi r17, d
    breq Mode__4

    cpi r17, p
    breq Mode__1

    end:
reti

/*----------------------------Извлечение из массива нужного символа для последнего индикатора---------------------*/
get_r22:

ldi zl, low(mass<<1) ; загрузка в регистр ZL low адреса массива mass
ldi zh, high(mass<<1) ; загрузка в регистр ZH high адреса массива mass

call what_parametr
 mov r22, r19
 andi r22, 0x0F

 ldi r20, 0x00
 cycle:
   cp r20, r22
   breq get_elem
   adiw Z, 1
   inc r20
 rjmp cycle

 get_elem:
 lpm r0, Z ; загрузка данных в регистр r0
 mov r22, r0 ; чтение данных из регистра r0 в r16


ret

/*----------------------------Извлечение из массива нужного символа для предпоследнего индикатора---------------------*/
get_r19:

call what_parametr
 lsr r19
 lsr r19
 lsr r19
 lsr r19

 cpi r17, h
 breq check_minus

 rjmp without

check_minus:
 mov r20, flag_minus
 cpi r20, 0x01
 breq minus

 without:

ldi zl, low(mass<<1) ; загрузка в регистр ZL low адреса массива mass
ldi zh, high(mass<<1) ; загрузка в регистр ZH high адреса массива mass

 ldi r20, 0x00
 cycle2:
   cp r20, r19
   breq get_elem2
   adiw Z, 1
   inc r20
 rjmp cycle2

 get_elem2:
 lpm r0, z ; загрузка данных в регистр r0
 mov r19, r0 ; чтение данных из регистра r0 в r16
 rjmp to_end

 minus:
   ldi r19, 0x40

to_end:

ldi r24, 0x14
ret

/*----------------------------Иниациализация таймеров---------------------*/
timer_ini:

ldi r20, 0x00
mov kol_in_timer, r20
mov flag_200ms, r20
mov flag_100ms, r20
mov _200_ms, r20
mov _100_ms, r20
clr r16
out TCNT0, r16
ldi r16, 0x08
out TCCR0, r16
ldi r16, 0x9b
out OCR0, r16
ldi r16, 0x02
out TIMSK, r16
out TIFR, r16
ldi r16, 0x0D
out TCCR0, r16
ret

timer_delay_ini:

clr kol_in_timer
clr r25
out TCNT2, r25/*
ldi r25, 0x08
out TCCR2, r25*/
ldi r25, 0x9b
out OCR2, r25
ldi r25, 0x80
out TIMSK, r25
out TIFR, r25/*
ldi r25, 0x0f
out TCCR2, r25*/
ret
/*-------------------------------------------------------------------------------------------*/

inc_ba:

 mov r20, inc_or_dec
 cpi r20, 0x02
 breq decr
    inc ba
    call timer_ini

    wait2:          ;Цикл ожидания, пока нажата кнопка
         sbic PIND, 0 ;Если РВ2=1 (кнопка SB2 отпущена), пропустить след. строку
    rjmp wait2
    rjmp nul1

decr:
    dec ba
    call timer_ini

     wait7:          ;Цикл ожидания, пока нажата кнопка
         sbic PIND, 1 ;Если РВ2=1 (кнопка SB2 отпущена), пропустить след. строку
    rjmp wait7

nul1:
    clr r20
    out TCCR0, r20
    clr inc_or_dec
    out TIMSK, r20
    mov r19, ba
ret


inc_hb:

call smth_hb

  mov r20, inc_or_dec
 cpi r20, 0x02
 breq decr3
call timer_ini

 wait3:          ;Цикл ожидания, пока нажата кнопка
    sbic PIND, 0 ;Если РВ2=1 (кнопка SB2 отпущена), пропустить след. строку
rjmp wait3
rjmp stop

decr3:
 call timer_ini

 wait8:          ;Цикл ожидания, пока нажата кнопка
    sbic PIND, 1 ;Если РВ2=1 (кнопка SB2 отпущена), пропустить след. строку
rjmp wait8

stop:
clr r20
out TCCR0, r20
out TIMSK, r20
clr inc_or_dec
mov r19, hb

ret

inc_pa:

call smth_pa

  mov r20, inc_or_dec
 cpi r20, 0x02
 breq decr9
call timer_ini

 wait4:          ;Цикл ожидания, пока нажата кнопка
    sbic PIND, 0 ;Если РВ2=1 (кнопка SB2 отпущена), пропустить след. строку
rjmp wait4
rjmp stop2

decr9:
 call timer_ini

 wait10:          ;Цикл ожидания, пока нажата кнопка
    sbic PIND, 1 ;Если РВ2=1 (кнопка SB2 отпущена), пропустить след. строку
rjmp wait10

stop2:
clr r20
out TCCR0, r20
out TIMSK, r20
clr inc_or_dec
mov r19, pa

ret

/*-------------------какие числа выводим на индикаторы--------------------------*/
what_parametr:

cpi r17, b
breq Mode_one

cpi r17, h
breq Mode_two

cpi r17, d
breq Mode_three

cpi r17, p
breq Mode_four

Mode_one:
  mov r19, ba
rjmp bye

Mode_two:
  mov r19, hb
rjmp bye

Mode_three:
  mov r19, dc
rjmp bye

Mode_four:
  mov r19, pa
rjmp bye

bye:
ret

smth_hb:
 mov r20, inc_or_dec
 cpi r20, 0x02
 breq decr2

    mov r20, flag_minus
    cpi r20, 0x01
    breq minus_or_not

    mov r20, hb
    cpi r20, 0x04
    breq set_minus

    inc hb
    rjmp okeey

    minus_or_not:
        dec hb
        mov r20, hb
        cpi r20, 0x00
        breq nul_flag
    rjmp okeey

    set_minus:
        ldi r20, 0x01
        mov flag_minus, r20
    rjmp okeey

    nul_flag:
        clr flag_minus
    rjmp okeey

decr2:
   mov r20, flag_minus
    cpi r20, 0x01
    breq minus_or_not2

    mov r20, hb
    cpi r20, 0x00
    breq set_minus2

    dec hb
    rjmp okeey

    minus_or_not2:
        mov r20, hb
        cpi r20, 0x04
        breq nul_flag2
        inc hb
        mov r20, hb
    rjmp okeey

    set_minus2:
        ldi r20, 0x01
        inc hb
        mov flag_minus, r20
    rjmp okeey

    nul_flag2:
        clr flag_minus

   okeey:

ret

smth_pa:
  mov r20, inc_or_dec
 cpi r20, 0x02
 breq decr5

    mov r20, pa
    cpi r20, 0x0F
    breq get_one
    inc pa
    rjmp next_step
    get_one:
        clr pa
        inc pa
    rjmp next_step

decr5:

    mov r20, pa
    cpi r20, 0x00
    breq get_one2
    dec pa
    rjmp next_step
    get_one2:
        ldi r20, 0x0F
        mov pa, r20
    rjmp next_step

   next_step:

ret

incr_decr:

    cpi r17, b
    breq mode_ba

    cpi r17, h
    breq mode_hb

    cpi r17, p
    breq mode_pa

    mode_ba:
    call inc_ba
    rjmp next

    mode_hb:
    call inc_hb
    rjmp next

    mode_pa:
    call inc_pa
    rjmp next
next:

ret

left_or_right:

    mov r23, flag_minus
    cpi r23, 0x01
    breq left

    ldi r23, 0x00
    while_right:
         cp r23, hb
         breq exitt
         out SREG, _100_ms
         ror r18
         in r16, SREG
         mov _100_ms, r16
         inc r23
    rjmp while_right

    left:
      ldi r23, 0x00
      while_left:
         cp r23, hb
         breq exitt
         out SREG, _100_ms
         rol r18
         in r16, SREG
         mov _100_ms, r16
         inc r23
      rjmp while_left
   exitt:

ret

get_r24_for_b:

ldi zl, low(freq<<1) ; загрузка в регистр ZL low адреса массива mass
ldi zh, high(freq<<1) ; загрузка в регистр ZH high адреса массива mass

    mov r28, pa
    dec r28
    ldi r24, 0x00
    cycle72:
      cp r24, r28
      breq get_elem72
      adiw Z, 1
      inc r24
    rjmp cycle72

    get_elem72:
    lpm r0, z ; загрузка данных в регистр r0
    mov r24, r0 ;

ret

sreg_and_ror:

out SREG, sreg1
    ror r22
    in r16, SREG
    mov sreg1, r16

/*  out SREG, sreg2
    ror r19
    in r16, SREG
    mov sreg2, r16*/

ret