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Glaas2

RippleAdder

Jul 28th, 2022 (edited)
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  1. `timescale 1ns / 1ps
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company:
  4. // Engineer:
  5. //
  6. // Create Date:    11:03:25 07/28/2022
  7. // Design Name:
  8. // Module Name:    RippleAdder
  9. // Project Name:
  10. // Target Devices:
  11. // Tool versions:
  12. // Description:
  13. //
  14. // Dependencies: FullAdder
  15. //
  16. // Revision:
  17. // Revision 0.01 - File Created
  18. // Additional Comments:
  19. //
  20. //////////////////////////////////////////////////////////////////////////////////
  21. module RippleAdder(
  22.     input [3:0] A,
  23.     input [3:0] B,
  24.     output [3:0] SUM,
  25.     output C
  26.     );
  27.  
  28.     wire wirea, wireb, wirec;
  29.  
  30. //module FullAdder(input A, input B, input C, output SUM, output COUT);
  31. //1'b0 cadena de binarios de 1 bit
  32.  
  33. FullAdder FA1(A[0], B[0], 1'b0, SUM[0], wirea);
  34. FullAdder FA2(A[1], B[1],wirea, SUM[1], wireb);
  35. FullAdder FA3(A[2], B[2],wireb, SUM[2], wirec);  
  36. FullAdder FA4(A[3], B[4],wirec, SUM[3], C);
  37.  
  38. /*
  39. //// RippleAdder: testbench
  40. `timescale 1ns / 1ps
  41.  
  42. ////////////////////////////////////////////////////////////////////////////////
  43. // Company:
  44. // Engineer:
  45. //
  46. // Create Date:   11:19:51 07/28/2022
  47. // Design Name:   RippleAdder
  48. // Module Name:   C:/Users/F-307/Desktop/Nueva carpeta/RippleAdder/RippleAdder_tb.v
  49. // Project Name:  RippleAdder
  50. // Target Device:  
  51. // Tool versions:  
  52. // Description:
  53. //
  54. // Verilog Test Fixture created by ISE for module: RippleAdder
  55. //
  56. // Dependencies:
  57. //
  58. // Revision:
  59. // Revision 0.01 - File Created
  60. // Additional Comments:
  61. //
  62. ////////////////////////////////////////////////////////////////////////////////
  63.  
  64. module RippleAdder_tb;
  65.  
  66.     // Inputs
  67.     reg [3:0] A;
  68.     reg [3:0] B;
  69.  
  70.     // Outputs
  71.     wire [3:0] SUM;
  72.     wire C;
  73.  
  74.     // Instantiate the Unit Under Test (UUT)
  75.     RippleAdder uut (
  76.         .A(A),
  77.         .B(B),
  78.         .SUM(SUM),
  79.         .C(C)
  80.     );
  81.  
  82.     initial begin
  83.         // Initialize Inputs
  84.         A = 0;
  85.         B = 0;
  86.  
  87.         // Wait 100 ns for global reset to finish
  88.         #100;
  89.        
  90.         // Add stimulus here
  91.         A = 4'b0010;
  92.         B = 4'b1101;
  93.         #100;
  94.        
  95.         A=10;
  96.         B=1;
  97.         #100;
  98.  
  99. */
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