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- `timescale 1ns / 1ps
- //////////////////////////////////////////////////////////////////////////////////
- // Company:
- // Engineer:
- //
- // Create Date: 11:03:25 07/28/2022
- // Design Name:
- // Module Name: RippleAdder
- // Project Name:
- // Target Devices:
- // Tool versions:
- // Description:
- //
- // Dependencies: FullAdder
- //
- // Revision:
- // Revision 0.01 - File Created
- // Additional Comments:
- //
- //////////////////////////////////////////////////////////////////////////////////
- module RippleAdder(
- input [3:0] A,
- input [3:0] B,
- output [3:0] SUM,
- output C
- );
- wire wirea, wireb, wirec;
- //module FullAdder(input A, input B, input C, output SUM, output COUT);
- //1'b0 cadena de binarios de 1 bit
- FullAdder FA1(A[0], B[0], 1'b0, SUM[0], wirea);
- FullAdder FA2(A[1], B[1],wirea, SUM[1], wireb);
- FullAdder FA3(A[2], B[2],wireb, SUM[2], wirec);
- FullAdder FA4(A[3], B[4],wirec, SUM[3], C);
- /*
- //// RippleAdder: testbench
- `timescale 1ns / 1ps
- ////////////////////////////////////////////////////////////////////////////////
- // Company:
- // Engineer:
- //
- // Create Date: 11:19:51 07/28/2022
- // Design Name: RippleAdder
- // Module Name: C:/Users/F-307/Desktop/Nueva carpeta/RippleAdder/RippleAdder_tb.v
- // Project Name: RippleAdder
- // Target Device:
- // Tool versions:
- // Description:
- //
- // Verilog Test Fixture created by ISE for module: RippleAdder
- //
- // Dependencies:
- //
- // Revision:
- // Revision 0.01 - File Created
- // Additional Comments:
- //
- ////////////////////////////////////////////////////////////////////////////////
- module RippleAdder_tb;
- // Inputs
- reg [3:0] A;
- reg [3:0] B;
- // Outputs
- wire [3:0] SUM;
- wire C;
- // Instantiate the Unit Under Test (UUT)
- RippleAdder uut (
- .A(A),
- .B(B),
- .SUM(SUM),
- .C(C)
- );
- initial begin
- // Initialize Inputs
- A = 0;
- B = 0;
- // Wait 100 ns for global reset to finish
- #100;
- // Add stimulus here
- A = 4'b0010;
- B = 4'b1101;
- #100;
- A=10;
- B=1;
- #100;
- */
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