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  1. Receives n-bit value 'A' and returns lg(n)+1 bit value indicating the number of sequential ones starting from the LSB. eg '01001011' yields '010'
  2.  
  3.  
  4. A3A2A1A0|S2S1S0
  5. 0 0 0 0 |0 0 0
  6. 0 0 0 1 |0 0 1
  7. 0 0 1 1 |0 1 0
  8. 0 0 1 0 |0 0 0
  9.  
  10. 0 1 0 0 |0 0 0
  11. 0 1 0 1 |0 0 1
  12. 0 1 1 1 |0 1 1
  13. 0 1 1 0 |0 0 0
  14.  
  15. 1 1 0 0 |0 0 0
  16. 1 1 0 1 |0 0 1
  17. 1 1 1 1 |1 0 0
  18. 1 1 1 0 |0 0 0
  19.  
  20. 1 0 0 0 |0 0 0
  21. 1 0 0 1 |0 0 1
  22. 1 0 1 1 |0 1 1
  23. 1 0 1 0 |0 0 0
  24.  
  25. A3A2\A1A0 00 01 11 10
  26. 00 0 0 0 0
  27. 01 0 0 0 0
  28. 11 0 0 1 0
  29. 10 0 0 0 0
  30. S2 =A3A2A1A0
  31.  
  32. A3A2\A1A0 00 01 11 10
  33. 00 0 0 1 0
  34. 01 0 0 1 0
  35. 11 0 0 0 0
  36. 10 0 0 1 0
  37. S1 = A1A0(A3'+A2')
  38.  
  39. A3A2\A1A0 00 01 11 10
  40. 00 0 1 0 0
  41. 01 0 1 1 0
  42. 11 0 1 0 0
  43. 10 0 1 1 0
  44. S0 = A1'A0+A3'A2A0
  45.  
  46.  
  47. In|Out
  48. 1 |1
  49. 2 |2
  50. 3 |2
  51. 4 |3
  52. 8 |4
  53. 16 |5
  54. 32 |6
  55. 64 |7
  56.  
  57. \\\\\\\\\\\\\\\\
  58. 16 bit #
  59.  
  60. 1000 0000 0000 0000 //location of left-most bit
  61. |---8---| |---8---|
  62.  
  63. Bit 16 if left bank all ones and right bank all ones
  64.  
  65. 0111 1111 1000 0000
  66. |---8---| |---8---|
  67.  
  68. Bit 8 if left bank not all ones and right bank all ones
  69.  
  70. 0111 1000 0111 1000
  71. |---8---| |---8---|
  72.  
  73. Bit 4 if left bank not all ones and right bank all ones
  74.  
  75.  
  76. \\\\\\\\\\\\\\
  77. xxxx xxxx xxxx xxx0 00000 0
  78. xxxx xxxx xxxx xx01 00001 1
  79. xxxx xxxx xxxx x011 00010 2
  80. xxxx xxxx xxxx 0111 00011 3 xxx0
  81.  
  82. xxxx xxxx xxx0 1111 00100 4
  83. xxxx xxxx xx01 1111 00101 5
  84. xxxx xxxx x011 1111 00110 6
  85. xxxx xxxx 0111 1111 00111 7 xx01
  86.  
  87. xxxx xxx0 1111 1111 01000 8
  88. xxxx xx01 1111 1111 01001 9
  89. xxxx x011 1111 1111 01010 10
  90. xxxx 0111 1111 1111 01011 11 x011
  91.  
  92. xxx0 1111 1111 1111 01100 12
  93. xx01 1111 1111 1111 01101 13
  94. x011 1111 1111 1111 01110 14
  95. 0111 1111 1111 1111 01111 15 0111
  96.  
  97. 1111 1111 1111 1111 10000 16 1111
  98.  
  99. Anding blocks of four bits yields the same pattern as a four subsequence.
  100.  
  101. 1: Any sequential pair is 01 with all ones afterward
  102. ---------------------- Bit 1
  103. xxxx xxxx xxxx xx01 00001 1
  104. xxxx xxxx xxxx 0111 00011 3
  105.  
  106. xxxx xxxx xx01 1111 00101 5
  107. xxxx xxxx 0111 1111 00111 7
  108.  
  109. xxxx xx01 1111 1111 01001 9
  110. xxxx 0111 1111 1111 01011 11
  111.  
  112. xx01 1111 1111 1111 01101 13
  113. 0111 1111 1111 1111 01111 15
  114.  
  115. +++ Reduce via dc's
  116.  
  117. dc\ba 00 01 11 10
  118. 00 0 a 0 0
  119. 01 0 a b 0
  120. 11 0 a 0 0
  121. 10 0 a 0 0
  122. ---------------------- Bit 2
  123. xxxx xxxx xxxx x011 00010 2
  124. xxxx xxxx xxxx 0111 00011 3
  125.  
  126. xxxx xxxx x011 1111 00110 6
  127. xxxx xxxx 0111 1111 00111 7
  128.  
  129. xxxx x011 1111 1111 01010 10
  130. xxxx 0111 1111 1111 01011 11
  131.  
  132. x011 1111 1111 1111 01110 14
  133. 0111 1111 1111 1111 01111 15
  134.  
  135. ---------------------- Bit 4
  136. xxxx xxxx xxx0 1111 00100 4
  137. xxxx xxxx xx01 1111 00101 5
  138. xxxx xxxx x011 1111 00110 6
  139. xxxx xxxx 0111 1111 00111 7
  140.  
  141. xxx0 1111 1111 1111 01100 12
  142. xx01 1111 1111 1111 01101 13
  143. x011 1111 1111 1111 01110 14
  144. 0111 1111 1111 1111 01111 15
  145.  
  146. ---------------------- Bit 8
  147. xxxx xxx0 1111 1111 01000 8
  148. xxxx xx01 1111 1111 01001 9
  149. xxxx x011 1111 1111 01010 10
  150. xxxx 0111 1111 1111 01011 11
  151.  
  152. xxx0 1111 1111 1111 01100 12
  153. xx01 1111 1111 1111 01101 13
  154. x011 1111 1111 1111 01110 14
  155. 0111 1111 1111 1111 01111 15
  156.  
  157. ---------------------- Bit 16
  158. 1111 1111 1111 1111 10000 16
  159.  
  160. \\\\\ Solving the four case:
  161. xxx0 000 0
  162. xx01 001 1
  163. x011 010 2
  164. 0111 011 3 xxx0
  165. 1111 100
  166.  
  167. A3A2A1A0 | S2S1S0
  168. 0 0 0 0 | 0 0 0
  169. 0 0 0 1 | 0 0 1
  170. 0 0 1 1 | 0 1 0
  171. 0 0 1 0 | 0 0 0
  172.  
  173. 0 1 0 0 | 0 0 0
  174. 0 1 0 1 | 0 0 1
  175. 0 1 1 1 | 0 1 1
  176. 0 1 1 0 | 0 0 0
  177.  
  178. 1 1 0 0 | 0 0 0
  179. 1 1 0 1 | 0 0 1
  180. 1 1 1 1 | 1 0 0
  181. 1 1 1 0 | 0 0 0
  182.  
  183. 1 0 0 0 | 0 0 0
  184. 1 0 0 1 | 0 0 1
  185. 1 0 1 1 | 0 1 0
  186. 1 0 1 0 | 0 0 0
  187.  
  188. A3A2\A1A0 00 01 11 10
  189. 00 0 0 0 0
  190. 01 0 0 0 0
  191. 11 0 0 1 0
  192. 10 0 0 0 0
  193. S2 =A3A2A1A0
  194.  
  195. A3A2\A1A0 00 01 11 10
  196. 00 0 0 1 0
  197. 01 0 0 1 0
  198. 11 0 0 0 0
  199. 10 0 0 1 0
  200. S1 = A1A0(A3'+A2')
  201. = A1A0(A3A2)'
  202. = A3'A1A0+A2'A1A2
  203.  
  204. A3A2\A1A0 00 01 11 10
  205. 00 0 1 0 0
  206. 01 0 1 1 0
  207. 11 0 1 0 0
  208. 10 0 1 0 0
  209. S0 = A1'A0+A3'A2A0
  210. = (A1'+A3'A2)A0
  211.  
  212.  
  213. A3A2\A1A0 00 01 11 10
  214. 00 0 0 1 0
  215. 01 0 0 0 0
  216. 11 0 0 1 0
  217. 10 0 0 0 0
  218. Feed S2 into the next layer to compute the next pair of output bit
  219.  
  220.  
  221. /////////////Modular Design Of Fast Leading Zeros Counting Circuit
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