library ieee;
use ieee.std_logic_1164.all;

entity ripple_adder is
    port( input_1 : in STD_LOGIC_VECTOR(3 downto 0);
          input_2 : in STD_LOGIC_VECTOR(3 downto 0);
	  o_sum : out STD_LOGIC_VECTOR(3 downto 0);
	  o_carry : out STD_LOGIC);
end ripple_adder;
architecture STRUCTURAL of ripple_adder is
component full_adder is
    port( i_carry: in STD_LOGIC;
	  i_1 : in STD_LOGIC;
	  i_2 : in STD_LOGIC;
	  o_sum : out STD_LOGIC;
	  o_carry : out STD_LOGIC);
end component;
signal c0,c1,c2,c3 :std_logic ;
begin

FA1 : full_adder port map (i_carry => '0' ,
                           i_1=> input_1(0) ,
                           i_2 => input_2(0),
                           o_sum=> o_sum(0) ,
                           o_carry => c0     ) ;
FA2 : full_adder port map (
                           i_carry =>c0 ,
                           i_1=> input_1(1) ,
                           i_2 => input_2(1) ,
                           o_sum=> o_sum(1),
                           o_carry => c1 ) ;

FA3 : full_adder port map (i_carry =>c1 ,
                           i_1=> input_1(2) ,
                           i_2 => input_2(2) ,
                           o_sum=> o_sum(2) ,
                           o_carry => c2 ) ;

FA4 : full_adder port map (i_carry =>c2 ,
                           i_1=> input_1(3) ,
                           i_2 => input_2(3) ,
                           o_sum=> o_sum(3) ,
                           o_carry =>o_carry  ) ;


end STRUCTURAL;