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  1. /dts-v1/;
  2.  
  3. / {
  4. #address-cells = <0x01>;
  5. #size-cells = <0x01>;The rt2880 pinmux can only set the muxing of pin groups. Muxing indiviual pins
  6. is not supported. There is no pinconf support.
  7. compatible = "mediatek,linkit\0mediatek,mt7628an-soc";
  8. model = "MediaTek LinkIt Smart 7688";
  9.  
  10. cpus {
  11.  
  12. cpu@0 {
  13. compatible = "mips,mips24KEc";
  14. };
  15. };
  16.  
  17. chosen {
  18. bootargs = "console=ttyS0,115200";
  19. };
  20.  
  21. cpuintc@0 {
  22. compatible = "mti,cpu-interrupt-controller";
  23. interrupt-controller;
  24. #interrupt-cells = <0x01>;
  25. linux,phandle = <0x03>;
  26. phandle = <0x03>;
  27. };
  28.  
  29. palmbus@10000000 {
  30. compatible = "palmbus";
  31. reg = <0x10000000 0x200000>;
  32. ranges = <0x00 0x10000000 0x1fffff>;
  33. #address-cells = <0x01>;
  34. #size-cells = <0x01>;
  35.  
  36. sysc@0 {
  37. compatible = "ralink,mt7620a-sysc";
  38. reg = <0x00 0x100>;
  39. };
  40.  
  41. watchdog@120 {
  42. compatible = "ralink,mt7628an-wdt\0mtk,mt7621-wdt";
  43. reg = <0x120 0x10>;
  44. resets = <0x01 0x08>;
  45. reset-names = "wdt";
  46. interrupt-parent = <0x02>;
  47. interrupts = <0x18>;
  48. };
  49.  
  50. intc@200 {
  51. compatible = "ralink,mt7628an-intc\0ralink,rt2880-intc";
  52. reg = <0x200 0x100>;
  53. resets = <0x01 0x09>;
  54. reset-names = "intc";
  55. interrupt-controller;
  56. #interrupt-cells = <0x01>;
  57. interrupt-parent = <0x03>;
  58. interrupts = <0x02>;
  59. ralink,intc-registers = <0x9c 0xa0 0x6c 0xa4 0x80 0x78>;
  60. linux,phandle = <0x02>;
  61. phandle = <0x02>;
  62. };
  63.  
  64. memc@300 {
  65. compatible = "ralink,mt7620a-memc\0ralink,rt3050-memc";
  66. reg = <0x300 0x100>;
  67. resets = <0x01 0x14>;
  68. reset-names = "mc";
  69. interrupt-parent = <0x02>;
  70. interrupts = <0x03>;
  71. };
  72.  
  73. gpio@600 {
  74. #address-cells = <0x01>;
  75. #size-cells = <0x00>;
  76. compatible = "mtk,mt7628-gpio\0mtk,mt7621-gpio";
  77. reg = <0x600 0x100>;
  78. interrupt-parent = <0x02>;
  79. interrupts = <0x06>;
  80.  
  81. bank@0 {
  82. reg = <0x00>;
  83. compatible = "mtk,mt7621-gpio-bank";
  84. gpio-controller;
  85. #gpio-cells = <0x02>;
  86. linux,phandle = <0x08>;
  87. phandle = <0x08>;
  88. };
  89.  
  90. bank@1 {
  91. reg = <0x01>;
  92. compatible = "mtk,mt7621-gpio-bank";
  93. gpio-controller;
  94. #gpio-cells = <0x02>;
  95. linux,phandle = <0x12>;
  96. phandle = <0x12>;
  97. };
  98.  
  99. bank@2 {
  100. reg = <0x02>;
  101. compatible = "mtk,mt7621-gpio-bank";
  102. gpio-controller;
  103. #gpio-cells = <0x02>;
  104. };
  105. };
  106.  
  107. i2c@900 {
  108. compatible = "mediatek,mt7628-i2c";
  109. reg = <0x900 0x100>;
  110. resets = <0x01 0x10>;
  111. reset-names = "i2c";
  112. #address-cells = <0x01>;
  113. #size-cells = <0x00>;
  114. status = "disabled";
  115. pinctrl-names = "default";
  116. pinctrl-0 = <0x04>;
  117. };
  118.  
  119. i2s@a00 {
  120. compatible = "ralink,mt7620a-i2s";
  121. reg = <0xa00 0x100>;
  122. resets = <0x01 0x11>;
  123. reset-names = "i2s";
  124. interrupt-parent = <0x02>;
  125. interrupts = <0x0a>;
  126. dmas = <0x05 0x02 0x05 0x03>;
  127. dma-names = "tx\0rx";
  128. status = "disabled";
  129. };
  130.  
  131. spi@b00 {
  132. compatible = "ralink,mt7621-spi";
  133. reg = <0xb00 0x100>;
  134. resets = <0x01 0x12>;
  135. reset-names = "spi";
  136. #address-cells = <0x01>;
  137. #size-cells = <0x01>;
  138. pinctrl-names = "default";
  139. pinctrl-0 = <0x06 0x07 0x07>;
  140. status = "okay";
  141.  
  142. m25p80@0 {
  143. #address-cells = <0x01>;
  144. #size-cells = <0x01>;
  145. compatible = "mx25l6405d";
  146. reg = <0x00 0x00>;
  147. linux,modalias = "m25p80\0mx25l6405d";
  148. spi-max-frequency = <0x2625a00>;
  149. m25p,chunked-io = <0x1f>;
  150.  
  151. partition@0 {
  152. label = "u-boot";
  153. reg = <0x00 0x30000>;
  154. };
  155.  
  156. partition@30000 {
  157. label = "u-boot-env";
  158. reg = <0x30000 0x10000>;
  159. };
  160.  
  161. partition@40000 {
  162. label = "factory";
  163. reg = <0x40000 0x10000>;
  164. linux,phandle = <0x11>;
  165. phandle = <0x11>;
  166. };
  167.  
  168. partition@50000 {
  169. label = "firmware";
  170. reg = <0x50000 0x7b0000>;
  171. };
  172. };
  173.  
  174. ads7843@2 {
  175. #address-cells = <0x01>;
  176. #size-cells = <0x01>;
  177. compatible = "ti,ads7843";
  178. reg = <0x02 0x00>;
  179. spi-max-frequency = <0xea60>;
  180. pendown-gpio = <0x08 0x0b 0x00>;
  181. ti,x-min = [00 00];
  182. ti,x-max = [1f 40];
  183. ti,y-min = [00 00];
  184. ti,y-max = [12 c0];
  185. ti,x-plate-ohms = [00 28];
  186. ti,pressure-max = [3a 98];
  187. linux,wakeup;
  188. };
  189. };
  190.  
  191. uartlite@c00 {
  192. compatible = "ns16550a";
  193. reg = <0xc00 0x100>;
  194. reg-shift = <0x02>;
  195. reg-io-width = <0x04>;
  196. no-loopback-test;
  197. resets = <0x01 0x0c>;
  198. reset-names = "uartl";
  199. interrupt-parent = <0x02>;
  200. interrupts = <0x14>;
  201. pinctrl-names = "default";
  202. pinctrl-0 = <0x09>;
  203. };
  204.  
  205. uart1@d00 {
  206. compatible = "ns16550a";
  207. reg = <0xd00 0x100>;
  208. reg-shift = <0x02>;
  209. reg-io-width = <0x04>;
  210. no-loopback-test;
  211. resets = <0x01 0x13>;
  212. reset-names = "uart1";
  213. interrupt-parent = <0x02>;
  214. interrupts = <0x15>;
  215. pinctrl-names = "default";
  216. pinctrl-0 = <0x0a>;
  217. status = "disabled";
  218. };
  219.  
  220. uart2@e00 {
  221. compatible = "ns16550a";
  222. reg = <0xe00 0x100>;
  223. reg-shift = <0x02>;
  224. reg-io-width = <0x04>;
  225. no-loopback-test;
  226. resets = <0x01 0x14>;
  227. reset-names = "uart2";
  228. interrupt-parent = <0x02>;
  229. interrupts = <0x16>;
  230. pinctrl-names = "default";
  231. pinctrl-0 = <0x0b>;
  232. status = "okay";
  233. };
  234.  
  235. pwm@5000 {
  236. compatible = "mediatek,mt7628-pwm";
  237. reg = <0x5000 0x1000>;
  238. resets = <0x01 0x1f>;
  239. reset-names = "pwm";
  240. pinctrl-names = "default";
  241. pinctrl-0 = <0x0c 0x0d>;
  242. status = "okay";
  243. };
  244.  
  245. pcm@2000 {
  246. compatible = "ralink,mt7620a-pcm";
  247. reg = <0x2000 0x800>;
  248. resets = <0x01 0x0b>;
  249. reset-names = "pcm";
  250. interrupt-parent = <0x02>;
  251. interrupts = <0x04>;
  252. status = "disabled";
  253. };
  254.  
  255. gdma@2800 {
  256. compatible = "ralink,mt7620a-gdma\0ralink,rt2880-gdma";
  257. reg = <0x2800 0x800>;
  258. resets = <0x01 0x0e>;
  259. reset-names = "dma";
  260. interrupt-parent = <0x02>;
  261. interrupts = <0x07>;
  262. #dma-cells = <0x01>;
  263. #dma-channels = <0x10>;
  264. #dma-requests = <0x10>;
  265. status = "disabled";
  266. linux,phandle = <0x05>;
  267. phandle = <0x05>;
  268. };
  269. };
  270.  
  271. pinctrl {
  272. compatible = "ralink,rt2880-pinmux";
  273. pinctrl-names = "default";
  274. pinctrl-0 = <0x0e>;
  275.  
  276. pinctrl0 {
  277. linux,phandle = <0x0e>;
  278. phandle = <0x0e>;
  279.  
  280. gpio {
  281. ralink,group = "gpio";
  282. ralink,function = "gpio";
  283. };
  284.  
  285. pwm1 {
  286. ralink,group = "pwm1";
  287. ralink,function = "gpio";
  288. };
  289.  
  290. perst {
  291. ralink,group = "perst";
  292. ralink,function = "gpio";
  293. };
  294.  
  295. refclk {
  296. ralink,group = "refclk";
  297. ralink,function = "gpio";
  298. };
  299.  
  300. i2s {
  301. ralink,group = "i2s";
  302. ralink,function = "gpio";
  303. };
  304.  
  305. i2c {
  306. ralink,group = "i2c";
  307. ralink,function = "gpio";
  308. };
  309.  
  310. uart1 {
  311. ralink,group = "uart1";
  312. ralink,function = "gpio";
  313. };
  314.  
  315. spis {
  316. ralink,group = "spis";
  317. ralink,function = "gpio";
  318. };
  319.  
  320. wled_an {
  321. ralink,group = "wled_an";
  322. ralink,function = "wled_an";
  323. };
  324.  
  325. wdt {
  326. ralink,group = "wdt";
  327. ralink,function = "gpio";
  328. };
  329. };
  330.  
  331. spi {
  332. linux,phandle = <0x06>;
  333. phandle = <0x06>;
  334.  
  335. spi {
  336. ralink,group = "spi";
  337. ralink,function = "spi";
  338. };
  339. };
  340.  
  341. spi_cs1 {
  342. linux,phandle = <0x07>;
  343. phandle = <0x07>;
  344.  
  345. spi_cs1 {
  346. ralink,group = "spi cs1";
  347. ralink,function = "spi cs1";
  348. };
  349. };
  350.  
  351. i2c {
  352. linux,phandle = <0x04>;
  353. phandle = <0x04>;
  354.  
  355. i2c {
  356. ralink,group = "i2c";
  357. ralink,function = "i2c";
  358. };
  359. };
  360.  
  361. uartlite {
  362. linux,phandle = <0x09>;
  363. phandle = <0x09>;
  364.  
  365. uartlite {
  366. ralink,group = "uart0";
  367. ralink,function = "uart0";
  368. };
  369. };
  370.  
  371. uart1 {
  372. linux,phandle = <0x0a>;
  373. phandle = <0x0a>;
  374.  
  375. uart1 {
  376. ralink,group = "uart1";
  377. ralink,function = "uart1";
  378. };
  379. };
  380.  
  381. uart2 {
  382. linux,phandle = <0x0b>;
  383. phandle = <0x0b>;
  384.  
  385. uart2 {
  386. ralink,group = "uart2";
  387. ralink,function = "uart2";
  388. };
  389. };
  390.  
  391. sdxc {
  392. linux,phandle = <0x0f>;
  393. phandle = <0x0f>;
  394.  
  395. sdxc {
  396. ralink,group = "sdmode";
  397. ralink,function = "sdxc";
  398. };
  399. };
  400.  
  401. pwm0 {
  402. linux,phandle = <0x0c>;
  403. phandle = <0x0c>;
  404.  
  405. pwm0 {
  406. ralink,group = "pwm0";
  407. ralink,function = "pwm0";
  408. };
  409. };
  410.  
  411. pwm1 {
  412. linux,phandle = <0x0d>;
  413. phandle = <0x0d>;
  414.  
  415. pwm1 {
  416. ralink,group = "pwm1";
  417. ralink,function = "pwm1";
  418. };
  419. };
  420.  
  421. i2s {
  422.  
  423. i2s {
  424. ralink,group = "i2s";
  425. ralink,function = "pcm";
  426. };
  427. };
  428. };
  429.  
  430. rstctrl {
  431. compatible = "ralink,mt7620a-reset\0ralink,rt2880-reset";
  432. #reset-cells = <0x01>;
  433. linux,phandle = <0x01>;
  434. phandle = <0x01>;
  435. };
  436.  
  437. usbphy@10120000 {
  438. compatible = "ralink,mt7628an-usbphy\0ralink,mt7620a-usbphy";
  439. reg = <0x10120000 0x3e8>;
  440. #phy-cells = <0x01>;
  441. resets = <0x01 0x16 0x01 0x19>;
  442. reset-names = "host\0device";
  443. linux,phandle = <0x10>;
  444. phandle = <0x10>;
  445. };
  446.  
  447. sdhci@10130000 {
  448. compatible = "ralink,mt7620-sdhci";
  449. reg = <0x10130000 0xfa0>;
  450. interrupt-parent = <0x02>;
  451. interrupts = <0x0e>;
  452. pinctrl-names = "default";
  453. pinctrl-0 = <0x0f>;
  454. status = "okay";
  455. mediatek,cd-low;
  456. };
  457.  
  458. ehci@101c0000 {
  459. compatible = "ralink,rt3xxx-ehci";
  460. reg = <0x101c0000 0x1000>;
  461. phys = <0x10 0x01>;
  462. phy-names = "usb";
  463. interrupt-parent = <0x02>;
  464. interrupts = <0x12>;
  465. };
  466.  
  467. ohci@101c1000 {
  468. compatible = "ralink,rt3xxx-ohci";
  469. reg = <0x101c1000 0x1000>;
  470. phys = <0x10 0x01>;
  471. phy-names = "usb";
  472. interrupt-parent = <0x02>;
  473. interrupts = <0x12>;
  474. };
  475.  
  476. ethernet@10100000 {
  477. compatible = "ralink,rt5350-eth";
  478. reg = <0x10100000 0x2710>;
  479. interrupt-parent = <0x03>;
  480. interrupts = <0x05>;
  481. resets = <0x01 0x15 0x01 0x17>;
  482. reset-names = "fe\0esw";
  483. mtd-mac-address = <0x11 0x28>;
  484. };
  485.  
  486. esw@10110000 {
  487. compatible = "ralink,rt3050-esw";
  488. reg = <0x10110000 0x1f40>;
  489. resets = <0x01 0x17>;
  490. reset-names = "esw";
  491. interrupt-parent = <0x02>;
  492. interrupts = <0x11>;
  493. };
  494.  
  495. pcie@10140000 {
  496. compatible = "mediatek,mt7620-pci";
  497. reg = <0x10140000 0x100 0x10142000 0x100>;
  498. #address-cells = <0x03>;
  499. #size-cells = <0x02>;
  500. resets = <0x01 0x1a>;
  501. reset-names = "pcie0";
  502. interrupt-parent = <0x03>;
  503. interrupts = <0x04>;
  504. status = "disabled";
  505. device_type = "pci";
  506. bus-range = <0x00 0xff>;
  507. ranges = <0x2000000 0x00 0x00 0x20000000 0x00 0x10000000 0x1000000 0x00 0x00 0x10160000 0x00 0x10000>;
  508.  
  509. pcie-bridge {
  510. reg = <0x00 0x00 0x00 0x00 0x00>;
  511. #address-cells = <0x03>;
  512. #size-cells = <0x02>;
  513. device_type = "pci";
  514. };
  515. };
  516.  
  517. memory@0 {
  518. device_type = "memory";
  519. reg = <0x00 0x4000000>;
  520. };
  521.  
  522. gpio-keys-polled {
  523. compatible = "gpio-keys-polled";
  524. #address-cells = <0x01>;
  525. #size-cells = <0x00>;
  526. poll-interval = <0x14>;
  527.  
  528. wps {
  529. label = "reset";
  530. gpios = <0x12 0x06 0x01>;
  531. linux,code = <0x211>;
  532. };
  533. };
  534. }
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