`timescale 1ns / 1ps

module H2(start, rxrdy, reset, num12, dreq, clk, txrdy, rdy, incarca, depl, ddisp);
    input start, rxrdy, reset, num12, dreq, clk;
    output txrdy, rdy, incarca, depl, ddisp;
    reg txrdy, rdy, incarca, depl, ddisp;
    reg[2:0] s;

    always@(posedge clk or reset or start or dreq or rxrdy)
    begin
        if(reset)
            begin
                s = 0;
                txrdy = 0;
                rdy = 1;
                incarca = 0;
                depl = 0;
                ddisp = 0;
            end
        else
        begin
            if(s == 0)
            begin
                if(start)
                begin
                    s = 1;
                    rdy = 0;
                    incarca = 1;
                end
            end
            else if (s == 1)
            begin
                incarca = 0;
                ddisp = 1;
                s = 2;
            end
            else if (s == 2)
            begin
                if (dreq)
                begin
                    s = 3;
                    ddisp = 0;
                    depl = 1;
                end
            end
            else if (s == 3)
            begin
                s = 4;
            end
            else if (s == 4)
            begin
                if(num12)
                begin
                    s = 5;
                    txrdy = 1;
                    depl = 0;
                end
            end
            if (s == 5)
            begin
                depl = 0;
                if (rxrdy)
                begin
                    s = 0;
                    txrdy = 0;
                    rdy = 1;
                end
                else
                    s = 5;
            end
        end
    end


endmodule