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hanni76

sunxi h3 h5 dts

hanni76
Mar 12th, 2018
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  1. /*
  2. * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
  3. *
  4. * This file is dual-licensed: you can use it either under the terms
  5. * of the GPL or the X11 license, at your option. Note that this dual
  6. * licensing only applies to this file, and not this project as a
  7. * whole.
  8. *
  9. * a) This file is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation; either version 2 of the
  12. * License, or (at your option) any later version.
  13. *
  14. * This file is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * Or, alternatively,
  20. *
  21. * b) Permission is hereby granted, free of charge, to any person
  22. * obtaining a copy of this software and associated documentation
  23. * files (the "Software"), to deal in the Software without
  24. * restriction, including without limitation the rights to use,
  25. * copy, modify, merge, publish, distribute, sublicense, and/or
  26. * sell copies of the Software, and to permit persons to whom the
  27. * Software is furnished to do so, subject to the following
  28. * conditions:
  29. *
  30. * The above copyright notice and this permission notice shall be
  31. * included in all copies or substantial portions of the Software.
  32. *
  33. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35. * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37. * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38. * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40. * OTHER DEALINGS IN THE SOFTWARE.
  41. */
  42.  
  43. #include <dt-bindings/clock/sun8i-de2.h>
  44. #include <dt-bindings/clock/sun8i-h3-ccu.h>
  45. #include <dt-bindings/clock/sun8i-r-ccu.h>
  46. #include <dt-bindings/interrupt-controller/arm-gic.h>
  47. #include <dt-bindings/reset/sun8i-de2.h>
  48. #include <dt-bindings/reset/sun8i-h3-ccu.h>
  49. #include <dt-bindings/reset/sun8i-r-ccu.h>
  50. #include <dt-bindings/thermal/thermal.h>
  51.  
  52. / {
  53. interrupt-parent = <&gic>;
  54. #address-cells = <1>;
  55. #size-cells = <1>;
  56.  
  57. chosen {
  58. #address-cells = <1>;
  59. #size-cells = <1>;
  60. ranges;
  61.  
  62. framebuffer-hdmi {
  63. compatible = "allwinner,simple-framebuffer",
  64. "simple-framebuffer";
  65. allwinner,pipeline = "mixer0-lcd0-hdmi";
  66. clocks = <&display_clocks CLK_MIXER0>,
  67. <&ccu CLK_TCON0>, <&ccu CLK_HDMI>;
  68. status = "disabled";
  69. };
  70.  
  71. framebuffer-tve {
  72. compatible = "allwinner,simple-framebuffer",
  73. "simple-framebuffer";
  74. allwinner,pipeline = "mixer1-lcd1-tve";
  75. clocks = <&display_clocks CLK_MIXER1>,
  76. <&ccu CLK_TVE>;
  77. status = "disabled";
  78. };
  79. };
  80.  
  81. clocks {
  82. #address-cells = <1>;
  83. #size-cells = <1>;
  84. ranges;
  85.  
  86. osc24M: osc24M_clk {
  87. #clock-cells = <0>;
  88. compatible = "fixed-clock";
  89. clock-frequency = <24000000>;
  90. clock-output-names = "osc24M";
  91. };
  92.  
  93. osc32k: osc32k_clk {
  94. #clock-cells = <0>;
  95. compatible = "fixed-clock";
  96. clock-frequency = <32768>;
  97. clock-output-names = "osc32k";
  98. };
  99.  
  100. iosc: internal-osc-clk {
  101. #clock-cells = <0>;
  102. compatible = "fixed-clock";
  103. clock-frequency = <16000000>;
  104. clock-accuracy = <300000000>;
  105. clock-output-names = "iosc";
  106. };
  107. };
  108.  
  109. de: display-engine {
  110. compatible = "allwinner,sun8i-h3-display-engine";
  111. allwinner,pipelines = <&mixer0>;
  112. status = "disabled";
  113. };
  114.  
  115. soc {
  116. compatible = "simple-bus";
  117. #address-cells = <1>;
  118. #size-cells = <1>;
  119. ranges;
  120.  
  121. display_clocks: clock@1000000 {
  122. /* compatible is in per SoC .dtsi file */
  123. reg = <0x01000000 0x100000>;
  124. clocks = <&ccu CLK_DE>,
  125. <&ccu CLK_BUS_DE>;
  126. clock-names = "mod",
  127. "bus";
  128. resets = <&ccu RST_BUS_DE>;
  129. #clock-cells = <1>;
  130. #reset-cells = <1>;
  131. };
  132.  
  133. syscon: syscon@1c00000 {
  134. compatible = "allwinner,sun8i-h3-system-controller",
  135. "syscon";
  136. reg = <0x01c00000 0x1000>;
  137. };
  138.  
  139. dma: dma-controller@1c02000 {
  140. compatible = "allwinner,sun8i-h3-dma";
  141. reg = <0x01c02000 0x1000>;
  142. interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
  143. clocks = <&ccu CLK_BUS_DMA>;
  144. resets = <&ccu RST_BUS_DMA>;
  145. #dma-cells = <1>;
  146. };
  147.  
  148. ths: thermal-sensor@1c25000 {
  149. /* Compatible should be set on per-SoC basis */
  150. reg = <0x01c25000 0x400>;
  151. interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
  152. clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
  153. clock-names = "bus", "mod";
  154. resets = <&ccu RST_BUS_THS>;
  155. #io-channel-cells = <0>;
  156. };
  157.  
  158. mmc0: mmc@1c0f000 {
  159. /* compatible and clocks are in per SoC .dtsi file */
  160. reg = <0x01c0f000 0x1000>;
  161. resets = <&ccu RST_BUS_MMC0>;
  162. reset-names = "ahb";
  163. interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
  164. status = "disabled";
  165. #address-cells = <1>;
  166. #size-cells = <0>;
  167. };
  168.  
  169. mmc1: mmc@1c10000 {
  170. /* compatible and clocks are in per SoC .dtsi file */
  171. reg = <0x01c10000 0x1000>;
  172. resets = <&ccu RST_BUS_MMC1>;
  173. reset-names = "ahb";
  174. interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
  175. status = "disabled";
  176. #address-cells = <1>;
  177. #size-cells = <0>;
  178. };
  179.  
  180. mmc2: mmc@1c11000 {
  181. /* compatible and clocks are in per SoC .dtsi file */
  182. reg = <0x01c11000 0x1000>;
  183. resets = <&ccu RST_BUS_MMC2>;
  184. reset-names = "ahb";
  185. interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
  186. status = "disabled";
  187. #address-cells = <1>;
  188. #size-cells = <0>;
  189. };
  190.  
  191. mixer0: mixer@1100000 {
  192. compatible = "allwinner,sun8i-h3-de2-mixer-0";
  193. reg = <0x01100000 0x100000>;
  194. clocks = <&display_clocks CLK_BUS_MIXER0>,
  195. <&display_clocks CLK_MIXER0>;
  196. clock-names = "bus",
  197. "mod";
  198. resets = <&display_clocks RST_MIXER0>;
  199. status = "disabled";
  200.  
  201. ports {
  202. #address-cells = <1>;
  203. #size-cells = <0>;
  204.  
  205. mixer0_out: port@1 {
  206. #address-cells = <1>;
  207. #size-cells = <0>;
  208. reg = <1>;
  209.  
  210. mixer0_out_tcon0: endpoint@0 {
  211. reg = <0>;
  212. remote-endpoint = <&tcon0_in_mixer0>;
  213. };
  214. };
  215. };
  216. };
  217.  
  218. tcon0: lcd-controller@1c0c000 {
  219. compatible = "allwinner,sun8i-h3-tcon-tv",
  220. "allwinner,sun8i-a83t-tcon-tv";
  221. reg = <0x01c0c000 0x1000>;
  222. interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
  223. clocks = <&ccu CLK_BUS_TCON0>,
  224. <&ccu CLK_TCON0>;
  225. clock-names = "ahb",
  226. "tcon-ch1";
  227. resets = <&ccu RST_BUS_TCON0>;
  228. reset-names = "lcd";
  229. status = "disabled";
  230.  
  231. ports {
  232. #address-cells = <1>;
  233. #size-cells = <0>;
  234.  
  235. tcon0_in: port@0 {
  236. #address-cells = <1>;
  237. #size-cells = <0>;
  238. reg = <0>;
  239.  
  240. tcon0_in_mixer0: endpoint@0 {
  241. reg = <0>;
  242. remote-endpoint = <&mixer0_out_tcon0>;
  243. };
  244. };
  245.  
  246. tcon0_out: port@1 {
  247. #address-cells = <1>;
  248. #size-cells = <0>;
  249. reg = <1>;
  250.  
  251. tcon0_out_hdmi: endpoint@1 {
  252. reg = <1>;
  253. remote-endpoint = <&hdmi_in_tcon0>;
  254. };
  255. };
  256. };
  257. };
  258.  
  259. hdmi: hdmi@1ee0000 {
  260. compatible = "allwinner,sun8i-h3-dw-hdmi",
  261. "allwinner,sun8i-a83t-dw-hdmi";
  262. reg = <0x01ee0000 0x10000>;
  263. reg-io-width = <1>;
  264. interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
  265. clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>;
  266. clock-names = "iahb", "isfr";
  267. resets = <&ccu RST_BUS_HDMI1>;
  268. reset-names = "ctrl";
  269. phys = <&hdmi_phy>;
  270. phy-names = "hdmi-phy";
  271. status = "disabled";
  272.  
  273. ports {
  274. #address-cells = <1>;
  275. #size-cells = <0>;
  276.  
  277. hdmi_in: port@0 {
  278. #address-cells = <1>;
  279. #size-cells = <0>;
  280. reg = <0>;
  281.  
  282. hdmi_in_tcon0: endpoint@0 {
  283. reg = <0>;
  284. remote-endpoint = <&tcon0_out_hdmi>;
  285. };
  286. };
  287.  
  288. hdmi_out: port@1 {
  289. #address-cells = <1>;
  290. #size-cells = <0>;
  291. reg = <1>;
  292. };
  293. };
  294. };
  295.  
  296. hdmi_phy: hdmi-phy@1ef0000 {
  297. compatible = "allwinner,sun8i-h3-hdmi-phy";
  298. reg = <0x01ef0000 0x10000>;
  299. clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
  300. <&ccu CLK_HDMI>, <&ccu 6>;
  301. clock-names = "bus", "mod", "tmds", "pll-0";
  302. resets = <&ccu RST_BUS_HDMI0>;
  303. reset-names = "phy";
  304. #phy-cells = <0>;
  305. };
  306.  
  307. usb_otg: usb@1c19000 {
  308. compatible = "allwinner,sun8i-h3-musb";
  309. reg = <0x01c19000 0x400>;
  310. clocks = <&ccu CLK_BUS_OTG>;
  311. resets = <&ccu RST_BUS_OTG>;
  312. interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
  313. interrupt-names = "mc";
  314. phys = <&usbphy 0>;
  315. phy-names = "usb";
  316. extcon = <&usbphy 0>;
  317. status = "disabled";
  318. };
  319.  
  320. usbphy: phy@1c19400 {
  321. compatible = "allwinner,sun8i-h3-usb-phy";
  322. reg = <0x01c19400 0x2c>,
  323. <0x01c1a800 0x4>,
  324. <0x01c1b800 0x4>,
  325. <0x01c1c800 0x4>,
  326. <0x01c1d800 0x4>;
  327. reg-names = "phy_ctrl",
  328. "pmu0",
  329. "pmu1",
  330. "pmu2",
  331. "pmu3";
  332. clocks = <&ccu CLK_USB_PHY0>,
  333. <&ccu CLK_USB_PHY1>,
  334. <&ccu CLK_USB_PHY2>,
  335. <&ccu CLK_USB_PHY3>;
  336. clock-names = "usb0_phy",
  337. "usb1_phy",
  338. "usb2_phy",
  339. "usb3_phy";
  340. resets = <&ccu RST_USB_PHY0>,
  341. <&ccu RST_USB_PHY1>,
  342. <&ccu RST_USB_PHY2>,
  343. <&ccu RST_USB_PHY3>;
  344. reset-names = "usb0_reset",
  345. "usb1_reset",
  346. "usb2_reset",
  347. "usb3_reset";
  348. status = "disabled";
  349. #phy-cells = <1>;
  350. };
  351.  
  352. ehci0: usb@1c1a000 {
  353. compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
  354. reg = <0x01c1a000 0x100>;
  355. interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
  356. clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>;
  357. resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
  358. status = "disabled";
  359. };
  360.  
  361. ohci0: usb@1c1a400 {
  362. compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
  363. reg = <0x01c1a400 0x100>;
  364. interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
  365. clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>,
  366. <&ccu CLK_USB_OHCI0>;
  367. resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
  368. status = "disabled";
  369. };
  370.  
  371. ehci1: usb@1c1b000 {
  372. compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
  373. reg = <0x01c1b000 0x100>;
  374. interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
  375. clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>;
  376. resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
  377. phys = <&usbphy 1>;
  378. phy-names = "usb";
  379. status = "disabled";
  380. };
  381.  
  382. ohci1: usb@1c1b400 {
  383. compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
  384. reg = <0x01c1b400 0x100>;
  385. interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
  386. clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>,
  387. <&ccu CLK_USB_OHCI1>;
  388. resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
  389. phys = <&usbphy 1>;
  390. phy-names = "usb";
  391. status = "disabled";
  392. };
  393.  
  394. ehci2: usb@1c1c000 {
  395. compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
  396. reg = <0x01c1c000 0x100>;
  397. interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
  398. clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>;
  399. resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
  400. phys = <&usbphy 2>;
  401. phy-names = "usb";
  402. status = "disabled";
  403. };
  404.  
  405. ohci2: usb@1c1c400 {
  406. compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
  407. reg = <0x01c1c400 0x100>;
  408. interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
  409. clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>,
  410. <&ccu CLK_USB_OHCI2>;
  411. resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
  412. phys = <&usbphy 2>;
  413. phy-names = "usb";
  414. status = "disabled";
  415. };
  416.  
  417. ehci3: usb@1c1d000 {
  418. compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
  419. reg = <0x01c1d000 0x100>;
  420. interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
  421. clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>;
  422. resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
  423. phys = <&usbphy 3>;
  424. phy-names = "usb";
  425. status = "disabled";
  426. };
  427.  
  428. ohci3: usb@1c1d400 {
  429. compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
  430. reg = <0x01c1d400 0x100>;
  431. interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
  432. clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>,
  433. <&ccu CLK_USB_OHCI3>;
  434. resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
  435. phys = <&usbphy 3>;
  436. phy-names = "usb";
  437. status = "disabled";
  438. };
  439.  
  440. ccu: clock@1c20000 {
  441. /* compatible is in per SoC .dtsi file */
  442. reg = <0x01c20000 0x400>;
  443. clocks = <&osc24M>, <&osc32k>;
  444. clock-names = "hosc", "losc";
  445. #clock-cells = <1>;
  446. #reset-cells = <1>;
  447. };
  448.  
  449. pio: pinctrl@1c20800 {
  450. /* compatible is in per SoC .dtsi file */
  451. reg = <0x01c20800 0x400>;
  452. interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
  453. <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
  454. clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
  455. clock-names = "apb", "hosc", "losc";
  456. gpio-controller;
  457. #gpio-cells = <3>;
  458. interrupt-controller;
  459. #interrupt-cells = <3>;
  460.  
  461. emac_rgmii_pins: emac0 {
  462. pins = "PD0", "PD1", "PD2", "PD3", "PD4",
  463. "PD5", "PD7", "PD8", "PD9", "PD10",
  464. "PD12", "PD13", "PD15", "PD16", "PD17";
  465. function = "emac";
  466. drive-strength = <40>;
  467. };
  468.  
  469. i2c0_pins: i2c0 {
  470. pins = "PA11", "PA12";
  471. function = "i2c0";
  472. };
  473.  
  474. i2c1_pins: i2c1 {
  475. pins = "PA18", "PA19";
  476. function = "i2c1";
  477. };
  478.  
  479. i2c2_pins: i2c2 {
  480. pins = "PE12", "PE13";
  481. function = "i2c2";
  482. };
  483.  
  484. mmc0_pins_a: mmc0 {
  485. pins = "PF0", "PF1", "PF2", "PF3",
  486. "PF4", "PF5";
  487. function = "mmc0";
  488. drive-strength = <30>;
  489. bias-pull-up;
  490. };
  491.  
  492. mmc0_cd_pin: mmc0_cd_pin {
  493. pins = "PF6";
  494. function = "gpio_in";
  495. bias-pull-up;
  496. };
  497.  
  498. mmc1_pins_a: mmc1 {
  499. pins = "PG0", "PG1", "PG2", "PG3",
  500. "PG4", "PG5";
  501. function = "mmc1";
  502. drive-strength = <30>;
  503. bias-pull-up;
  504. };
  505.  
  506. mmc2_8bit_pins: mmc2_8bit {
  507. pins = "PC5", "PC6", "PC8",
  508. "PC9", "PC10", "PC11",
  509. "PC12", "PC13", "PC14",
  510. "PC15", "PC16";
  511. function = "mmc2";
  512. drive-strength = <30>;
  513. bias-pull-up;
  514. };
  515.  
  516. spdif_tx_pins_a: spdif {
  517. pins = "PA17";
  518. function = "spdif";
  519. };
  520.  
  521. spi0_pins: spi0 {
  522. pins = "PC0", "PC1", "PC2", "PC3";
  523. function = "spi0";
  524. };
  525.  
  526. spi1_pins: spi1 {
  527. pins = "PA15", "PA16", "PA14", "PA13";
  528. function = "spi1";
  529. };
  530.  
  531. uart0_pins_a: uart0 {
  532. pins = "PA4", "PA5";
  533. function = "uart0";
  534. };
  535.  
  536. uart1_pins: uart1 {
  537. pins = "PG6", "PG7";
  538. function = "uart1";
  539. };
  540.  
  541. uart1_rts_cts_pins: uart1_rts_cts {
  542. pins = "PG8", "PG9";
  543. function = "uart1";
  544. };
  545.  
  546. uart2_pins: uart2 {
  547. pins = "PA0", "PA1";
  548. function = "uart2";
  549. };
  550.  
  551. uart3_pins: uart3 {
  552. pins = "PA13", "PA14";
  553. function = "uart3";
  554. };
  555.  
  556. uart3_rts_cts_pins: uart3_rts_cts {
  557. pins = "PA15", "PA16";
  558. function = "uart3";
  559. };
  560. };
  561.  
  562. timer@1c20c00 {
  563. compatible = "allwinner,sun4i-a10-timer";
  564. reg = <0x01c20c00 0xa0>;
  565. interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
  566. <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
  567. clocks = <&osc24M>;
  568. };
  569.  
  570. emac: ethernet@1c30000 {
  571. compatible = "allwinner,sun8i-h3-emac";
  572. syscon = <&syscon>;
  573. reg = <0x01c30000 0x10000>;
  574. interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
  575. interrupt-names = "macirq";
  576. resets = <&ccu RST_BUS_EMAC>;
  577. reset-names = "stmmaceth";
  578. clocks = <&ccu CLK_BUS_EMAC>;
  579. clock-names = "stmmaceth";
  580. #address-cells = <1>;
  581. #size-cells = <0>;
  582. status = "disabled";
  583.  
  584. mdio: mdio {
  585. #address-cells = <1>;
  586. #size-cells = <0>;
  587. compatible = "snps,dwmac-mdio";
  588. };
  589.  
  590. mdio-mux {
  591. compatible = "allwinner,sun8i-h3-mdio-mux";
  592. #address-cells = <1>;
  593. #size-cells = <0>;
  594.  
  595. mdio-parent-bus = <&mdio>;
  596. /* Only one MDIO is usable at the time */
  597. internal_mdio: mdio@1 {
  598. compatible = "allwinner,sun8i-h3-mdio-internal";
  599. reg = <1>;
  600. #address-cells = <1>;
  601. #size-cells = <0>;
  602.  
  603. int_mii_phy: ethernet-phy@1 {
  604. compatible = "ethernet-phy-ieee802.3-c22";
  605. reg = <1>;
  606. clocks = <&ccu CLK_BUS_EPHY>;
  607. resets = <&ccu RST_BUS_EPHY>;
  608. };
  609. };
  610.  
  611. external_mdio: mdio@2 {
  612. reg = <2>;
  613. #address-cells = <1>;
  614. #size-cells = <0>;
  615. };
  616. };
  617. };
  618.  
  619. spi0: spi@1c68000 {
  620. compatible = "allwinner,sun8i-h3-spi";
  621. reg = <0x01c68000 0x1000>;
  622. interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
  623. clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
  624. clock-names = "ahb", "mod";
  625. dmas = <&dma 23>, <&dma 23>;
  626. dma-names = "rx", "tx";
  627. pinctrl-names = "default";
  628. pinctrl-0 = <&spi0_pins>;
  629. resets = <&ccu RST_BUS_SPI0>;
  630. status = "disabled";
  631. #address-cells = <1>;
  632. #size-cells = <0>;
  633. };
  634.  
  635. spi1: spi@1c69000 {
  636. compatible = "allwinner,sun8i-h3-spi";
  637. reg = <0x01c69000 0x1000>;
  638. interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
  639. clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
  640. clock-names = "ahb", "mod";
  641. dmas = <&dma 24>, <&dma 24>;
  642. dma-names = "rx", "tx";
  643. pinctrl-names = "default";
  644. pinctrl-0 = <&spi1_pins>;
  645. resets = <&ccu RST_BUS_SPI1>;
  646. status = "disabled";
  647. #address-cells = <1>;
  648. #size-cells = <0>;
  649. };
  650.  
  651. wdt0: watchdog@1c20ca0 {
  652. compatible = "allwinner,sun6i-a31-wdt";
  653. reg = <0x01c20ca0 0x20>;
  654. interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
  655. };
  656.  
  657. spdif: spdif@1c21000 {
  658. #sound-dai-cells = <0>;
  659. compatible = "allwinner,sun8i-h3-spdif";
  660. reg = <0x01c21000 0x400>;
  661. interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
  662. clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
  663. resets = <&ccu RST_BUS_SPDIF>;
  664. clock-names = "apb", "spdif";
  665. dmas = <&dma 2>;
  666. dma-names = "tx";
  667. status = "disabled";
  668. };
  669.  
  670. pwm: pwm@1c21400 {
  671. compatible = "allwinner,sun8i-h3-pwm";
  672. reg = <0x01c21400 0x8>;
  673. clocks = <&osc24M>;
  674. #pwm-cells = <3>;
  675. status = "disabled";
  676. };
  677.  
  678. i2s0: i2s@1c22000 {
  679. #sound-dai-cells = <0>;
  680. compatible = "allwinner,sun8i-h3-i2s";
  681. reg = <0x01c22000 0x400>;
  682. interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
  683. clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
  684. clock-names = "apb", "mod";
  685. dmas = <&dma 3>, <&dma 3>;
  686. resets = <&ccu RST_BUS_I2S0>;
  687. dma-names = "rx", "tx";
  688. status = "disabled";
  689. };
  690.  
  691. i2s1: i2s@1c22400 {
  692. #sound-dai-cells = <0>;
  693. compatible = "allwinner,sun8i-h3-i2s";
  694. reg = <0x01c22400 0x400>;
  695. interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
  696. clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
  697. clock-names = "apb", "mod";
  698. dmas = <&dma 4>, <&dma 4>;
  699. resets = <&ccu RST_BUS_I2S1>;
  700. dma-names = "rx", "tx";
  701. status = "disabled";
  702. };
  703.  
  704. codec: codec@1c22c00 {
  705. #sound-dai-cells = <0>;
  706. compatible = "allwinner,sun8i-h3-codec";
  707. reg = <0x01c22c00 0x400>;
  708. interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
  709. clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
  710. clock-names = "apb", "codec";
  711. resets = <&ccu RST_BUS_CODEC>;
  712. dmas = <&dma 15>, <&dma 15>;
  713. dma-names = "rx", "tx";
  714. allwinner,codec-analog-controls = <&codec_analog>;
  715. status = "disabled";
  716. };
  717.  
  718. uart0: serial@1c28000 {
  719. compatible = "snps,dw-apb-uart";
  720. reg = <0x01c28000 0x400>;
  721. interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
  722. reg-shift = <2>;
  723. reg-io-width = <4>;
  724. clocks = <&ccu CLK_BUS_UART0>;
  725. resets = <&ccu RST_BUS_UART0>;
  726. dmas = <&dma 6>, <&dma 6>;
  727. dma-names = "rx", "tx";
  728. status = "disabled";
  729. };
  730.  
  731. uart1: serial@1c28400 {
  732. compatible = "snps,dw-apb-uart";
  733. reg = <0x01c28400 0x400>;
  734. interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
  735. reg-shift = <2>;
  736. reg-io-width = <4>;
  737. clocks = <&ccu CLK_BUS_UART1>;
  738. resets = <&ccu RST_BUS_UART1>;
  739. dmas = <&dma 7>, <&dma 7>;
  740. dma-names = "rx", "tx";
  741. status = "disabled";
  742. };
  743.  
  744. uart2: serial@1c28800 {
  745. compatible = "snps,dw-apb-uart";
  746. reg = <0x01c28800 0x400>;
  747. interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
  748. reg-shift = <2>;
  749. reg-io-width = <4>;
  750. clocks = <&ccu CLK_BUS_UART2>;
  751. resets = <&ccu RST_BUS_UART2>;
  752. dmas = <&dma 8>, <&dma 8>;
  753. dma-names = "rx", "tx";
  754. status = "disabled";
  755. };
  756.  
  757. uart3: serial@1c28c00 {
  758. compatible = "snps,dw-apb-uart";
  759. reg = <0x01c28c00 0x400>;
  760. interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
  761. reg-shift = <2>;
  762. reg-io-width = <4>;
  763. clocks = <&ccu CLK_BUS_UART3>;
  764. resets = <&ccu RST_BUS_UART3>;
  765. dmas = <&dma 9>, <&dma 9>;
  766. dma-names = "rx", "tx";
  767. status = "disabled";
  768. };
  769.  
  770. i2c0: i2c@1c2ac00 {
  771. compatible = "allwinner,sun6i-a31-i2c";
  772. reg = <0x01c2ac00 0x400>;
  773. interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
  774. clocks = <&ccu CLK_BUS_I2C0>;
  775. resets = <&ccu RST_BUS_I2C0>;
  776. pinctrl-names = "default";
  777. pinctrl-0 = <&i2c0_pins>;
  778. status = "disabled";
  779. #address-cells = <1>;
  780. #size-cells = <0>;
  781. };
  782.  
  783. i2c1: i2c@1c2b000 {
  784. compatible = "allwinner,sun6i-a31-i2c";
  785. reg = <0x01c2b000 0x400>;
  786. interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
  787. clocks = <&ccu CLK_BUS_I2C1>;
  788. resets = <&ccu RST_BUS_I2C1>;
  789. pinctrl-names = "default";
  790. pinctrl-0 = <&i2c1_pins>;
  791. status = "disabled";
  792. #address-cells = <1>;
  793. #size-cells = <0>;
  794. };
  795.  
  796. i2c2: i2c@1c2b400 {
  797. compatible = "allwinner,sun6i-a31-i2c";
  798. reg = <0x01c2b400 0x400>;
  799. interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
  800. clocks = <&ccu CLK_BUS_I2C2>;
  801. resets = <&ccu RST_BUS_I2C2>;
  802. pinctrl-names = "default";
  803. pinctrl-0 = <&i2c2_pins>;
  804. status = "disabled";
  805. #address-cells = <1>;
  806. #size-cells = <0>;
  807. };
  808.  
  809. gic: interrupt-controller@1c81000 {
  810. compatible = "arm,gic-400";
  811. reg = <0x01c81000 0x1000>,
  812. <0x01c82000 0x2000>,
  813. <0x01c84000 0x2000>,
  814. <0x01c86000 0x2000>;
  815. interrupt-controller;
  816. #interrupt-cells = <3>;
  817. interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  818. };
  819.  
  820. rtc: rtc@1f00000 {
  821. compatible = "allwinner,sun6i-a31-rtc";
  822. reg = <0x01f00000 0x54>;
  823. interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
  824. <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
  825. };
  826.  
  827. r_ccu: clock@1f01400 {
  828. compatible = "allwinner,sun8i-h3-r-ccu";
  829. reg = <0x01f01400 0x100>;
  830. clocks = <&osc24M>, <&osc32k>, <&iosc>,
  831. <&ccu 9>;
  832. clock-names = "hosc", "losc", "iosc", "pll-periph";
  833. #clock-cells = <1>;
  834. #reset-cells = <1>;
  835. };
  836.  
  837. r_i2c: i2c@1f02400 {
  838. compatible = "allwinner,sun6i-a31-i2c";
  839. reg = <0x01f02400 0x400>;
  840. interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
  841. pinctrl-names = "default";
  842. pinctrl-0 = <&r_i2c_pins>;
  843. clocks = <&r_ccu CLK_APB0_I2C>;
  844. resets = <&r_ccu RST_APB0_I2C>;
  845. status = "disabled";
  846. #address-cells = <1>;
  847. #size-cells = <0>;
  848. };
  849.  
  850. codec_analog: codec-analog@1f015c0 {
  851. compatible = "allwinner,sun8i-h3-codec-analog";
  852. reg = <0x01f015c0 0x4>;
  853. };
  854.  
  855. ir: ir@1f02000 {
  856. compatible = "allwinner,sun5i-a13-ir";
  857. clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
  858. clock-names = "apb", "ir";
  859. resets = <&r_ccu RST_APB0_IR>;
  860. interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
  861. reg = <0x01f02000 0x40>;
  862. status = "disabled";
  863. };
  864.  
  865. r_pio: pinctrl@1f02c00 {
  866. compatible = "allwinner,sun8i-h3-r-pinctrl";
  867. reg = <0x01f02c00 0x400>;
  868. interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
  869. clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
  870. clock-names = "apb", "hosc", "losc";
  871. gpio-controller;
  872. #gpio-cells = <3>;
  873. interrupt-controller;
  874. #interrupt-cells = <3>;
  875.  
  876. ir_pins_a: ir {
  877. pins = "PL11";
  878. function = "s_cir_rx";
  879. };
  880.  
  881. r_i2c_pins: r-i2c {
  882. pins = "PL0", "PL1";
  883. function = "s_i2c";
  884. };
  885. };
  886. };
  887. };
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