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[wip:20200104] add Allwinner V3s support (2/2)

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  1. diff -uNpr sunxi.orig/files.sunxi sunxi/files.sunxi
  2. --- sunxi.orig/files.sunxi 2020-01-02 15:55:43.055618955 +0900
  3. +++ sunxi/files.sunxi 2020-01-04 11:19:05.708944696 +0900
  4. @@ -52,6 +52,11 @@ device sun8ih3rccu: sunxi_ccu
  5. attach sun8ih3rccu at fdt with sunxi_h3_r_ccu
  6. file arch/arm/sunxi/sun8i_h3_r_ccu.c sunxi_h3_r_ccu
  7.  
  8. +# CCU (V3s)
  9. +device sun8iv3sccu: sunxi_ccu
  10. +attach sun8iv3sccu at fdt with sunxi_v3s_ccu
  11. +file arch/arm/sunxi/sun8i_v3s_ccu.c sunxi_v3s_ccu
  12. +
  13. # CCU (A80)
  14. device sun9ia80ccu: sunxi_ccu
  15. attach sun9ia80ccu at fdt with sunxi_a80_ccu
  16. @@ -131,6 +136,7 @@ file arch/arm/sunxi/sun6i_a31_gpio.c su
  17. file arch/arm/sunxi/sun7i_a20_gpio.c sunxi_gpio & soc_sun7i_a20
  18. file arch/arm/sunxi/sun8i_a83t_gpio.c sunxi_gpio & soc_sun8i_a83t
  19. file arch/arm/sunxi/sun8i_h3_gpio.c sunxi_gpio & soc_sun8i_h3
  20. +file arch/arm/sunxi/sun8i_v3s_gpio.c sunxi_gpio & soc_sun8i_v3s
  21. file arch/arm/sunxi/sun9i_a80_gpio.c sunxi_gpio & soc_sun9i_a80
  22. file arch/arm/sunxi/sun50i_a64_gpio.c sunxi_gpio & soc_sun50i_a64
  23. file arch/arm/sunxi/sun50i_h6_gpio.c sunxi_gpio & soc_sun50i_h6
  24. @@ -383,6 +389,7 @@ defflag opt_soc.h SOC_SUN7I_A20: SOC_S
  25. defflag opt_soc.h SOC_SUN8I: SOC_SUNXI
  26. defflag opt_soc.h SOC_SUN8I_A83T: SOC_SUN8I, SOC_SUNXI_MC
  27. defflag opt_soc.h SOC_SUN8I_H3: SOC_SUN8I
  28. +defflag opt_soc.h SOC_SUN8I_V3S: SOC_SUN8I
  29. defflag opt_soc.h SOC_SUN9I: SOC_SUNXI
  30. defflag opt_soc.h SOC_SUN9I_A80: SOC_SUN9I, SOC_SUNXI_MC
  31. defflag opt_soc.h SOC_SUN50I: SOC_SUNXI
  32. diff -uNpr sunxi.orig/sun8i_v3s_ccu.c sunxi/sun8i_v3s_ccu.c
  33. --- sunxi.orig/sun8i_v3s_ccu.c 1970-01-01 09:00:00.000000000 +0900
  34. +++ sunxi/sun8i_v3s_ccu.c 2020-01-04 11:34:09.593703367 +0900
  35. @@ -0,0 +1,426 @@
  36. +/* $NetBSD: sun8i_v3s_ccu.c,v 1.5 2017/11/09 21:52:32 jmcneill Exp $ */
  37. +
  38. +/*-
  39. + * Copyright (c) 2017 Jared McNeill <[email protected]>
  40. + * All rights reserved.
  41. + *
  42. + * Redistribution and use in source and binary forms, with or without
  43. + * modification, are permitted provided that the following conditions
  44. + * are met:
  45. + * 1. Redistributions of source code must retain the above copyright
  46. + * notice, this list of conditions and the following disclaimer.
  47. + * 2. Redistributions in binary form must reproduce the above copyright
  48. + * notice, this list of conditions and the following disclaimer in the
  49. + * documentation and/or other materials provided with the distribution.
  50. + *
  51. + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  52. + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  53. + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  54. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  55. + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  56. + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  57. + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  58. + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  59. + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  60. + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  61. + * SUCH DAMAGE.
  62. + */
  63. +
  64. +#include <sys/cdefs.h>
  65. +
  66. +__KERNEL_RCSID(1, "$NetBSD: sun8i_v3s_ccu.c,v 1.5 2017/11/09 21:52:32 jmcneill Exp $");
  67. +
  68. +#include <sys/param.h>
  69. +#include <sys/bus.h>
  70. +#include <sys/device.h>
  71. +#include <sys/systm.h>
  72. +
  73. +#include <dev/fdt/fdtvar.h>
  74. +
  75. +#include <arm/sunxi/sunxi_ccu.h>
  76. +#include <arm/sunxi/sun8i_v3s_ccu.h>
  77. +
  78. +#define PLL_CPU_CTRL_REG 0x000
  79. +#define PLL_AUDIO_CTRL_REG 0x008
  80. +#define PLL_VIDEO_CTRL_REG 0x010
  81. +#define PLL_VE_CTRL_REG 0x018
  82. +#define PLL_DDR0_CTRL_REG 0x020
  83. +#define PLL_PERIPH0_CTRL_REG 0x028
  84. +#define PLL_ISP_CTRL_REG 0x02c
  85. +#define PLL_PERIPH1_CTRL_REG 0x044
  86. +#define PLL_DDR1_CTRL_REG 0x04c
  87. +#define CPU_AXI_CFG_REG 0x050
  88. +#define AHB1_APB1_CFG_REG 0x054
  89. +#define APB2_CFG_REG 0x058
  90. +#define AHB2_CFG_REG 0x05c
  91. +#define BUS_CLK_GATING_REG0 0x060
  92. +#define BUS_CLK_GATING_REG1 0x064
  93. +#define BUS_CLK_GATING_REG2 0x068
  94. +#define BUS_CLK_GATING_REG3 0x06c
  95. +#define BUS_CLK_GATING_REG4 0x070
  96. +#define SDMMC0_CLK_REG 0x088
  97. +#define SDMMC1_CLK_REG 0x08c
  98. +#define SDMMC2_CLK_REG 0x090
  99. +#define CE_CLK_REG 0x09c
  100. +#define SPI0_CLK_REG 0x0a0
  101. +#define USBPHY_CFG_REG 0x0cc
  102. +#define DRAM_CFG_REG 0x0f4
  103. +#define PLL_DDR1_CFG_REG 0x0f8
  104. +#define MBUS_RST_REG 0x0fc
  105. +#define DRAM_CLK_GATING_REG 0x100
  106. +#define DE_CLK_REG 0x104
  107. +#define TCON_CLK_REG 0x118
  108. +#define CSI_MISC_CLK_REG 0x130
  109. +#define CSI_CLK_REG 0x134
  110. +#define VE_CLK_REG 0x13c
  111. +#define AC_DIG_CLK_REG 0x140
  112. +#define AVS_CLK_REG 0x144
  113. +#define MBUS_CLK_REG 0x15c
  114. +#define MIPI_CSI_REG 0x16c
  115. +#define BUS_SOFT_RST_REG0 0x2c0
  116. +#define BUS_SOFT_RST_REG1 0x2c4
  117. +#define BUS_SOFT_RST_REG2 0x2c8
  118. +#define BUS_SOFT_RST_REG3 0x2d0
  119. +#define BUS_SOFT_RST_REG4 0x2d8
  120. +
  121. +static int sun8i_v3s_ccu_match(device_t, cfdata_t, void *);
  122. +static void sun8i_v3s_ccu_attach(device_t, device_t, void *);
  123. +
  124. +static const char * const compatible[] = {
  125. + "allwinner,sun8i-v3s-ccu",
  126. + NULL
  127. +};
  128. +
  129. +CFATTACH_DECL_NEW(sunxi_v3s_ccu, sizeof(struct sunxi_ccu_softc),
  130. + sun8i_v3s_ccu_match, sun8i_v3s_ccu_attach, NULL, NULL);
  131. +
  132. +static struct sunxi_ccu_reset sun8i_v3s_ccu_resets[] = {
  133. + SUNXI_CCU_RESET(V3S_RST_USB_PHY0, USBPHY_CFG_REG, 0),
  134. +
  135. + SUNXI_CCU_RESET(V3S_RST_MBUS, MBUS_RST_REG, 31),
  136. +
  137. + SUNXI_CCU_RESET(V3S_RST_BUS_CE, BUS_SOFT_RST_REG0, 5),
  138. + SUNXI_CCU_RESET(V3S_RST_BUS_DMA, BUS_SOFT_RST_REG0, 6),
  139. + SUNXI_CCU_RESET(V3S_RST_BUS_MMC0, BUS_SOFT_RST_REG0, 8),
  140. + SUNXI_CCU_RESET(V3S_RST_BUS_MMC1, BUS_SOFT_RST_REG0, 9),
  141. + SUNXI_CCU_RESET(V3S_RST_BUS_MMC2, BUS_SOFT_RST_REG0, 10),
  142. + SUNXI_CCU_RESET(V3S_RST_BUS_DRAM, BUS_SOFT_RST_REG0, 14),
  143. + SUNXI_CCU_RESET(V3S_RST_BUS_EMAC, BUS_SOFT_RST_REG0, 17),
  144. + SUNXI_CCU_RESET(V3S_RST_BUS_HSTIMER, BUS_SOFT_RST_REG0, 19),
  145. + SUNXI_CCU_RESET(V3S_RST_BUS_SPI0, BUS_SOFT_RST_REG0, 20),
  146. + SUNXI_CCU_RESET(V3S_RST_BUS_OTG, BUS_SOFT_RST_REG0, 24),
  147. + SUNXI_CCU_RESET(V3S_RST_BUS_EHCI0, BUS_SOFT_RST_REG0, 26),
  148. + SUNXI_CCU_RESET(V3S_RST_BUS_OHCI0, BUS_SOFT_RST_REG0, 29),
  149. +
  150. + SUNXI_CCU_RESET(V3S_RST_BUS_VE, BUS_SOFT_RST_REG1, 0),
  151. + SUNXI_CCU_RESET(V3S_RST_BUS_TCON0, BUS_SOFT_RST_REG1, 4),
  152. + SUNXI_CCU_RESET(V3S_RST_BUS_CSI, BUS_SOFT_RST_REG1, 8),
  153. + SUNXI_CCU_RESET(V3S_RST_BUS_DE, BUS_SOFT_RST_REG1, 12),
  154. + SUNXI_CCU_RESET(V3S_RST_BUS_DBG, BUS_SOFT_RST_REG1, 31),
  155. +
  156. + SUNXI_CCU_RESET(V3S_RST_BUS_EPHY, BUS_SOFT_RST_REG2, 2),
  157. +
  158. + SUNXI_CCU_RESET(V3S_RST_BUS_CODEC, BUS_SOFT_RST_REG3, 0),
  159. +
  160. + SUNXI_CCU_RESET(V3S_RST_BUS_I2C0, BUS_SOFT_RST_REG4, 0),
  161. + SUNXI_CCU_RESET(V3S_RST_BUS_I2C1, BUS_SOFT_RST_REG4, 1),
  162. + SUNXI_CCU_RESET(V3S_RST_BUS_UART0, BUS_SOFT_RST_REG4, 16),
  163. + SUNXI_CCU_RESET(V3S_RST_BUS_UART1, BUS_SOFT_RST_REG4, 17),
  164. + SUNXI_CCU_RESET(V3S_RST_BUS_UART2, BUS_SOFT_RST_REG4, 18),
  165. + /* V3S_RST_BUS_I2S0 is missing */
  166. +};
  167. +
  168. +static const char *ahb1_parents[] = { "losc", "hosc", "axi", "pll_periph0" };
  169. +static const char *ahb2_parents[] = { "ahb1", "pll_periph0" };
  170. +static const char *apb1_parents[] = { "ahb1" };
  171. +static const char *apb2_parents[] = { "losc", "hosc", "pll_periph0" };
  172. +static const char *mod_parents[] = { "hosc", "pll_periph0", "pll_periph1" };
  173. +static const char *de_parents[] = { "pll_video", "pll_periph0" };
  174. +static const char *tcon_parents[] = { "pll_video", "pll_periph0" };
  175. +
  176. +static const struct sunxi_ccu_nkmp_tbl sun8i_v3s_cpu_table[] = {
  177. + { 60000000, 9, 0, 0, 2 },
  178. + { 66000000, 10, 0, 0, 2 },
  179. + { 72000000, 11, 0, 0, 2 },
  180. + { 78000000, 12, 0, 0, 2 },
  181. + { 84000000, 13, 0, 0, 2 },
  182. + { 90000000, 14, 0, 0, 2 },
  183. + { 96000000, 15, 0, 0, 2 },
  184. + { 102000000, 16, 0, 0, 2 },
  185. + { 108000000, 17, 0, 0, 2 },
  186. + { 114000000, 18, 0, 0, 2 },
  187. + { 120000000, 9, 0, 0, 1 },
  188. + { 132000000, 10, 0, 0, 1 },
  189. + { 144000000, 11, 0, 0, 1 },
  190. + { 156000000, 12, 0, 0, 1 },
  191. + { 168000000, 13, 0, 0, 1 },
  192. + { 180000000, 14, 0, 0, 1 },
  193. + { 192000000, 15, 0, 0, 1 },
  194. + { 204000000, 16, 0, 0, 1 },
  195. + { 216000000, 17, 0, 0, 1 },
  196. + { 228000000, 18, 0, 0, 1 },
  197. + { 240000000, 9, 0, 0, 0 },
  198. + { 264000000, 10, 0, 0, 0 },
  199. + { 288000000, 11, 0, 0, 0 },
  200. + { 312000000, 12, 0, 0, 0 },
  201. + { 336000000, 13, 0, 0, 0 },
  202. + { 360000000, 14, 0, 0, 0 },
  203. + { 384000000, 15, 0, 0, 0 },
  204. + { 408000000, 16, 0, 0, 0 },
  205. + { 432000000, 17, 0, 0, 0 },
  206. + { 456000000, 18, 0, 0, 0 },
  207. + { 480000000, 19, 0, 0, 0 },
  208. + { 504000000, 20, 0, 0, 0 },
  209. + { 528000000, 21, 0, 0, 0 },
  210. + { 552000000, 22, 0, 0, 0 },
  211. + { 576000000, 23, 0, 0, 0 },
  212. + { 600000000, 24, 0, 0, 0 },
  213. + { 624000000, 25, 0, 0, 0 },
  214. + { 648000000, 26, 0, 0, 0 },
  215. + { 672000000, 27, 0, 0, 0 },
  216. + { 696000000, 28, 0, 0, 0 },
  217. + { 720000000, 29, 0, 0, 0 },
  218. + { 768000000, 15, 1, 0, 0 },
  219. + { 792000000, 10, 2, 0, 0 },
  220. + { 816000000, 16, 1, 0, 0 },
  221. + { 864000000, 17, 1, 0, 0 },
  222. + { 912000000, 18, 1, 0, 0 },
  223. + { 936000000, 12, 2, 0, 0 },
  224. + { 960000000, 19, 1, 0, 0 },
  225. + { 1008000000, 20, 1, 0, 0 },
  226. + { 1056000000, 21, 1, 0, 0 },
  227. + { 1080000000, 14, 2, 0, 0 },
  228. + { 1104000000, 22, 1, 0, 0 },
  229. + { 1152000000, 23, 1, 0, 0 },
  230. + { 1200000000, 24, 1, 0, 0 },
  231. + { 1224000000, 16, 2, 0, 0 },
  232. + { 1248000000, 25, 1, 0, 0 },
  233. + { 1296000000, 26, 1, 0, 0 },
  234. + { 1344000000, 27, 1, 0, 0 },
  235. + { 1368000000, 18, 2, 0, 0 },
  236. + { 1392000000, 28, 1, 0, 0 },
  237. + { 1440000000, 29, 1, 0, 0 },
  238. + { 1512000000, 20, 2, 0, 0 },
  239. + { 1536000000, 15, 3, 0, 0 },
  240. + { 1584000000, 21, 2, 0, 0 },
  241. + { 1632000000, 16, 3, 0, 0 },
  242. + { 1656000000, 22, 2, 0, 0 },
  243. + { 1728000000, 23, 2, 0, 0 },
  244. + { 1800000000, 24, 2, 0, 0 },
  245. + { 1824000000, 18, 3, 0, 0 },
  246. + { 1872000000, 25, 2, 0, 0 },
  247. + { 0 }
  248. +};
  249. +
  250. +static const struct sunxi_ccu_nkmp_tbl sun8i_v3s_ac_dig_table[] = {
  251. + { 24576000, 13, 0, 0, 13 },
  252. + { 0 }
  253. +};
  254. +
  255. +static struct sunxi_ccu_clk sun8i_v3s_ccu_clks[] = {
  256. + SUNXI_CCU_NKMP_TABLE(V3S_CLK_CPU, "pll_cpu", "hosc",
  257. + PLL_CPU_CTRL_REG, /* reg */
  258. + __BITS(12,8), /* n */
  259. + __BITS(5,4), /* k */
  260. + __BITS(1,0), /* m */
  261. + __BITS(17,16), /* p */
  262. + __BIT(31), /* enable */
  263. + __BIT(28), /* lock */
  264. + sun8i_v3s_cpu_table, /* table */
  265. + SUNXI_CCU_NKMP_SCALE_CLOCK | SUNXI_CCU_NKMP_FACTOR_P_POW2),
  266. +
  267. + SUNXI_CCU_NKMP(V3S_CLK_PLL_PERIPH0, "pll_periph0", "hosc",
  268. + PLL_PERIPH0_CTRL_REG, /* reg */
  269. + __BITS(12,8), /* n */
  270. + __BITS(5,4), /* k */
  271. + 0, /* m */
  272. + __BITS(17,16), /* p */
  273. + __BIT(31), /* enable */
  274. + SUNXI_CCU_NKMP_DIVIDE_BY_TWO),
  275. +
  276. + SUNXI_CCU_FRACTIONAL(V3S_CLK_PLL_VIDEO, "pll_video", "hosc",
  277. + PLL_VIDEO_CTRL_REG, /* reg */
  278. + __BITS(14,8), /* m */
  279. + 16, /* m_min */
  280. + 50, /* m_max */
  281. + __BIT(24), /* div_en */
  282. + __BIT(25), /* frac_sel */
  283. + 270000000, 297000000, /* frac values */
  284. + __BITS(3,0), /* prediv */
  285. + 4, /* prediv_val */
  286. + __BIT(31), /* enable */
  287. + SUNXI_CCU_FRACTIONAL_PLUSONE | SUNXI_CCU_FRACTIONAL_SET_ENABLE),
  288. +
  289. + SUNXI_CCU_NKMP_TABLE(V3S_CLK_PLL_AUDIO_BASE, "pll_audio", "hosc",
  290. + PLL_AUDIO_CTRL_REG, /* reg */
  291. + __BITS(14,8), /* n */
  292. + 0, /* k */
  293. + __BITS(4,0), /* m */
  294. + __BITS(19,16), /* p */
  295. + __BIT(31), /* enable */
  296. + __BIT(28), /* lock */
  297. + sun8i_v3s_ac_dig_table, /* table */
  298. + 0),
  299. +
  300. + SUNXI_CCU_PREDIV(V3S_CLK_AHB1, "ahb1", ahb1_parents,
  301. + AHB1_APB1_CFG_REG, /* reg */
  302. + __BITS(7,6), /* prediv */
  303. + __BIT(3), /* prediv_sel */
  304. + __BITS(5,4), /* div */
  305. + __BITS(13,12), /* sel */
  306. + SUNXI_CCU_PREDIV_POWER_OF_TWO),
  307. +
  308. + SUNXI_CCU_PREDIV(V3S_CLK_AHB2, "ahb2", ahb2_parents,
  309. + AHB2_CFG_REG, /* reg */
  310. + 0, /* prediv */
  311. + __BIT(1), /* prediv_sel */
  312. + 0, /* div */
  313. + __BITS(1,0), /* sel */
  314. + SUNXI_CCU_PREDIV_DIVIDE_BY_TWO),
  315. +
  316. + SUNXI_CCU_DIV(V3S_CLK_APB1, "apb1", apb1_parents,
  317. + AHB1_APB1_CFG_REG, /* reg */
  318. + __BITS(9,8), /* div */
  319. + 0, /* sel */
  320. + SUNXI_CCU_DIV_POWER_OF_TWO|SUNXI_CCU_DIV_ZERO_IS_ONE),
  321. +
  322. + SUNXI_CCU_NM(V3S_CLK_APB2, "apb2", apb2_parents,
  323. + APB2_CFG_REG, /* reg */
  324. + __BITS(17,16), /* n */
  325. + __BITS(4,0), /* m */
  326. + __BITS(25,24), /* sel */
  327. + 0, /* enable */
  328. + SUNXI_CCU_NM_POWER_OF_TWO),
  329. +
  330. + SUNXI_CCU_DIV_GATE(V3S_CLK_DE, "de", de_parents,
  331. + DE_CLK_REG, /* reg */
  332. + __BITS(3,0), /* div */
  333. + __BITS(26,24), /* sel */
  334. + __BIT(31), /* enable */
  335. + 0),
  336. +
  337. + SUNXI_CCU_NM(V3S_CLK_MMC0, "mmc0", mod_parents,
  338. + SDMMC0_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31),
  339. + SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN),
  340. + SUNXI_CCU_PHASE(V3S_CLK_MMC0_SAMPLE, "mmc0_sample", "mmc0",
  341. + SDMMC0_CLK_REG, __BITS(22,20)),
  342. + SUNXI_CCU_PHASE(V3S_CLK_MMC0_OUTPUT, "mmc0_output", "mmc0",
  343. + SDMMC0_CLK_REG, __BITS(10,8)),
  344. + SUNXI_CCU_NM(V3S_CLK_MMC1, "mmc1", mod_parents,
  345. + SDMMC1_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31),
  346. + SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN),
  347. + SUNXI_CCU_PHASE(V3S_CLK_MMC1_SAMPLE, "mmc1_sample", "mmc1",
  348. + SDMMC1_CLK_REG, __BITS(22,20)),
  349. + SUNXI_CCU_PHASE(V3S_CLK_MMC1_OUTPUT, "mmc1_output", "mmc1",
  350. + SDMMC1_CLK_REG, __BITS(10,8)),
  351. + SUNXI_CCU_NM(V3S_CLK_MMC2, "mmc2", mod_parents,
  352. + SDMMC2_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31),
  353. + SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN),
  354. + SUNXI_CCU_PHASE(V3S_CLK_MMC2_SAMPLE, "mmc2_sample", "mmc2",
  355. + SDMMC2_CLK_REG, __BITS(22,20)),
  356. + SUNXI_CCU_PHASE(V3S_CLK_MMC2_OUTPUT, "mmc2_output", "mmc2",
  357. + SDMMC2_CLK_REG, __BITS(10,8)),
  358. +
  359. + SUNXI_CCU_NM(V3S_CLK_SPI0, "spi0", mod_parents,
  360. + SPI0_CLK_REG, /* reg */
  361. + __BITS(17,16), /* n */
  362. + __BITS(3,0), /* m */
  363. + __BITS(25,24), /* sel */
  364. + __BIT(31), /* enable */
  365. + SUNXI_CCU_NM_ROUND_DOWN),
  366. +
  367. + SUNXI_CCU_GATE(V3S_CLK_AC_DIG, "ac_dig", "pll_audio",
  368. + AC_DIG_CLK_REG, 31),
  369. +
  370. + SUNXI_CCU_DIV_GATE(V3S_CLK_TCON0, "tcon", tcon_parents,
  371. + TCON_CLK_REG, /* reg */
  372. + __BITS(3,0), /* div */
  373. + __BITS(26,24), /* sel */
  374. + __BIT(31), /* enable */
  375. + 0),
  376. +
  377. + SUNXI_CCU_GATE(V3S_CLK_BUS_DMA, "bus-dma", "ahb1",
  378. + BUS_CLK_GATING_REG0, 6),
  379. + SUNXI_CCU_GATE(V3S_CLK_BUS_MMC0, "bus-mmc0", "ahb1",
  380. + BUS_CLK_GATING_REG0, 8),
  381. + SUNXI_CCU_GATE(V3S_CLK_BUS_MMC1, "bus-mmc1", "ahb1",
  382. + BUS_CLK_GATING_REG0, 9),
  383. + SUNXI_CCU_GATE(V3S_CLK_BUS_MMC2, "bus-mmc2", "ahb1",
  384. + BUS_CLK_GATING_REG0, 10),
  385. + SUNXI_CCU_GATE(V3S_CLK_BUS_EMAC, "bus-emac", "ahb2",
  386. + BUS_CLK_GATING_REG0, 17),
  387. + SUNXI_CCU_GATE(V3S_CLK_BUS_SPI0, "bus-spi0", "ahb1",
  388. + BUS_CLK_GATING_REG0, 20),
  389. + SUNXI_CCU_GATE(V3S_CLK_BUS_OTG, "bus-otg", "ahb2",
  390. + BUS_CLK_GATING_REG0, 24),
  391. + SUNXI_CCU_GATE(V3S_CLK_BUS_EHCI0, "bus-ehci", "ahb2",
  392. + BUS_CLK_GATING_REG0, 26),
  393. + SUNXI_CCU_GATE(V3S_CLK_BUS_OHCI0, "bus-ohci", "ahb2",
  394. + BUS_CLK_GATING_REG0, 29),
  395. +
  396. + SUNXI_CCU_GATE(V3S_CLK_BUS_VE, "bus-ve", "ahb1",
  397. + BUS_CLK_GATING_REG1, 0),
  398. + SUNXI_CCU_GATE(V3S_CLK_BUS_TCON0, "bus-tcon", "ahb1",
  399. + BUS_CLK_GATING_REG1, 4),
  400. + SUNXI_CCU_GATE(V3S_CLK_BUS_CSI, "bus-csi", "ahb1",
  401. + BUS_CLK_GATING_REG1, 8),
  402. + SUNXI_CCU_GATE(V3S_CLK_BUS_DE, "bus-de", "ahb1",
  403. + BUS_CLK_GATING_REG1, 12),
  404. +
  405. + SUNXI_CCU_GATE(V3S_CLK_BUS_CODEC, "bus-codec", "apb1",
  406. + BUS_CLK_GATING_REG2, 0),
  407. + SUNXI_CCU_GATE(V3S_CLK_BUS_PIO, "bus-pio", "apb1",
  408. + BUS_CLK_GATING_REG2, 5),
  409. +
  410. + SUNXI_CCU_GATE(V3S_CLK_BUS_I2C0, "bus-i2c0", "apb2",
  411. + BUS_CLK_GATING_REG3, 0),
  412. + SUNXI_CCU_GATE(V3S_CLK_BUS_I2C1, "bus-i2c1", "apb2",
  413. + BUS_CLK_GATING_REG3, 1),
  414. + SUNXI_CCU_GATE(V3S_CLK_BUS_UART0, "bus-uart0", "apb2",
  415. + BUS_CLK_GATING_REG3, 16),
  416. + SUNXI_CCU_GATE(V3S_CLK_BUS_UART1, "bus-uart1", "apb2",
  417. + BUS_CLK_GATING_REG3, 17),
  418. + SUNXI_CCU_GATE(V3S_CLK_BUS_UART2, "bus-uart2", "apb2",
  419. + BUS_CLK_GATING_REG3, 18),
  420. +
  421. + SUNXI_CCU_GATE(V3S_CLK_BUS_EPHY, "bus-ephy", "ahb1",
  422. + BUS_CLK_GATING_REG4, 0),
  423. +
  424. + SUNXI_CCU_GATE(V3S_CLK_USB_PHY0, "usb-phy0", "hosc",
  425. + USBPHY_CFG_REG, 8),
  426. + SUNXI_CCU_GATE(V3S_CLK_USB_OHCI0, "usb-ohci", "hosc",
  427. + USBPHY_CFG_REG, 16),
  428. +};
  429. +
  430. +static int
  431. +sun8i_v3s_ccu_match(device_t parent, cfdata_t cf, void *aux)
  432. +{
  433. + struct fdt_attach_args * const faa = aux;
  434. +
  435. + return of_match_compatible(faa->faa_phandle, compatible);
  436. +}
  437. +
  438. +static void
  439. +sun8i_v3s_ccu_attach(device_t parent, device_t self, void *aux)
  440. +{
  441. + struct sunxi_ccu_softc * const sc = device_private(self);
  442. + struct fdt_attach_args * const faa = aux;
  443. +
  444. + sc->sc_dev = self;
  445. + sc->sc_phandle = faa->faa_phandle;
  446. + sc->sc_bst = faa->faa_bst;
  447. +
  448. + sc->sc_resets = sun8i_v3s_ccu_resets;
  449. + sc->sc_nresets = __arraycount(sun8i_v3s_ccu_resets);
  450. +
  451. + sc->sc_clks = sun8i_v3s_ccu_clks;
  452. + sc->sc_nclks = __arraycount(sun8i_v3s_ccu_clks);
  453. +
  454. + if (sunxi_ccu_attach(sc) != 0)
  455. + return;
  456. +
  457. + aprint_naive("\n");
  458. + aprint_normal(": V3s CCU\n");
  459. +
  460. + sunxi_ccu_print(sc);
  461. +}
  462. diff -uNpr sunxi.orig/sun8i_v3s_ccu.h sunxi/sun8i_v3s_ccu.h
  463. --- sunxi.orig/sun8i_v3s_ccu.h 1970-01-01 09:00:00.000000000 +0900
  464. +++ sunxi/sun8i_v3s_ccu.h 2020-01-04 11:16:24.151811569 +0900
  465. @@ -0,0 +1,124 @@
  466. +/* $NetBSD: sun8i_v3s_ccu.h,v 1.1 2017/08/25 00:07:03 jmcneill Exp $ */
  467. +
  468. +/*-
  469. + * Copyright (c) 2017 Jared McNeill <[email protected]>
  470. + * All rights reserved.
  471. + *
  472. + * Redistribution and use in source and binary forms, with or without
  473. + * modification, are permitted provided that the following conditions
  474. + * are met:
  475. + * 1. Redistributions of source code must retain the above copyright
  476. + * notice, this list of conditions and the following disclaimer.
  477. + * 2. Redistributions in binary form must reproduce the above copyright
  478. + * notice, this list of conditions and the following disclaimer in the
  479. + * documentation and/or other materials provided with the distribution.
  480. + *
  481. + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  482. + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  483. + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  484. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  485. + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  486. + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  487. + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  488. + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  489. + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  490. + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  491. + * SUCH DAMAGE.
  492. + */
  493. +
  494. +#ifndef _SUN8I_V3S_CCU_H
  495. +#define _SUN8I_V3S_CCU_H
  496. +
  497. +#define V3S_RST_USB_PHY0 0
  498. +#define V3S_RST_MBUS 1
  499. +#define V3S_RST_BUS_CE 5
  500. +#define V3S_RST_BUS_DMA 6
  501. +#define V3S_RST_BUS_MMC0 7
  502. +#define V3S_RST_BUS_MMC1 8
  503. +#define V3S_RST_BUS_MMC2 9
  504. +#define V3S_RST_BUS_DRAM 11
  505. +#define V3S_RST_BUS_EMAC 12
  506. +#define V3S_RST_BUS_HSTIMER 14
  507. +#define V3S_RST_BUS_SPI0 15
  508. +#define V3S_RST_BUS_OTG 17
  509. +#define V3S_RST_BUS_EHCI0 18
  510. +#define V3S_RST_BUS_OHCI0 22
  511. +#define V3S_RST_BUS_VE 26
  512. +#define V3S_RST_BUS_TCON0 27
  513. +#define V3S_RST_BUS_CSI 30
  514. +#define V3S_RST_BUS_DE 34
  515. +#define V3S_RST_BUS_DBG 38
  516. +#define V3S_RST_BUS_EPHY 39
  517. +#define V3S_RST_BUS_CODEC 40
  518. +#define V3S_RST_BUS_I2C0 46
  519. +#define V3S_RST_BUS_I2C1 47
  520. +#define V3S_RST_BUS_UART0 49
  521. +#define V3S_RST_BUS_UART1 50
  522. +#define V3S_RST_BUS_UART2 51
  523. +#define V3S_RST_BUS_I2S0 52
  524. +
  525. +#define V3S_CLK_PLL_CPU 0 /*XXX*/
  526. +#define V3S_CLK_PLL_AUDIO_BASE 1 /*XXX*/
  527. +#define V3S_CLK_PLL_VIDEO 6 /*XXX*/
  528. +#define V3S_CLK_PLL_PERIPH0 8 /*XXX*/
  529. +#define V3S_CLK_CPU 14
  530. +#define V3S_CLK_AHB1 16 /*XXX*/
  531. +#define V3S_CLK_APB1 17 /*XXX*/
  532. +#define V3S_CLK_APB2 18 /*XXX*/
  533. +#define V3S_CLK_AHB2 19 /*XXX*/
  534. +#define V3S_CLK_BUS_CE 20
  535. +#define V3S_CLK_BUS_DMA 21
  536. +#define V3S_CLK_BUS_MMC0 22
  537. +#define V3S_CLK_BUS_MMC1 23
  538. +#define V3S_CLK_BUS_MMC2 24
  539. +#define V3S_CLK_BUS_DRAM 25
  540. +#define V3S_CLK_BUS_EMAC 26
  541. +#define V3S_CLK_BUS_HSTIMER 27
  542. +#define V3S_CLK_BUS_SPI0 28
  543. +#define V3S_CLK_BUS_OTG 29
  544. +#define V3S_CLK_BUS_EHCI0 30
  545. +#define V3S_CLK_BUS_OHCI0 31
  546. +#define V3S_CLK_BUS_VE 32
  547. +#define V3S_CLK_BUS_TCON0 33
  548. +#define V3S_CLK_BUS_CSI 34
  549. +#define V3S_CLK_BUS_DE 35
  550. +#define V3S_CLK_BUS_CODEC 36
  551. +#define V3S_CLK_BUS_PIO 37
  552. +#define V3S_CLK_BUS_I2C0 38
  553. +#define V3S_CLK_BUS_I2C1 39
  554. +#define V3S_CLK_BUS_UART0 40
  555. +#define V3S_CLK_BUS_UART1 41
  556. +#define V3S_CLK_BUS_UART2 42
  557. +#define V3S_CLK_BUS_EPHY 43
  558. +#define V3S_CLK_BUS_DBG 44
  559. +#define V3S_CLK_MMC0 45
  560. +#define V3S_CLK_MMC0_SAMPLE 46
  561. +#define V3S_CLK_MMC0_OUTPUT 47
  562. +#define V3S_CLK_MMC1 48
  563. +#define V3S_CLK_MMC1_SAMPLE 49
  564. +#define V3S_CLK_MMC1_OUTPUT 50
  565. +#define V3S_CLK_MMC2 51
  566. +#define V3S_CLK_MMC2_SAMPLE 52
  567. +#define V3S_CLK_MMC2_OUTPUT 53
  568. +#define V3S_CLK_CE 54
  569. +#define V3S_CLK_SPI0 55
  570. +#define V3S_CLK_USB_PHY0 56
  571. +#define V3S_CLK_USB_OHCI0 57
  572. +#define V3S_CLK_DRAM_VE 59
  573. +#define V3S_CLK_DRAM_CSI 60
  574. +#define V3S_CLK_DRAM_EHCI 61
  575. +#define V3S_CLK_DRAM_OHCI 62
  576. +#define V3S_CLK_DE 63
  577. +#define V3S_CLK_TCON0 64
  578. +#define V3S_CLK_CSI_MISC 65
  579. +#define V3S_CLK_CSI0_MCLK 66
  580. +#define V3S_CLK_CSI1_SCLK 67
  581. +#define V3S_CLK_CSI1_MCLK 68
  582. +#define V3S_CLK_VE 69
  583. +#define V3S_CLK_AC_DIG 70
  584. +#define V3S_CLK_AVS 71
  585. +#define V3S_CLK_MIPI_CSI 73
  586. +#define V3S_CLK_BUS_I2S0 75
  587. +#define V3S_CLK_I2S0 76
  588. +
  589. +#endif /* !_SUN8I_V3S_CCU_H */
  590. diff -uNpr sunxi.orig/sun8i_v3s_gpio.c sunxi/sun8i_v3s_gpio.c
  591. --- sunxi.orig/sun8i_v3s_gpio.c 1970-01-01 09:00:00.000000000 +0900
  592. +++ sunxi/sun8i_v3s_gpio.c 2020-01-04 11:20:30.335881350 +0900
  593. @@ -0,0 +1,103 @@
  594. +/* $NetBSD: sun8i_v3s_gpio.c,v 1.3 2018/04/03 16:01:25 bouyer Exp $ */
  595. +
  596. +/*-
  597. + * Copyright (c) 2017 Jared McNeill <[email protected]>
  598. + * All rights reserved.
  599. + *
  600. + * Redistribution and use in source and binary forms, with or without
  601. + * modification, are permitted provided that the following conditions
  602. + * are met:
  603. + * 1. Redistributions of source code must retain the above copyright
  604. + * notice, this list of conditions and the following disclaimer.
  605. + * 2. Redistributions in binary form must reproduce the above copyright
  606. + * notice, this list of conditions and the following disclaimer in the
  607. + * documentation and/or other materials provided with the distribution.
  608. + *
  609. + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  610. + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  611. + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  612. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  613. + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  614. + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  615. + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  616. + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  617. + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  618. + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  619. + * SUCH DAMAGE.
  620. + *
  621. + * $FreeBSD$
  622. + */
  623. +
  624. +#include <sys/cdefs.h>
  625. +__KERNEL_RCSID(0, "$NetBSD: sun8i_v3s_gpio.c,v 1.3 2018/04/03 16:01:25 bouyer Exp $");
  626. +
  627. +#include <sys/param.h>
  628. +#include <sys/systm.h>
  629. +#include <sys/kernel.h>
  630. +#include <sys/types.h>
  631. +
  632. +#include <arm/sunxi/sunxi_gpio.h>
  633. +
  634. +static const struct sunxi_gpio_pins v3s_pins[] = {
  635. + { "PB0", 1, 0, { "gpio_in", "gpio_out", "uart2", NULL, NULL, NULL, "irq" }, 6, 0, 0 },
  636. + { "PB1", 1, 1, { "gpio_in", "gpio_out", "uart2", NULL, NULL, NULL, "irq" }, 6, 1, 0 },
  637. + { "PB2", 1, 2, { "gpio_in", "gpio_out", "uart2", NULL, NULL, NULL, "irq" }, 6, 2, 0 },
  638. + { "PB3", 1, 3, { "gpio_in", "gpio_out", "uart2", NULL, NULL, NULL, "irq" }, 6, 3, 0 },
  639. + { "PB4", 1, 4, { "gpio_in", "gpio_out", "pwm0", NULL, NULL, NULL, "irq" }, 6, 4, 0 },
  640. + { "PB5", 1, 5, { "gpio_in", "gpio_out", "pwm1", NULL, NULL, NULL, "irq" }, 6, 5, 0 },
  641. + { "PB6", 1, 6, { "gpio_in", "gpio_out", "i2c0", NULL, NULL, NULL, "irq" }, 6, 6, 0 },
  642. + { "PB7", 1, 7, { "gpio_in", "gpio_out", "i2c0", NULL, NULL, NULL, "irq" }, 6, 7, 0 },
  643. + { "PB8", 1, 8, { "gpio_in", "gpio_out", "i2c1", "uart0", NULL, NULL, "irq" }, 6, 8, 0 },
  644. + { "PB9", 1, 9, { "gpio_in", "gpio_out", "i2c1", "uart0", NULL, NULL, "irq" }, 6, 9, 0 },
  645. +
  646. + { "PC0", 2, 0, { "gpio_in", "gpio_out", "mmc2", "spi0" } },
  647. + { "PC1", 2, 1, { "gpio_in", "gpio_out", "mmc2", "spi0" } },
  648. + { "PC2", 2, 2, { "gpio_in", "gpio_out", "mmc2", "spi0" } },
  649. + { "PC3", 2, 3, { "gpio_in", "gpio_out", "mmc2", "spi0" } },
  650. +
  651. + { "PE0", 4, 0, { "gpio_in", "gpio_out", "csi", "lcd" } },
  652. + { "PE1", 4, 1, { "gpio_in", "gpio_out", "csi", "lcd" } },
  653. + { "PE2", 4, 2, { "gpio_in", "gpio_out", "csi", "lcd" } },
  654. + { "PE3", 4, 3, { "gpio_in", "gpio_out", "csi", "lcd" } },
  655. + { "PE4", 4, 4, { "gpio_in", "gpio_out", "csi", "lcd" } },
  656. + { "PE5", 4, 5, { "gpio_in", "gpio_out", "csi", "lcd" } },
  657. + { "PE6", 4, 6, { "gpio_in", "gpio_out", "csi", "lcd" } },
  658. + { "PE7", 4, 7, { "gpio_in", "gpio_out", "csi", "lcd" } },
  659. + { "PE8", 4, 8, { "gpio_in", "gpio_out", "csi", "lcd" } },
  660. + { "PE9", 4, 9, { "gpio_in", "gpio_out", "csi", "lcd" } },
  661. + { "PE10", 4, 10, { "gpio_in", "gpio_out", "csi", "lcd" } },
  662. + { "PE11", 4, 11, { "gpio_in", "gpio_out", "csi", "lcd" } },
  663. + { "PE12", 4, 12, { "gpio_in", "gpio_out", "csi", "lcd" } },
  664. + { "PE13", 4, 13, { "gpio_in", "gpio_out", "csi", "lcd" } },
  665. + { "PE14", 4, 14, { "gpio_in", "gpio_out", "csi", "lcd" } },
  666. + { "PE15", 4, 15, { "gpio_in", "gpio_out", "csi", "lcd" } },
  667. + { "PE16", 4, 16, { "gpio_in", "gpio_out", "csi", "lcd" } },
  668. + { "PE17", 4, 17, { "gpio_in", "gpio_out", "csi", "lcd" } },
  669. + { "PE18", 4, 18, { "gpio_in", "gpio_out", "csi", "lcd" } },
  670. + { "PE19", 4, 19, { "gpio_in", "gpio_out", "csi", "lcd" } },
  671. + { "PE20", 4, 20, { "gpio_in", "gpio_out", "csi", "mipi" } },
  672. + { "PE21", 4, 21, { "gpio_in", "gpio_out", "csi", "i2c1", "uart1" } },
  673. + { "PE22", 4, 22, { "gpio_in", "gpio_out", "csi", "i2c1", "uart1" } },
  674. + { "PE23", 4, 23, { "gpio_in", "gpio_out", NULL, "lcd", "uart1" } },
  675. + { "PE24", 4, 24, { "gpio_in", "gpio_out", NULL, "lcd", "uart1" } },
  676. +
  677. + { "PF0", 5, 0, { "gpio_in", "gpio_out", "mmc0", "jtag" } },
  678. + { "PF1", 5, 1, { "gpio_in", "gpio_out", "mmc0", "jtag" } },
  679. + { "PF2", 5, 2, { "gpio_in", "gpio_out", "mmc0", "uart0" } },
  680. + { "PF3", 5, 3, { "gpio_in", "gpio_out", "mmc0", "jtag" } },
  681. + { "PF4", 5, 4, { "gpio_in", "gpio_out", "mmc0", "uart0" } },
  682. + { "PF5", 5, 5, { "gpio_in", "gpio_out", "mmc0", "jtag" } },
  683. + { "PF6", 5, 6, { "gpio_in", "gpio_out" } },
  684. +
  685. + { "PG0", 6, 0, { "gpio_in", "gpio_out", "mmc1", NULL, NULL, NULL, "irq" }, 6, 0, 1 },
  686. + { "PG1", 6, 1, { "gpio_in", "gpio_out", "mmc1", NULL, NULL, NULL, "irq" }, 6, 1, 1 },
  687. + { "PG2", 6, 2, { "gpio_in", "gpio_out", "mmc1", NULL, NULL, NULL, "irq" }, 6, 2, 1 },
  688. + { "PG3", 6, 3, { "gpio_in", "gpio_out", "mmc1", NULL, NULL, NULL, "irq" }, 6, 3, 1 },
  689. + { "PG4", 6, 4, { "gpio_in", "gpio_out", "mmc1", NULL, NULL, NULL, "irq" }, 6, 4, 1 },
  690. + { "PG5", 6, 5, { "gpio_in", "gpio_out", "mmc1", NULL, NULL, NULL, "irq" }, 6, 5, 1 },
  691. +};
  692. +
  693. +const struct sunxi_gpio_padconf sun8i_v3s_padconf = {
  694. + .npins = __arraycount(v3s_pins),
  695. + .pins = v3s_pins,
  696. +};
  697. diff -uNpr sunxi.orig/sunxi_gpio.c sunxi/sunxi_gpio.c
  698. --- sunxi.orig/sunxi_gpio.c 2020-01-02 15:55:43.069575547 +0900
  699. +++ sunxi/sunxi_gpio.c 2020-01-04 05:29:11.133565388 +0900
  700. @@ -101,6 +101,9 @@ static const struct of_compat_data compa
  701. { "allwinner,sun8i-h3-pinctrl", (uintptr_t)&sun8i_h3_padconf },
  702. { "allwinner,sun8i-h3-r-pinctrl", (uintptr_t)&sun8i_h3_r_padconf },
  703. #endif
  704. +#ifdef SOC_SUN8I_V3S
  705. + { "allwinner,sun8i-v3s-pinctrl", (uintptr_t)&sun8i_v3s_padconf },
  706. +#endif
  707. #ifdef SOC_SUN9I_A80
  708. { "allwinner,sun9i-a80-pinctrl", (uintptr_t)&sun9i_a80_padconf },
  709. { "allwinner,sun9i-a80-r-pinctrl", (uintptr_t)&sun9i_a80_r_padconf },
  710. diff -uNpr sunxi.orig/sunxi_gpio.h sunxi/sunxi_gpio.h
  711. --- sunxi.orig/sunxi_gpio.h 2020-01-02 15:55:43.070144754 +0900
  712. +++ sunxi/sunxi_gpio.h 2020-01-04 11:21:46.703407675 +0900
  713. @@ -79,6 +79,10 @@ extern const struct sunxi_gpio_padconf s
  714. extern const struct sunxi_gpio_padconf sun8i_h3_r_padconf;
  715. #endif
  716.  
  717. +#ifdef SOC_SUN8I_V3S
  718. +extern const struct sunxi_gpio_padconf sun8i_v3s_padconf;
  719. +#endif
  720. +
  721. #ifdef SOC_SUN9I_A80
  722. extern const struct sunxi_gpio_padconf sun9i_a80_padconf;
  723. extern const struct sunxi_gpio_padconf sun9i_a80_r_padconf;
  724. diff -uNpr sunxi.orig/sunxi_timer.c sunxi/sunxi_timer.c
  725. --- sunxi.orig/sunxi_timer.c 2020-01-02 15:55:43.080029809 +0900
  726. +++ sunxi/sunxi_timer.c 2020-01-02 16:57:06.170666181 +0900
  727. @@ -91,9 +91,11 @@ __KERNEL_RCSID(0, "$NetBSD: sunxi_timer.
  728. #define LOSC_CTRL_OSC32K_AUTO_SWT_EN __BIT(14)
  729. #define LOSC_CTRL_OSC32K_SEL __BIT(0)
  730.  
  731. -static const char * const compatible[] = {
  732. - "allwinner,sun4i-a10-timer",
  733. - NULL
  734. +static const struct of_compat_data compat_data[] = {
  735. + { "allwinner,sun4i-a10-timer", 6 },
  736. + { "allwinner,sun8i-v3s-timer", 3 },
  737. + { "allwinner,suniv-f1c100s-timer", 3 },
  738. + { NULL }
  739. };
  740.  
  741. struct sunxi_timer_softc {
  742. @@ -103,6 +105,8 @@ struct sunxi_timer_softc {
  743. int sc_phandle;
  744. struct clk *sc_clk;
  745.  
  746. + int sc_ntimers;
  747. +
  748. struct timecounter sc_tc;
  749. struct timecounter sc_tc_losc;
  750. };
  751. @@ -178,7 +182,7 @@ sunxi_timer_match(device_t parent, cfdat
  752. {
  753. struct fdt_attach_args * const faa = aux;
  754.  
  755. - return of_match_compatible(faa->faa_phandle, compatible);
  756. + return of_match_compat_data(faa->faa_phandle, compat_data);
  757. }
  758.  
  759. static void
  760. @@ -211,6 +215,7 @@ sunxi_timer_attach(device_t parent, devi
  761. aprint_error(": couldn't map registers\n");
  762. return;
  763. }
  764. + sc->sc_ntimers = of_search_compatible(phandle, compat_data)->data;
  765.  
  766. aprint_naive("\n");
  767. aprint_normal(": Timer\n");
  768. @@ -230,9 +235,6 @@ sunxi_timer_attach(device_t parent, devi
  769. TIMER_WRITE(sc, TMR2_CTRL_REG,
  770. __SHIFTIN(TMR2_CTRL_CLK_SRC_OSC24M, TMR2_CTRL_CLK_SRC) |
  771. TMR2_CTRL_RELOAD | TMR2_CTRL_EN);
  772. - /* Enable Timer 4 (timecounter for LOSC) */
  773. - TIMER_WRITE(sc, TMR4_INTV_VALUE_REG, ~0u);
  774. - TIMER_WRITE(sc, TMR4_CTRL_REG, TMR4_CTRL_RELOAD | TMR4_CTRL_EN);
  775.  
  776. /* Timecounter setup */
  777. tc->tc_get_timecount = sunxi_timer_get_timecount;
  778. @@ -242,26 +244,31 @@ sunxi_timer_attach(device_t parent, devi
  779. tc->tc_quality = 200;
  780. tc->tc_priv = sc;
  781. tc_init(tc);
  782. - tc_losc->tc_get_timecount = sunxi_timer_get_timecount_losc;
  783. - tc_losc->tc_counter_mask = ~0u;
  784. - tc_losc->tc_frequency = 32768;
  785. - tc_losc->tc_name = "LOSC";
  786. - tc_losc->tc_quality = 150;
  787. - tc_losc->tc_priv = sc;
  788. - /*
  789. - * LOSC is optional to implement in hardware.
  790. - * Make sure it ticks before registering it.
  791. - */
  792. - reg = __SHIFTIN(LOSC_CTRL_KEY_FIELD_V, LOSC_CTRL_KEY_FIELD) |
  793. - LOSC_CTRL_OSC32K_AUTO_SWT_EN |
  794. - LOSC_CTRL_OSC32K_SEL;
  795. - TIMER_WRITE(sc, LOSC_CTRL_REG, reg);
  796. - ticks = sunxi_timer_get_timecount_losc(tc_losc);
  797. - delay(100);
  798. - if (ticks != sunxi_timer_get_timecount_losc(tc_losc))
  799. - tc_init(tc_losc);
  800. - else
  801. - TIMER_WRITE(sc, LOSC_CTRL_REG, reg & ~LOSC_CTRL_OSC32K_SEL);
  802. +
  803. + /* Timer 4 (timecounter for LOSC) is optional */
  804. + if (sc->sc_ntimers > 3) {
  805. + tc_losc->tc_get_timecount = sunxi_timer_get_timecount_losc;
  806. + tc_losc->tc_counter_mask = ~0u;
  807. + tc_losc->tc_frequency = 32768;
  808. + tc_losc->tc_name = "LOSC";
  809. + tc_losc->tc_quality = 150;
  810. + tc_losc->tc_priv = sc;
  811. +
  812. + /* Make sure it ticks before registering it. */
  813. + TIMER_WRITE(sc, TMR4_INTV_VALUE_REG, ~0u);
  814. + TIMER_WRITE(sc, TMR4_CTRL_REG, TMR4_CTRL_RELOAD | TMR4_CTRL_EN);
  815. + reg = __SHIFTIN(LOSC_CTRL_KEY_FIELD_V, LOSC_CTRL_KEY_FIELD) |
  816. + LOSC_CTRL_OSC32K_AUTO_SWT_EN |
  817. + LOSC_CTRL_OSC32K_SEL;
  818. + TIMER_WRITE(sc, LOSC_CTRL_REG, reg);
  819. + ticks = sunxi_timer_get_timecount_losc(tc_losc);
  820. + delay(100);
  821. + if (ticks != sunxi_timer_get_timecount_losc(tc_losc))
  822. + tc_init(tc_losc);
  823. + else
  824. + TIMER_WRITE(sc, LOSC_CTRL_REG,
  825. + reg & ~LOSC_CTRL_OSC32K_SEL);
  826. + }
  827.  
  828. /* Use this as the OS timer in UP configurations */
  829. if (!arm_has_mpext_p) {
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