freq

module frequency_divider #(parameter DIVISOR = 2)(
    input clock_in,
    output clock_out
);
    wire[27:0] counter;

    clk_func #(.width(28), .step(1), .up_down(0), .M(DIVISOR)) mod_clk(
        .clk(clock_in), .out(counter)  // CHANGE .up_down, 1 - addition, 0 - substraction
    );
    assign clock_out = (counter < DIVISOR / 2) ? 1'b0 : 1'b1;

endmodule