`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:    08:57:32 03/27/2012
// Design Name:
// Module Name:    thunderbolt
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module thunderbolt(
    input left,
    input right,
    input reset,
    input clk,
    output reg [5:0] lights
    );

parameter lights_off = 2'b00;
parameter light_1 =    2'b01;
parameter light_2 =    2'b10;
parameter light_3 =    2'b11;

reg [1:0] state_left, next_left_state, state_right, next_right_state;

initial
        begin
                state_left = lights_off;
                state_right = lights_off;
                next_left_state = lights_off;
                next_right_state = lights_off;
        end

wire clk_en;

clk_div clock(.clk(clk), .reset(reset), .clk_en(clk_en));

always @(posedge clk_en, posedge reset)
        begin
                if (reset == 1)
                        begin
                                state_left <= lights_off;
                                state_right <= lights_off;
                        end
                else
                        begin
                                state_left <= next_left_state;
                                state_right <= next_right_state;
                        end
        end


always @(posedge clk_en)
        begin
                if (left == 1 && state_left == lights_off)
                        next_left_state <= light_1;

                case (state_left)
                        light_1: next_left_state <= light_2;
                        light_2: next_left_state <= light_3;
                        default: next_left_state <= lights_off;
                endcase

                if (right == 1 && state_right == lights_off)
                        next_right_state <= light_1;

                case (state_right)
                        light_1: next_right_state <= light_2;
                        light_2: next_right_state <= light_3;
                        default: next_right_state <= lights_off;
                endcase
        end

//output
always @(*)
        begin
                case(state_left)
                        light_1:   lights[5:3] <= 3'b001;
                        light_2:   lights[5:3] <= 3'b011;
                        light_3:   lights[5:3] <= 3'b111;
                        default: lights[5:3] <= 3'b000;
                endcase

                case(state_right)
                        light_1:   lights[2:0] <= 3'b100;
                        light_2:   lights[2:0] <= 3'b110;
                        light_3:   lights[2:0] <= 3'b111;
                        default: lights[2:0] <= 3'b000;
                endcase
        end
endmodule