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- abc -luts 6,6,6,1,2,4:
- === aoR3000 ===
- Number of wires: 60987
- Number of wire bits: 215626
- Number of public wires: 939
- Number of public wire bits: 12061
- Number of memories: 0
- Number of memory bits: 0
- Number of processes: 0
- Number of cells: 14928
- $__MISTRAL_MLAB 128
- MISTRAL_FF 2750
- MISTRAL_LUT4 7428
- MISTRAL_LUT5 3862
- MISTRAL_LUT6 759
- MISTRAL_NOT 1
- abc9 -luts 6,6,6,1,2,4 (attempt 1):
- === aoR3000 ===
- Number of wires: 239412
- Number of wire bits: 412390
- Number of public wires: 939
- Number of public wire bits: 12061
- Number of memories: 0
- Number of memory bits: 0
- Number of processes: 0
- Number of cells: 17163
- $__MISTRAL_MLAB 128
- MISTRAL_FF 2750
- MISTRAL_LUT4 9159
- MISTRAL_LUT5 4447
- MISTRAL_LUT6 679
- abc9 -luts 4:6 (attempt 2):
- === aoR3000 ===
- Number of wires: 239103
- Number of wire bits: 402672
- Number of public wires: 939
- Number of public wire bits: 12061
- Number of memories: 0
- Number of memory bits: 0
- Number of processes: 0
- Number of cells: 17060
- $__MISTRAL_MLAB 128
- MISTRAL_FF 2750
- MISTRAL_LUT4 11419
- MISTRAL_LUT5 2442
- MISTRAL_LUT6 321
- abc9 -luts 4:6 (attempt 3, after inlining synth):
- === aoR3000 ===
- Number of wires: 37771
- Number of wire bits: 86592
- Number of public wires: 512
- Number of public wire bits: 8988
- Number of memories: 0
- Number of memory bits: 0
- Number of processes: 0
- Number of cells: 15953
- $__MISTRAL_MLAB 128
- MISTRAL_FF 2675
- MISTRAL_LUT4 10755
- MISTRAL_LUT5 1985
- MISTRAL_LUT6 410
- abc9 -luts 4:6 (attempt 4, after adding DFF improvements):
- === aoR3000 ===
- Number of wires: 32754
- Number of wire bits: 75220
- Number of public wires: 536
- Number of public wire bits: 8610
- Number of memories: 0
- Number of memory bits: 0
- Number of processes: 0
- Number of cells: 13687
- $__MISTRAL_MLAB 128
- MISTRAL_FF 2255
- MISTRAL_LUT4 9272
- MISTRAL_LUT5 1655
- MISTRAL_LUT6 377
- Quartus, for comparison:
- +-----------------------------------------------------+
- ; Post-Synthesis Netlist Statistics for Top Partition ;
- +-----------------------+-----------------------------+
- ; Type ; Count ;
- +-----------------------+-----------------------------+
- ; arriav_ff ; 6333 ;
- ; CLR ; 669 ;
- ; CLR SCLR ; 48 ;
- ; CLR SLD ; 185 ;
- ; ENA ; 3267 ;
- ; ENA CLR ; 671 ;
- ; ENA CLR SCLR ; 705 ;
- ; ENA CLR SLD ; 152 ;
- ; plain ; 636 ;
- ; arriav_lcell_comb ; 5665 ;
- ; arith ; 480 ;
- ; 0 data inputs ; 2 ;
- ; 1 data inputs ; 305 ;
- ; 2 data inputs ; 77 ;
- ; 5 data inputs ; 96 ;
- ; extend ; 844 ;
- ; 7 data inputs ; 844 ;
- ; normal ; 4277 ;
- ; 0 data inputs ; 1 ;
- ; 1 data inputs ; 9 ;
- ; 2 data inputs ; 199 ;
- ; 3 data inputs ; 483 ;
- ; 4 data inputs ; 691 ;
- ; 5 data inputs ; 1092 ;
- ; 6 data inputs ; 1802 ;
- ; shared ; 64 ;
- ; 0 data inputs ; 1 ;
- ; 1 data inputs ; 31 ;
- ; 2 data inputs ; 32 ;
- ; arriav_mac ; 3 ;
- ; boundary_port ; 115 ;
- ; stratixv_ram_block ; 239 ;
- ; ; ;
- ; Max LUT depth ; 18.00 ;
- ; Average LUT depth ; 6.73 ;
- +-----------------------+-----------------------------+
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