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bshubenok_sirin Feb 7th, 2019 83 Never
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  1. /*
  2.  * This devicetree is generated by sopc2dts version 17.1 [9b3346002ac555f36b80b1bc56dad1cb86298234] on Tue Feb 27 13:47:36 EET 2018
  3.  * Sopc2dts is written by Walter Goossens <waltergoossens@home.nl>
  4.  * in cooperation with the nios2 community <nios2-dev@lists.rocketboards.org>
  5.  */
  6. /dts-v1/;
  7.  
  8. / {
  9.     model = "UniDASs";  /* appended from boardinfo */
  10.     compatible = "altr,socfpga-cyclone5", "altr,socfpga";   /* appended from boardinfo */
  11.     #address-cells = <1>;
  12.     #size-cells = <1>;
  13.  
  14.     aliases {
  15.         ethernet0 = "/sopc/ethernet@0xff702000";
  16.     }; //end aliases
  17.  
  18.     cpus {
  19.         #address-cells = <1>;
  20.         #size-cells = <0>;
  21.  
  22.         hps_0_arm_a9_0: cpu@0x0 {
  23.             device_type = "cpu";
  24.             compatible = "arm,cortex-a9-17.0", "arm,cortex-a9";
  25.             reg = <0x00000000>;
  26.             next-level-cache = <&hps_0_L2>; /* appended from boardinfo */
  27.         }; //end cpu@0x0 (hps_0_arm_a9_0)
  28.  
  29.         hps_0_arm_a9_1: cpu@0x1 {
  30.             device_type = "cpu";
  31.             compatible = "arm,cortex-a9-17.0", "arm,cortex-a9";
  32.             reg = <0x00000001>;
  33.             next-level-cache = <&hps_0_L2>; /* appended from boardinfo */
  34.         }; //end cpu@0x1 (hps_0_arm_a9_1)
  35.     }; //end cpus
  36.  
  37.     memory {
  38.         device_type = "memory";
  39.         reg = <0xffff0000 0x00010000>,
  40.             <0x00000000 0x80000000>;
  41.     }; //end memory
  42.  
  43.     clocks {
  44.         #address-cells = <1>;
  45.         #size-cells = <1>;
  46.  
  47.         hps_0_eosc1: hps_0_eosc1 {
  48.             compatible = "fixed-clock";
  49.             #clock-cells = <0>;
  50.             clock-frequency = <25000000>;   /* 25.00 MHz */
  51.             clock-output-names = "hps_0_eosc1-clk";
  52.         }; //end hps_0_eosc1 (hps_0_eosc1)
  53.  
  54.         hps_0_eosc2: hps_0_eosc2 {
  55.             compatible = "fixed-clock";
  56.             #clock-cells = <0>;
  57.             clock-frequency = <25000000>;   /* 25.00 MHz */
  58.             clock-output-names = "hps_0_eosc2-clk";
  59.         }; //end hps_0_eosc2 (hps_0_eosc2)
  60.  
  61.         hps_0_f2s_periph_ref_clk: hps_0_f2s_periph_ref_clk {
  62.             compatible = "fixed-clock";
  63.             #clock-cells = <0>;
  64.             clock-frequency = <0>;  /* 0.00 Hz */
  65.             clock-output-names = "hps_0_f2s_periph_ref_clk-clk";
  66.         }; //end hps_0_f2s_periph_ref_clk (hps_0_f2s_periph_ref_clk)
  67.  
  68.         hps_0_f2s_sdram_ref_clk: hps_0_f2s_sdram_ref_clk {
  69.             compatible = "fixed-clock";
  70.             #clock-cells = <0>;
  71.             clock-frequency = <0>;  /* 0.00 Hz */
  72.             clock-output-names = "hps_0_f2s_sdram_ref_clk-clk";
  73.         }; //end hps_0_f2s_sdram_ref_clk (hps_0_f2s_sdram_ref_clk)
  74.     }; //end clocks
  75.  
  76.     sopc0: sopc@0 {
  77.         device_type = "soc";
  78.         ranges;
  79.         #address-cells = <1>;
  80.         #size-cells = <1>;
  81.         compatible = "ALTR,avalon", "simple-bus";
  82.         bus-frequency = <0>;
  83.  
  84.         hps_0_bridges: bridge@0xc0000000 {
  85.             compatible = "altr,bridge-17.0", "simple-bus";
  86.             reg = <0xc0000000 0x20000000>;
  87.             clocks = <&h2f_user2_clock>;
  88.             #address-cells = <2>;
  89.             #size-cells = <1>;
  90.             ranges = <0x00000000 0x00030000 0xc0030000 0x00000008>,
  91.                 <0x00000000 0x00022000 0xc0022000 0x00000010>,
  92.                 <0x00000000 0x00000000 0xc0000000 0x00010000>,
  93.                 <0x00000000 0x00010000 0xc0010000 0x00010000>,
  94.                 <0x00000000 0x00030100 0xc0030100 0x00000020>,
  95.                 <0x00000000 0x00030200 0xc0030200 0x00000020>;
  96.  
  97.             sysid_qsys: sysid@0x000030000 {
  98.                 compatible = "altr,sysid-17.0", "altr,sysid-1.0";
  99.                 reg = <0x00000000 0x00030000 0x00000008>;
  100.                 clocks = <&h2f_user2_clock>;
  101.                 id = <2882400000>;  /* embeddedsw.dts.params.id type NUMBER */
  102.                 timestamp = <1519718409>;   /* embeddedsw.dts.params.timestamp type NUMBER */
  103.             }; //end sysid@0x000030000 (sysid_qsys)
  104.  
  105.             pps_time_source_0: unknown@0x000022000 {
  106.                 compatible = "unknown,unknown-1.0";
  107.                 reg = <0x00000000 0x00022000 0x00000010>;
  108.                 clocks = <&h2f_user2_clock>;
  109.             }; //end unknown@0x000022000 (pps_time_source_0)
  110.  
  111.             lms_iq_processor: unknown@0x000000000 {
  112.                 compatible = "unknown,unknown-1.0";
  113.                 reg = <0x00000000 0x00000000 0x00010000>;
  114.                 clocks = <&h2f_user2_clock>;
  115.             }; //end unknown@0x000000000 (lms_transceiver_0)
  116.  
  117.             reset_pio: gpio@0x000030100 {
  118.                 compatible = "altr,pio-17.0", "altr,pio-1.0";
  119.                 reg = <0x00000000 0x00030100 0x00000020>;
  120.                 clocks = <&h2f_user2_clock>;
  121.                 altr,gpio-bank-width = <2>; /* embeddedsw.dts.params.altr,gpio-bank-width type NUMBER */
  122.                 resetvalue = <0>;   /* embeddedsw.dts.params.resetvalue type NUMBER */
  123.                 #gpio-cells = <2>;
  124.                 gpio-controller;
  125.                 altr,ngpio = <2>;   /* appended from boardinfo */
  126.             }; //end gpio@0x000030100 (reset_pio)
  127.  
  128.             cs_pio: gpio@0x000030200 {
  129.                 gpio-controller;
  130.                 compatible = "altr,pio-17.0", "altr,pio-1.0";
  131.                 reg = <0x00000000 0x00030200 0x00000020>;
  132.                 clocks = <&h2f_user2_clock>;
  133.                 altr,gpio-bank-width = <4>; /* embeddedsw.dts.params.altr,gpio-bank-width type NUMBER */
  134.                 resetvalue = <1>;           /* embeddedsw.dts.params.resetvalue type NUMBER */
  135.                 #gpio-cells = <2>;
  136.                 altr,ngpio = <2>;           /* appended from boardinfo */
  137.                 gpio-line-names = "LMS6_CS", "LMS7_CS";
  138.             }; //end gpio@0x000030200 (cs_pio)
  139.         }; //end bridge@0xc0000000 (hps_0_bridges)
  140.  
  141.         hps_0_arm_gic_0: intc@0xfffed000 {
  142.             compatible = "arm,cortex-a9-gic-17.0", "arm,cortex-a9-gic";
  143.             reg = <0xfffed000 0x00001000>,
  144.                 <0xfffec100 0x00000100>;
  145.             reg-names = "axi_slave0", "axi_slave1";
  146.             interrupt-controller;
  147.             #interrupt-cells = <3>;
  148.         }; //end intc@0xfffed000 (hps_0_arm_gic_0)
  149.  
  150.         hps_0_L2: L2-cache@0xfffef000 {
  151.             compatible = "arm,pl310-cache-17.0", "arm,pl310-cache";
  152.             reg = <0xfffef000 0x00001000>;
  153.             interrupt-parent = <&hps_0_arm_gic_0>;
  154.             interrupts = <0 38 4>;
  155.             cache-level = <2>;  /* embeddedsw.dts.params.cache-level type NUMBER */
  156.             cache-unified;  /* appended from boardinfo */
  157.             arm,tag-latency = <1 1 1>;  /* appended from boardinfo */
  158.             arm,data-latency = <2 1 1>; /* appended from boardinfo */
  159.         }; //end L2-cache@0xfffef000 (hps_0_L2)
  160.  
  161.         hps_0_dma: dma@0xffe01000 {
  162.             compatible = "arm,pl330-17.0", "arm,pl330", "arm,primecell";
  163.             reg = <0xffe01000 0x00001000>;
  164.             interrupt-parent = <&hps_0_arm_gic_0>;
  165.             interrupts = <0 104 4>;
  166.             clocks = <&l4_main_clk>;
  167.             #dma-cells = <1>;   /* embeddedsw.dts.params.#dma-cells type NUMBER */
  168.             #dma-channels = <8>;    /* embeddedsw.dts.params.#dma-channels type NUMBER */
  169.             #dma-requests = <32>;   /* embeddedsw.dts.params.#dma-requests type NUMBER */
  170.             clock-names = "apb_pclk";   /* embeddedsw.dts.params.clock-names type STRING */
  171.             copy-align = <3>;   /* embeddedsw.dts.params.copy-align type NUMBER */
  172.             nr-irqs = <9>;  /* embeddedsw.dts.params.nr-irqs type NUMBER */
  173.             nr-valid-peri = <9>;    /* embeddedsw.dts.params.nr-valid-peri type NUMBER */
  174.         }; //end dma@0xffe01000 (hps_0_dma)
  175.  
  176.         hps_0_sysmgr: sysmgr@0xffd08000 {
  177.             compatible = "altr,sys-mgr-17.0", "altr,sys-mgr", "syscon";
  178.             reg = <0xffd08000 0x00000400>;
  179.             cpu1-start-addr = <4291854532>; /* embeddedsw.dts.params.cpu1-start-addr type NUMBER */
  180.         }; //end sysmgr@0xffd08000 (hps_0_sysmgr)
  181.  
  182.         hps_0_clkmgr: clkmgr@0xffd04000 {
  183.             compatible = "altr,clk-mgr-17.0", "altr,clk-mgr";
  184.             reg = <0xffd04000 0x00001000>;
  185.             clocks = <&hps_0_eosc1 &hps_0_eosc2 &hps_0_f2s_periph_ref_clk &hps_0_f2s_sdram_ref_clk>;
  186.             clock-names = "eosc1", "eosc2", "f2s_periph_ref_clk", "f2s_sdram_ref_clk";
  187.  
  188.             clock_tree {
  189.                 #size-cells = <0>;
  190.                 #address-cells = <1>;
  191.  
  192.                 sdram_pll: sdram_pll {
  193.                     compatible = "altr,socfpga-pll-clock";
  194.                     reg = <0x000000c0>;
  195.                     clocks = <&hps_0_eosc1 &hps_0_eosc2 &hps_0_f2s_sdram_ref_clk>;
  196.                     clock-names = "hps_0_eosc1", "hps_0_eosc2", "hps_0_f2s_sdram_ref_clk";
  197.                     #clock-cells = <0>;
  198.                     #address-cells = <1>;
  199.                     #size-cells = <0>;
  200.  
  201.                     ddr_dqs_clk: ddr_dqs_clk {
  202.                         compatible = "altr,socfpga-perip-clk";
  203.                         reg = <0x000000c8>;
  204.                         clocks = <&sdram_pll>;
  205.                         #clock-cells = <0>;
  206.                     }; //end ddr_dqs_clk (ddr_dqs_clk)
  207.  
  208.                     ddr_2x_dqs_clk: ddr_2x_dqs_clk {
  209.                         compatible = "altr,socfpga-perip-clk";
  210.                         reg = <0x000000cc>;
  211.                         clocks = <&sdram_pll>;
  212.                         #clock-cells = <0>;
  213.                     }; //end ddr_2x_dqs_clk (ddr_2x_dqs_clk)
  214.  
  215.                     ddr_dq_clk: ddr_dq_clk {
  216.                         compatible = "altr,socfpga-perip-clk";
  217.                         reg = <0x000000d0>;
  218.                         clocks = <&sdram_pll>;
  219.                         #clock-cells = <0>;
  220.                     }; //end ddr_dq_clk (ddr_dq_clk)
  221.  
  222.                     s2f_usr2_clk: s2f_usr2_clk {
  223.                         compatible = "altr,socfpga-perip-clk";
  224.                         reg = <0x000000d4>;
  225.                         clocks = <&sdram_pll>;
  226.                         #clock-cells = <0>;
  227.                     }; //end s2f_usr2_clk (s2f_usr2_clk)
  228.                 }; //end sdram_pll (sdram_pll)
  229.  
  230.                 periph_pll: periph_pll {
  231.                     compatible = "altr,socfpga-pll-clock";
  232.                     reg = <0x00000080>;
  233.                     clocks = <&hps_0_eosc1 &hps_0_eosc2 &hps_0_f2s_periph_ref_clk>;
  234.                     clock-names = "hps_0_eosc1", "hps_0_eosc2", "hps_0_f2s_periph_ref_clk";
  235.                     #clock-cells = <0>;
  236.                     #address-cells = <1>;
  237.                     #size-cells = <0>;
  238.  
  239.                     per_nand_mmc_clk: per_nand_mmc_clk {
  240.                         compatible = "altr,socfpga-perip-clk";
  241.                         reg = <0x00000094>;
  242.                         clocks = <&periph_pll>;
  243.                         #clock-cells = <0>;
  244.                     }; //end per_nand_mmc_clk (per_nand_mmc_clk)
  245.  
  246.                     per_base_clk: per_base_clk {
  247.                         compatible = "altr,socfpga-perip-clk";
  248.                         reg = <0x00000098>;
  249.                         clocks = <&periph_pll>;
  250.                         #clock-cells = <0>;
  251.                     }; //end per_base_clk (per_base_clk)
  252.  
  253.                     per_qspi_clk: per_qspi_clk {
  254.                         compatible = "altr,socfpga-perip-clk";
  255.                         reg = <0x00000090>;
  256.                         clocks = <&periph_pll>;
  257.                         #clock-cells = <0>;
  258.                     }; //end per_qspi_clk (per_qspi_clk)
  259.  
  260.                     s2f_usr1_clk: s2f_usr1_clk {
  261.                         compatible = "altr,socfpga-perip-clk";
  262.                         reg = <0x0000009c>;
  263.                         clocks = <&periph_pll>;
  264.                         #clock-cells = <0>;
  265.                     }; //end s2f_usr1_clk (s2f_usr1_clk)
  266.  
  267.                     emac0_clk: emac0_clk {
  268.                         compatible = "altr,socfpga-perip-clk";
  269.                         reg = <0x00000088>;
  270.                         clocks = <&periph_pll>;
  271.                         #clock-cells = <0>;
  272.                     }; //end emac0_clk (emac0_clk)
  273.  
  274.                     emac1_clk: emac1_clk {
  275.                         compatible = "altr,socfpga-perip-clk";
  276.                         reg = <0x0000008c>;
  277.                         clocks = <&periph_pll>;
  278.                         #clock-cells = <0>;
  279.                     }; //end emac1_clk (emac1_clk)
  280.                 }; //end periph_pll (periph_pll)
  281.  
  282.                 main_pll: main_pll {
  283.                     compatible = "altr,socfpga-pll-clock";
  284.                     reg = <0x00000040>;
  285.                     clocks = <&hps_0_eosc1>;
  286.                     #clock-cells = <0>;
  287.                     #address-cells = <1>;
  288.                     #size-cells = <0>;
  289.  
  290.                     cfg_s2f_usr0_clk: cfg_s2f_usr0_clk {
  291.                         compatible = "altr,socfpga-perip-clk";
  292.                         reg = <0x0000005c>;
  293.                         clocks = <&main_pll>;
  294.                         #clock-cells = <0>;
  295.                     }; //end cfg_s2f_usr0_clk (cfg_s2f_usr0_clk)
  296.  
  297.                     main_qspi_clk: main_qspi_clk {
  298.                         compatible = "altr,socfpga-perip-clk";
  299.                         reg = <0x00000054>;
  300.                         clocks = <&main_pll>;
  301.                         #clock-cells = <0>;
  302.                     }; //end main_qspi_clk (main_qspi_clk)
  303.  
  304.                     dbg_base_clk: dbg_base_clk {
  305.                         compatible = "altr,socfpga-perip-clk";
  306.                         reg = <0x00000050>;
  307.                         clocks = <&main_pll &hps_0_eosc1>;
  308.                         clock-names = "main_pll", "hps_0_eosc1";
  309.                         #clock-cells = <0>;
  310.                         div-reg = <0x000000e8 0x00000000 0x00000009>;
  311.                     }; //end dbg_base_clk (dbg_base_clk)
  312.  
  313.                     mpuclk: mpuclk {
  314.                         compatible = "altr,socfpga-perip-clk";
  315.                         reg = <0x00000048>;
  316.                         clocks = <&main_pll>;
  317.                         #clock-cells = <0>;
  318.                         div-reg = <0x000000e0 0x00000000 0x00000009>;
  319.                     }; //end mpuclk (mpuclk)
  320.  
  321.                     mainclk: mainclk {
  322.                         compatible = "altr,socfpga-perip-clk";
  323.                         reg = <0x0000004c>;
  324.                         clocks = <&main_pll>;
  325.                         #clock-cells = <0>;
  326.                         div-reg = <0x000000e4 0x00000000 0x00000009>;
  327.                     }; //end mainclk (mainclk)
  328.  
  329.                     main_nand_sdmmc_clk: main_nand_sdmmc_clk {
  330.                         compatible = "altr,socfpga-perip-clk";
  331.                         reg = <0x00000058>;
  332.                         clocks = <&main_pll>;
  333.                         #clock-cells = <0>;
  334.                     }; //end main_nand_sdmmc_clk (main_nand_sdmmc_clk)
  335.                 }; //end main_pll (main_pll)
  336.  
  337.                 mpu_l2_ram_clk: mpu_l2_ram_clk {
  338.                     compatible = "altr,socfpga-gate-clk";
  339.                     clocks = <&mpuclk>;
  340.                     #clock-cells = <0>;
  341.                     fixed-divider = <2>;
  342.                 }; //end mpu_l2_ram_clk (mpu_l2_ram_clk)
  343.  
  344.                 l4_main_clk: l4_main_clk {
  345.                     compatible = "altr,socfpga-gate-clk";
  346.                     clocks = <&mainclk>;
  347.                     #clock-cells = <0>;
  348.                     clk-gate = <0x00000060 0x00000000>;
  349.                 }; //end l4_main_clk (l4_main_clk)
  350.  
  351.                 l3_mp_clk: l3_mp_clk {
  352.                     compatible = "altr,socfpga-gate-clk";
  353.                     clocks = <&mainclk>;
  354.                     #clock-cells = <0>;
  355.                     clk-gate = <0x00000060 0x00000001>;
  356.                     div-reg = <0x00000064 0x00000000 0x00000002>;
  357.                 }; //end l3_mp_clk (l3_mp_clk)
  358.  
  359.                 l3_sp_clk: l3_sp_clk {
  360.                     compatible = "altr,socfpga-gate-clk";
  361.                     clocks = <&l3_mp_clk>;
  362.                     #clock-cells = <0>;
  363.                     div-reg = <0x00000064 0x00000002 0x00000002>;
  364.                 }; //end l3_sp_clk (l3_sp_clk)
  365.  
  366.                 l4_mp_clk: l4_mp_clk {
  367.                     compatible = "altr,socfpga-gate-clk";
  368.                     clocks = <&mainclk &per_base_clk>;
  369.                     clock-names = "mainclk", "per_base_clk";
  370.                     #clock-cells = <0>;
  371.                     clk-gate = <0x00000060 0x00000002>;
  372.                     div-reg = <0x00000064 0x00000004 0x00000003>;
  373.                 }; //end l4_mp_clk (l4_mp_clk)
  374.  
  375.                 l4_sp_clk: l4_sp_clk {
  376.                     compatible = "altr,socfpga-gate-clk";
  377.                     clocks = <&mainclk &per_base_clk>;
  378.                     clock-names = "mainclk", "per_base_clk";
  379.                     #clock-cells = <0>;
  380.                     clk-gate = <0x00000060 0x00000003>;
  381.                     div-reg = <0x00000064 0x00000007 0x00000003>;
  382.                 }; //end l4_sp_clk (l4_sp_clk)
  383.  
  384.                 dbg_at_clk: dbg_at_clk {
  385.                     compatible = "altr,socfpga-gate-clk";
  386.                     clocks = <&dbg_base_clk>;
  387.                     #clock-cells = <0>;
  388.                     clk-gate = <0x00000060 0x00000004>;
  389.                     div-reg = <0x00000068 0x00000000 0x00000002>;
  390.                 }; //end dbg_at_clk (dbg_at_clk)
  391.  
  392.                 dbg_clk: dbg_clk {
  393.                     compatible = "altr,socfpga-gate-clk";
  394.                     clocks = <&dbg_at_clk>;
  395.                     #clock-cells = <0>;
  396.                     clk-gate = <0x00000060 0x00000005>;
  397.                     div-reg = <0x00000068 0x00000002 0x00000002>;
  398.                 }; //end dbg_clk (dbg_clk)
  399.  
  400.                 dbg_trace_clk: dbg_trace_clk {
  401.                     compatible = "altr,socfpga-gate-clk";
  402.                     clocks = <&dbg_base_clk>;
  403.                     #clock-cells = <0>;
  404.                     clk-gate = <0x00000060 0x00000006>;
  405.                     div-reg = <0x0000006c 0x00000000 0x00000003>;
  406.                 }; //end dbg_trace_clk (dbg_trace_clk)
  407.  
  408.                 dbg_timer_clk: dbg_timer_clk {
  409.                     compatible = "altr,socfpga-gate-clk";
  410.                     clocks = <&dbg_base_clk>;
  411.                     #clock-cells = <0>;
  412.                     clk-gate = <0x00000060 0x00000007>;
  413.                 }; //end dbg_timer_clk (dbg_timer_clk)
  414.  
  415.                 cfg_clk: cfg_clk {
  416.                     compatible = "altr,socfpga-gate-clk";
  417.                     clocks = <&cfg_s2f_usr0_clk>;
  418.                     #clock-cells = <0>;
  419.                     clk-gate = <0x00000060 0x00000008>;
  420.                 }; //end cfg_clk (cfg_clk)
  421.  
  422.                 h2f_user0_clock: h2f_user0_clock {
  423.                     compatible = "altr,socfpga-gate-clk";
  424.                     clocks = <&cfg_s2f_usr0_clk>;
  425.                     #clock-cells = <0>;
  426.                     clk-gate = <0x00000060 0x00000009>;
  427.                 }; //end h2f_user0_clock (h2f_user0_clock)
  428.  
  429.                 emac_0_clk: emac_0_clk {
  430.                     compatible = "altr,socfpga-gate-clk";
  431.                     clocks = <&emac0_clk>;
  432.                     #clock-cells = <0>;
  433.                     clk-gate = <0x000000a0 0x00000000>;
  434.                 }; //end emac_0_clk (emac_0_clk)
  435.  
  436.                 emac_1_clk: emac_1_clk {
  437.                     compatible = "altr,socfpga-gate-clk";
  438.                     clocks = <&emac1_clk>;
  439.                     #clock-cells = <0>;
  440.                     clk-gate = <0x000000a0 0x00000001>;
  441.                 }; //end emac_1_clk (emac_1_clk)
  442.  
  443.                 usb_mp_clk: usb_mp_clk {
  444.                     compatible = "altr,socfpga-gate-clk";
  445.                     clocks = <&per_base_clk>;
  446.                     #clock-cells = <0>;
  447.                     clk-gate = <0x000000a0 0x00000002>;
  448.                     div-reg = <0x000000a4 0x00000000 0x00000003>;
  449.                 }; //end usb_mp_clk (usb_mp_clk)
  450.  
  451.                 spi_m_clk: spi_m_clk {
  452.                     compatible = "altr,socfpga-gate-clk";
  453.                     clocks = <&per_base_clk>;
  454.                     #clock-cells = <0>;
  455.                     clk-gate = <0x000000a0 0x00000003>;
  456.                     div-reg = <0x000000a4 0x00000003 0x00000003>;
  457.                 }; //end spi_m_clk (spi_m_clk)
  458.  
  459.                 can0_clk: can0_clk {
  460.                     compatible = "altr,socfpga-gate-clk";
  461.                     clocks = <&per_base_clk>;
  462.                     #clock-cells = <0>;
  463.                     clk-gate = <0x000000a0 0x00000004>;
  464.                     div-reg = <0x000000a4 0x00000006 0x00000003>;
  465.                 }; //end can0_clk (can0_clk)
  466.  
  467.                 can1_clk: can1_clk {
  468.                     compatible = "altr,socfpga-gate-clk";
  469.                     clocks = <&per_base_clk>;
  470.                     #clock-cells = <0>;
  471.                     clk-gate = <0x000000a0 0x00000005>;
  472.                     div-reg = <0x000000a4 0x00000009 0x00000003>;
  473.                 }; //end can1_clk (can1_clk)
  474.  
  475.                 gpio_db_clk: gpio_db_clk {
  476.                     compatible = "altr,socfpga-gate-clk";
  477.                     clocks = <&per_base_clk>;
  478.                     #clock-cells = <0>;
  479.                     clk-gate = <0x000000a0 0x00000006>;
  480.                     div-reg = <0x000000a8 0x00000000 0x00000018>;
  481.                 }; //end gpio_db_clk (gpio_db_clk)
  482.  
  483.                 h2f_user1_clock: h2f_user1_clock {
  484.                     compatible = "altr,socfpga-gate-clk";
  485.                     clocks = <&s2f_usr1_clk>;
  486.                     #clock-cells = <0>;
  487.                     clk-gate = <0x000000a0 0x00000007>;
  488.                 }; //end h2f_user1_clock (h2f_user1_clock)
  489.  
  490.                 sdmmc_clk: sdmmc_clk {
  491.                     compatible = "altr,socfpga-gate-clk";
  492.                     clocks = <&hps_0_f2s_periph_ref_clk &main_nand_sdmmc_clk &per_nand_mmc_clk>;
  493.                     clock-names = "hps_0_f2s_periph_ref_clk", "main_nand_sdmmc_clk", "per_nand_mmc_clk";
  494.                     #clock-cells = <0>;
  495.                     clk-gate = <0x000000a0 0x00000008>;
  496.                     clk-phase = <0 135>;    /* appended from boardinfo */
  497.                 }; //end sdmmc_clk (sdmmc_clk)
  498.  
  499.                 nand_x_clk: nand_x_clk {
  500.                     compatible = "altr,socfpga-gate-clk";
  501.                     clocks = <&hps_0_f2s_periph_ref_clk &main_nand_sdmmc_clk &per_nand_mmc_clk>;
  502.                     clock-names = "hps_0_f2s_periph_ref_clk", "main_nand_sdmmc_clk", "per_nand_mmc_clk";
  503.                     #clock-cells = <0>;
  504.                     clk-gate = <0x000000a0 0x00000009>;
  505.                 }; //end nand_x_clk (nand_x_clk)
  506.  
  507.                 nand_clk: nand_clk {
  508.                     compatible = "altr,socfpga-gate-clk";
  509.                     clocks = <&hps_0_f2s_periph_ref_clk &main_nand_sdmmc_clk &per_nand_mmc_clk>;
  510.                     clock-names = "hps_0_f2s_periph_ref_clk", "main_nand_sdmmc_clk", "per_nand_mmc_clk";
  511.                     #clock-cells = <0>;
  512.                     clk-gate = <0x000000a0 0x0000000a>;
  513.                     fixed-divider = <4>;
  514.                 }; //end nand_clk (nand_clk)
  515.  
  516.                 qspi_clk: qspi_clk {
  517.                     compatible = "altr,socfpga-gate-clk";
  518.                     clocks = <&hps_0_f2s_periph_ref_clk &main_qspi_clk &per_qspi_clk>;
  519.                     clock-names = "hps_0_f2s_periph_ref_clk", "main_qspi_clk", "per_qspi_clk";
  520.                     #clock-cells = <0>;
  521.                     clk-gate = <0x000000a0 0x0000000b>;
  522.                 }; //end qspi_clk (qspi_clk)
  523.  
  524.                 ddr_dqs_clk_gate: ddr_dqs_clk_gate {
  525.                     compatible = "altr,socfpga-gate-clk";
  526.                     clocks = <&ddr_dqs_clk>;
  527.                     #clock-cells = <0>;
  528.                     clk-gate = <0x000000d8 0x00000000>;
  529.                 }; //end ddr_dqs_clk_gate (ddr_dqs_clk_gate)
  530.  
  531.                 ddr_2x_dqs_clk_gate: ddr_2x_dqs_clk_gate {
  532.                     compatible = "altr,socfpga-gate-clk";
  533.                     clocks = <&ddr_2x_dqs_clk>;
  534.                     #clock-cells = <0>;
  535.                     clk-gate = <0x000000d8 0x00000001>;
  536.                 }; //end ddr_2x_dqs_clk_gate (ddr_2x_dqs_clk_gate)
  537.  
  538.                 ddr_dq_clk_gate: ddr_dq_clk_gate {
  539.                     compatible = "altr,socfpga-gate-clk";
  540.                     clocks = <&ddr_dq_clk>;
  541.                     #clock-cells = <0>;
  542.                     clk-gate = <0x000000d8 0x00000002>;
  543.                 }; //end ddr_dq_clk_gate (ddr_dq_clk_gate)
  544.  
  545.                 h2f_user2_clock: h2f_user2_clock {
  546.                     compatible = "altr,socfpga-gate-clk";
  547.                     clocks = <&s2f_usr2_clk>;
  548.                     #clock-cells = <0>;
  549.                     clk-gate = <0x000000d8 0x00000003>;
  550.                 }; //end h2f_user2_clock (h2f_user2_clock)
  551.  
  552.                 l3_main_clk: l3_main_clk {
  553.                     compatible = "altr,socfpga-gate-clk";
  554.                     clocks = <&mainclk>;
  555.                     #clock-cells = <0>;
  556.                 }; //end l3_main_clk (l3_main_clk)
  557.  
  558.                 mpu_periph_clk: mpu_periph_clk {
  559.                     compatible = "altr,socfpga-perip-clk";
  560.                     clocks = <&mpuclk>;
  561.                     #clock-cells = <0>;
  562.                     reg = <0x00000000>;
  563.                     fixed-divider = <4>;
  564.                 }; //end mpu_periph_clk (mpu_periph_clk)
  565.             }; //end clock_tree
  566.  
  567.             sdmmc_clk_divided: sdmmc_clk_divided {
  568.                 #clock-cells = <0>; /* appended from boardinfo */
  569.                 compatible = "altr,socfpga-gate-clk";   /* appended from boardinfo */
  570.                 clocks = <&sdmmc_clk>;  /* appended from boardinfo */
  571.                 fixed-divider = <4>;    /* appended from boardinfo */
  572.                 clk-gate = <0x000000a0 0x00000008>; /* appended from boardinfo */
  573.             }; //end sdmmc_clk_divided (sdmmc_clk_divided)
  574.         }; //end clkmgr@0xffd04000 (hps_0_clkmgr)
  575.  
  576.         hps_0_rstmgr: rstmgr@0xffd05000 {
  577.             compatible = "altr,rst-mgr-17.0", "altr,rst-mgr", "syscon";
  578.             reg = <0xffd05000 0x00000100>;
  579.             #reset-cells = <1>; /* appended from boardinfo */
  580.             altr,modrst-offset = <16>;  /* embeddedsw.dts.params.altr,modrst-offset type NUMBER */
  581.         }; //end rstmgr@0xffd05000 (hps_0_rstmgr)
  582.  
  583.         hps_0_fpgamgr: fpgamgr@0xff706000 {
  584.             compatible = "altr,fpga-mgr-17.0", "altr,fpga-mgr", "altr,socfpga-fpga-mgr";
  585.             reg = <0xff706000 0x00001000>,
  586.                 <0xffb90000 0x00000100>;
  587.             reg-names = "axi_slave0", "axi_slave1";
  588.             interrupt-parent = <&hps_0_arm_gic_0>;
  589.             interrupts = <0 175 4>;
  590.             transport = "mmio"; /* embeddedsw.dts.params.transport type STRING */
  591.         }; //end fpgamgr@0xff706000 (hps_0_fpgamgr)
  592.  
  593.         hps_0_uart0: serial@0xffc02000 {
  594.             compatible = "snps,dw-apb-uart-17.0", "snps,dw-apb-uart";
  595.             reg = <0xffc02000 0x00000100>;
  596.             interrupt-parent = <&hps_0_arm_gic_0>;
  597.             interrupts = <0 162 4>;
  598.             clocks = <&l4_sp_clk>;
  599.             reg-io-width = <4>; /* embeddedsw.dts.params.reg-io-width type NUMBER */
  600.             reg-shift = <2>;    /* embeddedsw.dts.params.reg-shift type NUMBER */
  601.             status = "okay";    /* embeddedsw.dts.params.status type STRING */
  602.         }; //end serial@0xffc02000 (hps_0_uart0)
  603.  
  604.         hps_0_uart1: serial@0xffc03000 {
  605.             compatible = "snps,dw-apb-uart-17.0", "snps,dw-apb-uart";
  606.             reg = <0xffc03000 0x00000100>;
  607.             interrupt-parent = <&hps_0_arm_gic_0>;
  608.             interrupts = <0 163 4>;
  609.             clocks = <&l4_sp_clk>;
  610.             reg-io-width = <4>; /* embeddedsw.dts.params.reg-io-width type NUMBER */
  611.             reg-shift = <2>;    /* embeddedsw.dts.params.reg-shift type NUMBER */
  612.             status = "disabled";    /* embeddedsw.dts.params.status type STRING */
  613.         }; //end serial@0xffc03000 (hps_0_uart1)
  614.  
  615.         hps_0_timer0: timer@0xffc08000 {
  616.             compatible = "snps,dw-apb-timer-sp-17.0", "snps,dw-apb-timer-sp";
  617.             reg = <0xffc08000 0x00000100>;
  618.             interrupt-parent = <&hps_0_arm_gic_0>;
  619.             interrupts = <0 167 4>;
  620.             clocks = <&l4_sp_clk>;
  621.             clock-names = "timer";  /* embeddedsw.dts.params.clock-names type STRING */
  622.         }; //end timer@0xffc08000 (hps_0_timer0)
  623.  
  624.         hps_0_timer1: timer@0xffc09000 {
  625.             compatible = "snps,dw-apb-timer-sp-17.0", "snps,dw-apb-timer-sp";
  626.             reg = <0xffc09000 0x00000100>;
  627.             interrupt-parent = <&hps_0_arm_gic_0>;
  628.             interrupts = <0 168 4>;
  629.             clocks = <&l4_sp_clk>;
  630.             clock-names = "timer";  /* embeddedsw.dts.params.clock-names type STRING */
  631.         }; //end timer@0xffc09000 (hps_0_timer1)
  632.  
  633.         hps_0_timer2: timer@0xffd00000 {
  634.             compatible = "snps,dw-apb-timer-osc-17.0", "snps,dw-apb-timer-osc";
  635.             reg = <0xffd00000 0x00000100>;
  636.             interrupt-parent = <&hps_0_arm_gic_0>;
  637.             interrupts = <0 169 4>;
  638.             clocks = <&hps_0_eosc1>;
  639.             clock-names = "timer";  /* embeddedsw.dts.params.clock-names type STRING */
  640.         }; //end timer@0xffd00000 (hps_0_timer2)
  641.  
  642.         hps_0_timer3: timer@0xffd01000 {
  643.             compatible = "snps,dw-apb-timer-osc-17.0", "snps,dw-apb-timer-osc";
  644.             reg = <0xffd01000 0x00000100>;
  645.             interrupt-parent = <&hps_0_arm_gic_0>;
  646.             interrupts = <0 170 4>;
  647.             clocks = <&hps_0_eosc1>;
  648.             clock-names = "timer";  /* embeddedsw.dts.params.clock-names type STRING */
  649.         }; //end timer@0xffd01000 (hps_0_timer3)
  650.  
  651.         hps_0_wd_timer0: timer@0xffd02000 {
  652.             compatible = "snps,dw-wdt-17.0", "snps,dw-wdt";
  653.             reg = <0xffd02000 0x00000100>;
  654.             interrupt-parent = <&hps_0_arm_gic_0>;
  655.             interrupts = <0 171 4>;
  656.             clocks = <&hps_0_eosc1>;
  657.             clock-names = "timer";  /* embeddedsw.dts.params.clock-names type STRING */
  658.         }; //end timer@0xffd02000 (hps_0_wd_timer0)
  659.  
  660.         hps_0_wd_timer1: timer@0xffd03000 {
  661.             compatible = "snps,dw-wdt-17.0", "snps,dw-wdt";
  662.             reg = <0xffd03000 0x00000100>;
  663.             interrupt-parent = <&hps_0_arm_gic_0>;
  664.             interrupts = <0 172 4>;
  665.             clocks = <&per_base_clk>;
  666.             clock-names = "timer";  /* embeddedsw.dts.params.clock-names type STRING */
  667.         }; //end timer@0xffd03000 (hps_0_wd_timer1)
  668.  
  669.         hps_0_gpio0: gpio@0xff708000 {
  670.             compatible = "snps,dw-apb-gpio", "snps,dw-gpio-17.0", "snps,dw-gpio";
  671.             reg = <0xff708000 0x00000100>;
  672.             gpio-controller;
  673.             interrupt-parent = <&hps_0_arm_gic_0>;
  674.             interrupts = <0 164 4>;
  675.             clocks = <&l4_mp_clk>;
  676.             #gpio-cells = <2>;
  677.             #address-cells = <1>;
  678.             #size-cells = <0>;
  679.  
  680.             hps_0_gpio0_porta: gpio-controller@0 {
  681.                 compatible = "snps,dw-apb-gpio-port";
  682.                 gpio-controller;
  683.                 #gpio-cells = <2>;
  684.                 snps,nr-gpios = <29>;
  685.                 reg = <0>;
  686.                 interrupt-controller;
  687.                 #interrupt-cells = <2>;
  688.                 interrupts = <0 164 4>;
  689.                 interrupt-parent = <&hps_0_arm_gic_0>;
  690.  
  691.                 usb_phy_reset {
  692.                     gpio-hog;
  693.                     gpios = <0 0>;
  694.                     output-low;
  695.                     line-name = "usb_phy_reset";
  696.                 };
  697.             };
  698.         };
  699.  
  700.         hps_0_gpio1: gpio@0xff709000 {
  701.             compatible = "snps,dw-apb-gpio", "snps,dw-gpio-17.0", "snps,dw-gpio";
  702.             reg = <0xff709000 0x00000100>;
  703.             interrupt-parent = <&hps_0_arm_gic_0>;
  704.             interrupts = <0 165 4>;
  705.             clocks = <&l4_mp_clk>;
  706.             #gpio-cells = <2>;
  707.             gpio-controller;
  708.             #address-cells = <1>;
  709.             #size-cells = <0>;
  710.  
  711.             hps_0_gpio1_porta: gpio-controller@0 {
  712.                 compatible = "snps,dw-apb-gpio-port";
  713.                 gpio-controller;
  714.                 #gpio-cells = <2>;
  715.                 snps,nr-gpios = <29>;
  716.                 reg = <0>;
  717.                 interrupt-controller;
  718.                 #interrupt-cells = <2>;
  719.                 interrupts = <0 165 4>;
  720.                 interrupt-parent = <&hps_0_arm_gic_0>;
  721.             }; //end gpio-controller@0 (hps_0_gpio1_porta)
  722.         }; //end gpio@0xff709000 (hps_0_gpio1)
  723.  
  724.         hps_0_gpio2: gpio@0xff70a000 {
  725.             compatible = "snps,dw-apb-gpio", "snps,dw-gpio-17.0", "snps,dw-gpio";
  726.             reg = <0xff70a000 0x00000100>;
  727.             interrupt-parent = <&hps_0_arm_gic_0>;
  728.             interrupts = <0 166 4>;
  729.             clocks = <&l4_mp_clk>;
  730.             #gpio-cells = <2>;
  731.             gpio-controller;
  732.             #address-cells = <1>;
  733.             #size-cells = <0>;
  734.  
  735.             hps_0_gpio2_porta: gpio-controller@0 {
  736.                 compatible = "snps,dw-apb-gpio-port";
  737.                 gpio-controller;
  738.                 #gpio-cells = <2>;
  739.                 snps,nr-gpios = <27>;
  740.                 reg = <0>;
  741.                 interrupt-controller;
  742.                 #interrupt-cells = <2>;
  743.                 interrupts = <0 166 4>;
  744.                 interrupt-parent = <&hps_0_arm_gic_0>;
  745.             }; //end gpio-controller@0 (hps_0_gpio2_porta)
  746.         }; //end gpio@0xff70a000 (hps_0_gpio2)
  747.  
  748.         hps_0_i2c0: i2c@0xffc04000 {
  749.             compatible = "snps,designware-i2c-17.0", "snps,designware-i2c";
  750.             reg = <0xffc04000 0x00000100>;
  751.             interrupt-parent = <&hps_0_arm_gic_0>;
  752.             interrupts = <0 158 4>;
  753.             clocks = <&l4_sp_clk>;
  754.             emptyfifo_hold_master = <1>;    /* embeddedsw.dts.params.emptyfifo_hold_master type NUMBER */
  755.             status = "okay";    /* embeddedsw.dts.params.status type STRING */
  756.             #address-cells = <1>;
  757.             #size-cells = <0>;
  758.             clock-frequency = <400000>; /* appended from boardinfo */
  759.  
  760.             eeprom: atmel,24AA025UID@0x50 {
  761.                 compatible = "microchip,24c04";
  762.                 reg = <0x00000050>;
  763.                 pagesize = <8>;
  764.             };
  765.         };
  766.  
  767.         hps_0_i2c1: i2c@0xffc05000 {
  768.             compatible = "snps,designware-i2c-17.0", "snps,designware-i2c";
  769.             reg = <0xffc05000 0x00000100>;
  770.             status = "disabled";
  771.             interrupt-parent = <&hps_0_arm_gic_0>;
  772.             interrupts = <0 159 4>;
  773.             clocks = <&l4_sp_clk>;
  774.             emptyfifo_hold_master = <1>;
  775.         };
  776.  
  777.         hps_0_i2c2: i2c@0xffc06000 {
  778.             compatible = "snps,designware-i2c-17.0", "snps,designware-i2c";
  779.             reg = <0xffc06000 0x00000100>;
  780.             status = "disabled";
  781.             interrupt-parent = <&hps_0_arm_gic_0>;
  782.             interrupts = <0 160 4>;
  783.             clocks = <&l4_sp_clk>;
  784.             emptyfifo_hold_master = <1>;
  785.         };
  786.  
  787.         hps_0_i2c3: i2c@0xffc07000 {
  788.             compatible = "snps,designware-i2c-17.0", "snps,designware-i2c";
  789.             reg = <0xffc07000 0x00000100>;
  790.             interrupt-parent = <&hps_0_arm_gic_0>;
  791.             interrupts = <0 161 4>;
  792.             clocks = <&l4_sp_clk>;
  793.             emptyfifo_hold_master = <1>;
  794.             status = "disabled";
  795.         };
  796.  
  797.         hps_0_nand0: flash@0xff900000 {
  798.             compatible = "denali,nand-17.0", "denali,denali-nand-dt";
  799.             reg = <0xff900000 0x00010000>,
  800.                 <0xffb80000 0x00010000>;
  801.             reg-names = "nand_data", "denali_reg";  /* embeddedsw.dts.params.reg-names type STRING */
  802.             interrupt-parent = <&hps_0_arm_gic_0>;
  803.             interrupts = <0 144 4>;
  804.             clocks = <&nand_clk>;
  805.             #address-cells = <1>;   /* embeddedsw.dts.params.#address-cells type NUMBER */
  806.             #size-cells = <1>;  /* embeddedsw.dts.params.#size-cells type NUMBER */
  807.             status = "disabled";    /* embeddedsw.dts.params.status type STRING */
  808.             bank-width = <2>;
  809.             device-width = <1>;
  810.         }; //end flash@0xff900000 (hps_0_nand0)
  811.  
  812.         hps_0_spim0: spi@0xfff00000 {
  813.             compatible = "snps,dw-spi-mmio-17.0", "snps,dw-spi-mmio", "snps,dw-apb-ssi";
  814.             reg = <0xfff00000 0x00000100>;
  815.             interrupt-parent = <&hps_0_arm_gic_0>;
  816.             interrupts = <0 154 4>;
  817.             clocks = <&spi_m_clk>;
  818.             #address-cells = <1>;   /* embeddedsw.dts.params.#address-cells type NUMBER */
  819.             #size-cells = <0>;  /* embeddedsw.dts.params.#size-cells type NUMBER */
  820.             bus-num = <0>;  /* embeddedsw.dts.params.bus-num type NUMBER */
  821.             num-chipselect = <4>;   /* embeddedsw.dts.params.num-chipselect type NUMBER */
  822.             status = "okay";    /* embeddedsw.dts.params.status type STRING */
  823.  
  824.             lms6002d: spid@0 {
  825.                 compatible = "spidev";
  826.                 reg = <0>;
  827.                 spi-max-frequency = <2000000>;
  828.                 enable-dma = <0>;
  829.             };
  830.         };
  831.  
  832.         hps_0_spim1: spi@0xfff01000 {
  833.             compatible = "snps,dw-spi-mmio-17.0", "snps,dw-spi-mmio", "snps,dw-apb-ssi";
  834.             reg = <0xfff01000 0x00000100>;
  835.             interrupt-parent = <&hps_0_arm_gic_0>;
  836.             interrupts = <0 155 4>;
  837.             clocks = <&spi_m_clk>;
  838.             #address-cells = <1>;   /* embeddedsw.dts.params.#address-cells type NUMBER */
  839.             #size-cells = <0>;  /* embeddedsw.dts.params.#size-cells type NUMBER */
  840.             bus-num = <0>;  /* embeddedsw.dts.params.bus-num type NUMBER */
  841.             num-chipselect = <4>;   /* embeddedsw.dts.params.num-chipselect type NUMBER */
  842.             status = "disabled";    /* embeddedsw.dts.params.status type STRING */
  843.         }; //end spi@0xfff01000 (hps_0_spim1)
  844.  
  845.         hps_0_qspi: flash@0xff705000 {
  846.             compatible = "cadence,qspi-17.0", "cadence,qspi", "cdns,qspi-nor";
  847.             reg = <0xff705000 0x00000100>,
  848.                 <0xffa00000 0x00000100>;
  849.             reg-names = "axi_slave0", "axi_slave1";
  850.             interrupt-parent = <&hps_0_arm_gic_0>;
  851.             interrupts = <0 151 4>;
  852.             clocks = <&qspi_clk>;
  853.             bus-num = <2>;  /* embeddedsw.dts.params.bus-num type NUMBER */
  854.             fifo-depth = <128>; /* embeddedsw.dts.params.fifo-depth type NUMBER */
  855.             num-chipselect = <4>;   /* embeddedsw.dts.params.num-chipselect type NUMBER */
  856.             status = "disabled";    /* embeddedsw.dts.params.status type STRING */
  857.             bank-width = <2>;
  858.             device-width = <1>;
  859.         }; //end flash@0xff705000 (hps_0_qspi)
  860.  
  861.         hps_0_sdmmc: flash@0xff704000 {
  862.             compatible = "altr,socfpga-dw-mshc";    /* appended from boardinfo */
  863.             reg = <0xff704000 0x00001000>;
  864.             interrupt-parent = <&hps_0_arm_gic_0>;
  865.             interrupts = <0 139 4>;
  866.             clocks = <&l4_mp_clk &sdmmc_clk_divided>;   /* appended from boardinfo */
  867.             clock-names = "biu", "ciu";
  868.             fifo-depth = <1024>;    /* embeddedsw.dts.params.fifo-depth type NUMBER */
  869.             num-slots = <1>;    /* embeddedsw.dts.params.num-slots type NUMBER */
  870.             status = "okay";    /* embeddedsw.dts.params.status type STRING */
  871.             #address-cells = <1>;   /* appended from boardinfo */
  872.             #size-cells = <0>;  /* appended from boardinfo */
  873.             broken-cd;  /* appended from boardinfo */
  874.             cap-mmc-highspeed;  /* appended from boardinfo */
  875.             cap-sd-highspeed;   /* appended from boardinfo */
  876.             bus-width = <4>;    /* appended from boardinfo */
  877.             altr,dw-mshc-ciu-div = <3>; /* appended from boardinfo */
  878.             supports-highspeed; /* appended from boardinfo */
  879.             altr,dw-mshc-sdr-timing = <0 3>;    /* appended from boardinfo */
  880.             cd = <&hps_0_gpio1_porta 18 0>; /* appended from boardinfo */
  881.             cd-gpios = <&hps_0_gpio1_porta 18 0>;   /* appended from boardinfo */
  882.  
  883.             slot_0: slot@0 {
  884.                 reg = <0>;  /* appended from boardinfo */
  885.                 bus-width = <4>;    /* appended from boardinfo */
  886.             }; //end slot@0 (slot_0)
  887.         }; //end flash@0xff704000 (hps_0_sdmmc)
  888.  
  889.         usbphy0: usbphy@0 {
  890.             compatible = "usb-nop-xceiv";
  891.             #phy-cells = <0>;
  892.             status = "okay";
  893.             //reset-gpios = <&hps_0_gpio0 0 0>;
  894.         };
  895.  
  896.         usb1: usb@0xffb40000 {
  897.             compatible = "snps,dwc2";
  898.             reg = <0xffb40000 0x00040000>;
  899.             interrupt-parent = <&hps_0_arm_gic_0>;
  900.             interrupts = <0 128 4>;
  901.             clocks = <&usb_mp_clk>;
  902.             resets = <&hps_0_rstmgr 35>;
  903.             reset-names = "dwc2";
  904.             clock-names = "otg";
  905.             phy-names = "usb2-phy";
  906.             phys = <&usbphy0>;
  907.             dr_mode = "host";
  908.             status = "okay";
  909.         }; //end usb@0xffb40000 (hps_0_usb1)
  910.  
  911.         hps_0_gmac0: ethernet@0xff700000 {
  912.             compatible = "synopsys,dwmac-17.0", "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
  913.             reg = <0xff700000 0x00002000>;
  914.             interrupt-parent = <&hps_0_arm_gic_0>;
  915.             interrupts = <0 115 4>;
  916.             clocks = <&emac0_clk>;
  917.             clock-names = "stmmaceth";  /* embeddedsw.dts.params.clock-names type STRING */
  918.             interrupt-names = "macirq"; /* embeddedsw.dts.params.interrupt-names type STRING */
  919.             rx-fifo-depth = <4096>; /* embeddedsw.dts.params.rx-fifo-depth type NUMBER */
  920.             snps,multicast-filter-bins = <256>; /* embeddedsw.dts.params.snps,multicast-filter-bins type NUMBER */
  921.             snps,perfect-filter-entries = <128>;    /* embeddedsw.dts.params.snps,perfect-filter-entries type NUMBER */
  922.             status = "disabled";    /* embeddedsw.dts.params.status type STRING */
  923.             tx-fifo-depth = <4096>; /* embeddedsw.dts.params.tx-fifo-depth type NUMBER */
  924.             address-bits = <48>;
  925.             max-frame-size = <1518>;
  926.             local-mac-address = [00 00 00 00 00 00];
  927.         }; //end ethernet@0xff700000 (hps_0_gmac0)
  928.  
  929.         hps_0_gmac1: ethernet@0xff702000 {
  930.             compatible = "synopsys,dwmac-17.0", "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
  931.             reg = <0xff702000 0x00002000>;
  932.             interrupt-parent = <&hps_0_arm_gic_0>;
  933.             interrupts = <0 120 4>;
  934.             clocks = <&emac1_clk>;
  935.             clock-names = "stmmaceth";              /* embeddedsw.dts.params.clock-names type STRING */
  936.             interrupt-names = "macirq";             /* embeddedsw.dts.params.interrupt-names type STRING */
  937.             rx-fifo-depth = <4096>;                 /* embeddedsw.dts.params.rx-fifo-depth type NUMBER */
  938.             snps,multicast-filter-bins = <256>;     /* embeddedsw.dts.params.snps,multicast-filter-bins type NUMBER */
  939.             snps,perfect-filter-entries = <128>;    /* embeddedsw.dts.params.snps,perfect-filter-entries type NUMBER */
  940.             status = "okay";                        /* embeddedsw.dts.params.status type STRING */
  941.             tx-fifo-depth = <4096>;                 /* embeddedsw.dts.params.tx-fifo-depth type NUMBER */
  942.             address-bits = <48>;
  943.             max-frame-size = <3800>;                /* appended from boardinfo */
  944.             local-mac-address = [00 00 00 00 00 00];
  945.             phy-mode = "rgmii";                     /* appended from boardinfo */
  946.             snps,phy-addr = <0xffffffff>;           /* appended from boardinfo */
  947.             phy-addr = <0xffffffff>;                /* appended from boardinfo */
  948.             txc-skew-ps = <3000>;                   /* appended from boardinfo */
  949.             rxc-skew-ps = <3000>;                   /* appended from boardinfo */
  950.             txen-skew-ps = <0>;                     /* appended from boardinfo */
  951.             rxdv-skew-ps = <0>;                     /* appended from boardinfo */
  952.             rxd0-skew-ps = <0>;                     /* appended from boardinfo */
  953.             rxd1-skew-ps = <0>;                     /* appended from boardinfo */
  954.             rxd2-skew-ps = <0>;                     /* appended from boardinfo */
  955.             rxd3-skew-ps = <0>;                     /* appended from boardinfo */
  956.             txd0-skew-ps = <0>;                     /* appended from boardinfo */
  957.             txd1-skew-ps = <0>;                     /* appended from boardinfo */
  958.             txd2-skew-ps = <0>;                     /* appended from boardinfo */
  959.             txd3-skew-ps = <0>;                     /* appended from boardinfo */
  960.             reset-names = "stmmaceth";  /* appended from boardinfo */
  961.             altr,sysmgr-syscon = <&hps_0_sysmgr 0x00000060 2>;  /* appended from boardinfo */
  962.             resets = <&hps_0_rstmgr 33>;    /* appended from boardinfo */
  963.         }; //end ethernet@0xff702000 (hps_0_gmac1)
  964.  
  965.         hps_0_dcan0: can@0xffc00000 {
  966.             compatible = "bosch,dcan-17.0", "bosch,d_can";
  967.             reg = <0xffc00000 0x00001000>;
  968.             interrupt-parent = <&hps_0_arm_gic_0>;
  969.             interrupts = <0 131 4 0 132 4>;
  970.             interrupt-names = "interrupt_sender0", "interrupt_sender1";
  971.             clocks = <&can0_clk>;
  972.             status = "disabled";    /* embeddedsw.dts.params.status type STRING */
  973.         }; //end can@0xffc00000 (hps_0_dcan0)
  974.  
  975.         hps_0_dcan1: can@0xffc01000 {
  976.             compatible = "bosch,dcan-17.0", "bosch,d_can";
  977.             reg = <0xffc01000 0x00001000>;
  978.             interrupt-parent = <&hps_0_arm_gic_0>;
  979.             interrupts = <0 135 4 0 136 4>;
  980.             interrupt-names = "interrupt_sender0", "interrupt_sender1";
  981.             clocks = <&can1_clk>;
  982.             status = "disabled";    /* embeddedsw.dts.params.status type STRING */
  983.         }; //end can@0xffc01000 (hps_0_dcan1)
  984.  
  985.         hps_0_l3regs: rl3regs@0xff800000 {
  986.             compatible = "altr,l3regs-17.0", "altr,l3regs", "syscon";
  987.             reg = <0xff800000 0x00001000>;
  988.         }; //end rl3regs@0xff800000 (hps_0_l3regs)
  989.  
  990.         hps_0_sdrctl: sdr-ctl@0xffc25000 {
  991.             compatible = "altr,sdr-ctl-17.0", "altr,sdr-ctl", "syscon";
  992.             reg = <0xffc25000 0x00001000>;
  993.         }; //end sdr-ctl@0xffc25000 (hps_0_sdrctl)
  994.  
  995.         hps_0_timer: timer@0xfffec600 {
  996.             compatible = "arm,cortex-a9-twd-timer-17.0", "arm,cortex-a9-twd-timer";
  997.             reg = <0xfffec600 0x00000100>;
  998.             interrupt-parent = <&hps_0_arm_gic_0>;
  999.             interrupts = <1 13 3844>;
  1000.             clocks = <&mpu_periph_clk>;
  1001.         }; //end timer@0xfffec600 (hps_0_timer)
  1002.  
  1003.         hps_0_scu: scu@0xfffec000 {
  1004.             compatible = "arm,corex-a9-scu-17.0", "arm,cortex-a9-scu";
  1005.             reg = <0xfffec000 0x00000100>;
  1006.         }; //end scu@0xfffec000 (hps_0_scu)
  1007.  
  1008.         unidas_iq: unidas_iq0@0xc000000 {
  1009.             compatible = "unidas-iq";
  1010.             reg = <0xc0000000 0x1000>;
  1011.             interrupt-parent = <&hps_0_arm_gic_0>;
  1012.             interrupts = <0 40 1>; // Not shared interrupt on 72 - 32 = 40 line
  1013.             dma-region-size = <716800>; // 512 x 1400 buffs
  1014.         };
  1015.  
  1016.         reset0: lms6002d_reset {
  1017.             gpios = <&reset_pio 0 1>;   /* appended from boardinfo */
  1018.         }; //end lms6002d_reset (reset0)
  1019.  
  1020.         reset1: lms7002m_reset {
  1021.             gpios = <&reset_pio 1 1>;   /* appended from boardinfo */
  1022.         }; //end lms7002m_reset (reset1)
  1023.  
  1024.         cs0: lms6002d_cs {
  1025.             gpios = <&cs_pio 0 1>;  /* appended from boardinfo */
  1026.             line-name = "lms_cs";
  1027.         }; //end lms6002d_cs (cs0)
  1028.  
  1029.         cs1: lms7002m_cs {
  1030.             gpios = <&cs_pio 1 1>;  /* appended from boardinfo */
  1031.         }; //end lms7002m_cs (cs1)
  1032.  
  1033.         pmu: pmu0 {
  1034.             #address-cells = <1>;   /* appended from boardinfo */
  1035.             #size-cells = <1>;  /* appended from boardinfo */
  1036.             compatible = "arm,cortex-a9-pmu";   /* appended from boardinfo */
  1037.             interrupt-parent = <&hps_0_arm_gic_0>;  /* appended from boardinfo */
  1038.             interrupts = <0 176 4 0 177 4>; /* appended from boardinfo */
  1039.             ranges; /* appended from boardinfo */
  1040.  
  1041.             cti0: cti0@ff118000 {
  1042.                 compatible = "arm,coresight-cti";   /* appended from boardinfo */
  1043.                 reg = <0xff118000 0x00001000>;  /* appended from boardinfo */
  1044.             }; //end cti0@ff118000 (cti0)
  1045.  
  1046.             cti1: cti0@ff119000 {
  1047.                 compatible = "arm,coresight-cti";   /* appended from boardinfo */
  1048.                 reg = <0xff119000 0x00001000>;  /* appended from boardinfo */
  1049.             }; //end cti0@ff119000 (cti1)
  1050.         }; //end pmu0 (pmu)
  1051.  
  1052.         fpgabridge0: fpgabridge@0 {
  1053.             compatible = "altr,socfpga-hps2fpga-bridge";    /* appended from boardinfo */
  1054.             label = "hps2fpga"; /* appended from boardinfo */
  1055.             clocks = <&l4_main_clk>;    /* appended from boardinfo */
  1056.             reset-names = "hps2fpga";   /* appended from boardinfo */
  1057.             resets = <&hps_0_rstmgr 96>;    /* appended from boardinfo */
  1058.         }; //end fpgabridge@0 (fpgabridge0)
  1059.  
  1060.         fpgabridge1: fpgabridge@1 {
  1061.             compatible = "altr,socfpga-lwhps2fpga-bridge";  /* appended from boardinfo */
  1062.             label = "lwhps2fpga";   /* appended from boardinfo */
  1063.             clocks = <&l4_main_clk>;    /* appended from boardinfo */
  1064.             reset-names = "lwhps2fpga"; /* appended from boardinfo */
  1065.             resets = <&hps_0_rstmgr 97>;    /* appended from boardinfo */
  1066.         }; //end fpgabridge@1 (fpgabridge1)
  1067.  
  1068.         fpgabridge2: fpgabridge@2 {
  1069.             compatible = "altr,socfpga-fpga2hps-bridge";    /* appended from boardinfo */
  1070.             label = "fpga2hps"; /* appended from boardinfo */
  1071.             clocks = <&l4_main_clk>;    /* appended from boardinfo */
  1072.             reset-names = "fpga2hps";   /* appended from boardinfo */
  1073.             resets = <&hps_0_rstmgr 98>;    /* appended from boardinfo */
  1074.         }; //end fpgabridge@2 (fpgabridge2)
  1075.     }; //end sopc@0 (sopc0)
  1076.  
  1077.     chosen {
  1078.         bootargs = "console=ttyS0,115200";
  1079.     }; //end chosen
  1080. }; //end /
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