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  1. module test_unit_sva (
  2.     input clk_i, rst_i, en_i,
  3.     input [3:0] some_data_i,
  4.     output [7:0] some_data_o
  5. );
  6. //counter is incremented at each posedge clock when en_i is asserted by the input value
  7. //some_data_i
  8.  
  9. property incrementCnt;
  10.     (en_i) |=> some_data_o == $past(some_data_i) + $past(some_data_o);
  11. endproperty
  12. //counter is reset at posedge rst
  13. property rstCnt;
  14.     @(posedge (clk_i)) $rose(rst_i) |=> (some_data_o == 0);
  15. endproperty
  16.  
  17. check_rstCnt_label: assert property (rstCnt)
  18. else $display ($time,,,"\t %m Failed reset init.!");
  19.  
  20. incrementCnt_labe: assert property (@(posedge (clk_i)) disable iff (rst_i) incrementCnt)
  21. else $display ($time,,,"\t %m Failed counter increment");
  22. endmodule
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