`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13.11.2019 14:08:22
// Design Name:
// Module Name: vga_out
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////


module vga_out(
    input clk, reset,
    output [3:0] pix_r,
    output [3:0] pix_g,
    output [3:0] pix_b,
    output hsync,
    output vsync
    );

    reg [10:0] hcount = 11'd300;
    reg [9:0] vcount = 10'd50;

    //outputs
    assign hsync = (hcount < 152 ) ? 1'b0:1'b1;
    assign vsync = (vcount < 3 ) ? 1'b1:1'b0;


    //colours
    assign pix_r = (hcount < 1824 && hcount > 383 && vcount < 931 && vcount > 30) ? 4'hF:4'h0;
    assign pix_g = (hcount < 1824 && hcount > 383 && vcount < 931 && vcount > 30) ? 4'hF:4'h0;
    assign pix_b = (hcount < 1824 && hcount > 383 && vcount < 931 && vcount > 30) ? 4'hF:4'h0;

    //assign pix_r = 4'hF;
    //assign pix_g = 4'hF;
    //assign pix_b = 4'hF;


    always @(posedge clk)
    begin
    if (reset) begin
    hcount <= 0;
    vcount <= 0;
    end
    if(hcount == 1903) begin
    hcount <= 0;
    vcount <= vcount +1;
    end
    else
    hcount <= hcount +1;
    if(vcount == 931)
    vcount <= 0;
    end



endmodule










`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13.11.2019 15:47:44
// Design Name:
// Module Name: vga_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//

module vga_tb();
    reg clk = 0;
    wire hsync, vsync;
    wire [3:0] pix_r;
    wire [3:0] pix_g;
    wire [3:0] pix_b;
    reg [10:0] hcount;
    reg [9:0] vcount;

    vga_out uut (.pix_r(pix_r), .pix_g(pix_g), .pix_b(pix_b), .hsync(hsync), .vsync(vsync)/*, .hcount(hcount), .vcount(vcount)*/);


    always #5 clk = ~clk;
   initial begin
/*
   $display("hcount: %d", hcount);
   $display("vcount: %d", vcount);

   #5 assign pix_r = 4'hF;
   #5 assign pix_g = 4'hF;
   #5 assign pix_b = 4'hF;
*/
    //$finish;
end



        endmodule