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  1. ----------------------------------------------------------------------------------
  2. -- Company:
  3. -- Engineer:
  4. --
  5. -- Create Date:    12:41:14 02/26/2020
  6. -- Design Name:
  7. -- Module Name:    alokadesme - Behavioral
  8. -- Project Name:
  9. -- Target Devices:
  10. -- Tool versions:
  11. -- Description:
  12. --
  13. -- Dependencies:
  14. --
  15. -- Revision:
  16. -- Revision 0.01 - File Created
  17. -- Additional Comments:
  18. --
  19. ----------------------------------------------------------------------------------
  20. library ieee;
  21. use ieee.std_logic_1164.all;
  22. use ieee.numeric_std.all;
  23.  
  24. entity fib is
  25.    port(
  26.       clk, reset : in std_logic;
  27.       start : in std_logic;
  28.       i: in std_logic_vector(4 downto 0);
  29.       ready, done_tick: out std_logic;
  30.       f: out std_logic_vector (19 downto 0));
  31. end fib;
  32.  
  33. architecture arch of fib is
  34.    type state_type is (idle, op, done);
  35.    signal state_reg, state_next: state_type;
  36.    signal t0_reg, t0_next: unsigned(19 downto 0);
  37.    signal t1_reg, t1_next: unsigned(19 downto 0);
  38.    signal n_reg, n_next: unsigned(4 downto 0);
  39. begin
  40. --  fsmd state and data registers
  41.    process(clk,reset)
  42.    begin
  43.       if reset = '1' then
  44.          state_reg <= idle;
  45.          t0_reg<=  (others=> '0');
  46.          t1_reg<=  (others=> '0');
  47.          n_reg <=  (others=> '0');
  48.       elsif (clk'event and clk = '1') then
  49.          state_reg <= state_next;
  50.          t0_reg <= t0_next;
  51.          t1_reg <= t1_next;
  52.          n_reg <= n_next;
  53.       end if;
  54.    end process;
  55. --  fsmd next - state logic
  56.    process(state_reg, n_reg, t0_reg, t1_reg, start, i, n_next)
  57.    begin
  58.       ready <= '0';
  59.       done_tick <= '0';
  60.       state_next <= state_reg;
  61.       t0_next <= t0_reg;
  62.       t1_next <= t1_reg;
  63.       n_next <= n_reg;
  64.       case state_reg is
  65.          when idle =>
  66.             ready <= '1';
  67.             if start= '1' then
  68.                t0_next <= (others => '0');
  69.                t1_next <= (0 => '1', others => '0');
  70.                n_next <= unsigned(i);
  71.                state_next <= op;
  72.             end if;
  73.          when op =>
  74.             if n_reg = 0 then
  75.                t1_next <= (others => '0');
  76.                state_next <= done;
  77.             elsif n_reg = 1 then
  78.                state_next <= done;
  79.             else
  80.                t1_next <= t1_reg + t0_reg;
  81.                t0_next <= t1_reg;
  82.                n_next <= n_reg - 1;
  83.             end if;
  84.          when done =>
  85.             done_tick <= '1';
  86.             state_next <= idle;
  87.       end case;
  88.    end process;
  89. -- output
  90.    f <= std_logic_vector(t1_reg);
  91. end arch;
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