Lab 8 CLA 4 bits

module ac
  (
  input x,y, ci,
  output z, p, g
  );

  assign z = x ^ y ^ ci;
  assign g = x & y;
  assign p = x | y;

endmodule

module bc
  (
  input gi0, pi0, gi1, pi1, ci,
  output go, po, co
  );

  assign go = gi1 | (gi0 & pi1);
  assign po = pi1 & pi0;
  assign co = (ci & pi0) | gi0;

endmodule


module ml_cla
  (
  input [3:0] x, y,
  input ci,
  output [3:0] z,
  output co
  );

  wire g3, g2, g1, g0, p3, p2, p1, p0, c3, c2, c1, c0, g23, p23, g01, p01, g03, p03;
  //wires
  //4 ACs
  //3 BCs

  ac ac_1
  (
    .x(x[0]),
    .y(y[0]),
    .ci(ci),
    .z(z[0]),
    .g(g),
    .p(p)

  );

  ac ac_2
  (
    .x(x[1]),
    .y(y[1]),
    .ci(ci),
    .z(z[1]),
    .g(g),
    .p(p)

  );

  ac ac_3
  (
    .x(x[2]),
    .y(y[2]),
    .ci(ci),
    .z(z[2]),
    .g(g),
    .p(p)

  );

  ac ac_4
  (
    .x(x[3]),
    .y(y[3]),
    .ci(ci),
    .z(z[3]),
    .g(g),
    .p(p)

  );


  bc bc_1
  (
    .gi0(g0),
    .pi0(p0),
    .gi1(g1),
    .pi1(p1),
    .ci(ci),
    .go(g01),
    .po(p01),
    .co(c1)
  );

  bc bc_2
  (
    .gi0(g2),
    .pi0(p2),
    .gi1(g3),
    .pi1(p3),
    .ci(c2),
    .go(g23),
    .po(p23),
    .co(c3)
  );

  bc bc_3
  (
    .gi0(g01),
    .pi0(p01),
    .gi1(g23),
    .pi1(p23),
    .ci(ci),
    .go(g03),
    .po(p03),
    .co(c2)
  );

  assign co = g03 | ( p03 & ci);

endmodule


module ml_cla_tb
  (
  output reg [3:0] x, y,
  output reg ci,
  output co ,
  output [3:0] z
  );

  integer i;

  initial begin

  {x, y, ci} = 7'd0;

    for(i = 1; i < 256; i = i+1)
     #100 {x, y, ci} = i[7:0];

  end
endmodule