datapath.sv

module datapath (
                     //week 1 stuff
                     input Clk, Reset,
                     input LD_MAR, LD_MDR, MIO_EN, LD_IR, LD_PC,
                     input GatePC, GateMDR, GateALU, GateMARMUX,
                     input [15:0] Data_To_CPU,
                     input [1:0] ADDR2MUX, ALUK, PCMUX,
                     //week 2 stuff
                     input LD_BEN, LD_CC, LD_REG, LD_LED, //not sure about LD_LED
                     input DRMUX, SR1MUX, SR2MUX, ADDR1MUX,
                     //week 1 stuff
                     output logic [15:0] MAR,
                     output logic [15:0] MDR,
                     output logic [15:0] IR,
                     output logic [15:0] PC,
                     //week 2 stuff
                     output logic [11:0] LED,
                     output logic BEN
                     );

    logic [15:0] mem_bus;
    logic [15:0] MDR_input; //thing that goes into MDR
    logic [15:0] PC_input; //thing that goes into PC
    logic [15:0] PC_plus_one;
    logic [15:0] ADDR2_output, ADDR1_output, ADDER_output;
    logic [15:0] ALU_output;
    logic [15:0] PC_output;
    logic [15:0] MDR_output;
    logic [15:0] SR2_output, SR1_output, SR2MUX_output;
    logic [15:0] SEXT5, SEXT6, SEXT9, SEXT11;
    logic [2:0] DRMUX_output, SR1MUX_output;
    logic N_input, Z_input, P_input, N_output, Z_output, P_output;

    //LED logic for IR
    always_ff @ (posedge Clk)
    begin

        if (~LD_LED)
            LED <= 12'h0;
        else
            LED <= IR[11:0];
    end


    //NZP Logic Stuff - tentatively done
    always_comb begin
        if (mem_bus[15] == 1'b1) begin
            N_input = 1'b1;
            Z_input = 1'b0;
            P_input = 1'b0;
        end
        else if (mem_bus[15] == 1'b0) begin
            if (mem_bus == 16'h0) begin
                N_input = 1'b0;
                Z_input = 1'b1;
                P_input = 1'b0;
            end
            else begin
                N_input = 1'b0;
                Z_input = 1'b0;
                P_input = 1'b1;
            end
        end
        else begin //default
            N_input = 1'b0;
            Z_input = 1'b1;
            P_input = 1'b0;
        end
    end


    //MUXES - tentatively done
    one_hot tristate_mux(.Din1(PC_output), .Din2(MDR_output), .Din3(ALU_output), .Din4(ADDER_output),
                                .sel1(GatePC), .sel2(GateMDR), .sel3(GateALU), .sel4(GateMARMUX), .Dout(mem_bus));
    two_one_mux mdr_mux(.Din0(mem_bus), .Din1(Data_To_CPU), .sel(MIO_EN), .Dout(MDR_input));
    mux4 pc_mux(.Din0(PC_plus_one), .Din1(mem_bus), .Din2(ADDER_output), .Din3(16'bx), .sel(PCMUX), .Dout(PC_input));
    two_one_mux addr1_mux(.Din0(PC_output), .Din1(SR1_output), .sel(ADDR1MUX), .Dout(ADDR1_output));
    mux4 addr2_mux(.Din0(16'b0), .Din1(SEXT6), .Din2(SEXT9), .Din3(SEXT11), .sel(ADDR2MUX), .Dout(ADDR2_output));
    two_one_mux #(3) dr_mux(.Din0(IR[11:9]), .Din1(3'b111), .sel(DRMUX), .Dout(DRMUX_output));
    two_one_mux #(3) sr1_mux(.Din0(IR[11:9]), .Din1(IR[8:6]), .sel(SR1MUX), .Dout(SR1MUX_output));
    two_one_mux sr2_mux(.Din0(SR2_output), .Din1(SEXT5), .sel(SR2MUX), .Dout(SR2MUX_output));


    //Registers & Flip Flops
        //registers - tentatively done
    reg_16 PC_reg(.Clk, .Reset, .Load(LD_PC), .D(PC_input), .Data_Out(PC_output));
    reg_16 IR_reg(.Clk, .Reset, .Load(LD_IR), .D(mem_bus), .Data_Out(IR));
    reg_16 MAR_reg(.Clk, .Reset, .Load(LD_MAR), .D(mem_bus), .Data_Out(MAR));
    reg_16 MDR_reg(.Clk, .Reset, .Load(LD_MDR), .D(MDR_input), .Data_Out(MDR_output));

        //flip flops - tentatively done
    flipflop N_reg(.Clk, .Load(LD_CC), .Reset, .D(N_input), .Q(N_output));
    flipflop_z Z_reg(.Clk, .Load(LD_CC), .Reset, .D(Z_input), .Q(Z_output));
    flipflop P_reg(.Clk, .Load(LD_CC), .Reset, .D(P_input), .Q(P_output));
    flipflop ben_reg(.Clk, .Load(LD_BEN), .Reset,
                        .D((IR[11] & N_output) | (IR[10] & Z_output) | (IR[9] & P_output)),
                        .Q(BEN));


    //RegFile Unit - tentatively done
    RegFile file(.Clk, .Reset, .Load(LD_REG), .mem_shit(mem_bus), .DRMUX_output, .SR2_select(IR[2:0]), .SR1MUX_output, .SR2_output, .SR1_output);


    //ALUs - tentatively done
    ALU adder(.A(ADDR1_output), .B(ADDR2_output), .ALUK(2'b00), .Dout(ADDER_output));
    ALU main_ALU(.A(SR1_output), .B(SR2MUX_output), .ALUK, .Dout(ALU_output));


    //Assignments
    assign PC_plus_one = PC_output + 16'h0001;
    assign PC = PC_output;
    assign MDR = MDR_output;
    assign SEXT5 = 16'(signed'(IR[4:0]));
    assign SEXT6 = 16'(signed'(IR[5:0]));
    assign SEXT9 = 16'(signed'(IR[8:0]));
    assign SEXT11 = 16'(signed'(IR[10:0]));


endmodule