library ieee;
library altera_mf;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use altera_mf.altera_mf_components.all;
entity Pipeline is
    port(
        clock           : in std_logic;
        reset          : in std_logic;
		  IO_DATA		   : out std_logic_vector(31 downto 0);
		  IO_WRITE			: out std_logic;
		  dbg_fbufopcode : out std_logic_vector(31 downto 0);
		  dbg_dbufopcode : out std_logic_vector(6 downto 0);
		  dbg_ebufopcode : out std_logic_vector(6 downto 0);
		  dbg_mbufopcode : out std_logic_vector(6 downto 0)
    );
end Pipeline;

architecture a of Pipeline is

	begin
	    IO_DATA <= exresult;

		dbg_fbufopcode <= fbufinstruction;
		dbg_dbufopcode <= dbufopcode;
		dbg_ebufopcode <= ebufopcode;
		dbg_mbufopcode <= mbufopcode;

        fetch : entity work.InstructionFetch
        PORT MAP (
            clock,
            reset,
            exresult,
            branchmux,
            fetchPC,
            fetchinstruction
        );

        fetchbuffer : entity work.FBUF
        PORT MAP (
            clock,
            reset,
            fetchPC,
            fetchinstruction,
            fbufPC,
            fbufinstruction
        );

        decode : entity work.InstructionDecode
        PORT MAP (
            fbufinstruction,
            decodeopcode,
            decoderd,
            decoders1,
            decoders2,
            decodeimm,
            decodefunct3,
            decodefunct7
        );

        dbuf : entity work.DBUF
        PORT MAP (
            clock,
            reset,
            fbufPC,
            decodeopcode,
            decoderd,
            decodereadrs1,
            decodereadrs2,
            decodeimm,
            decodefunct3,
            decodefunct7,
            dbufPC,
            dbufopcode,
            dbufrd,
            dbufreadrs1,
            dbufreadrs2,
            dbufimm,
            dbuffunct3,
            dbuffunct7
        );

        ex : entity work.Execute
        PORT MAP (
            dbufPC,
            dbufopcode,
            dbufrd,
            dbufreadrs1,
            dbufreadrs2,
            dbufimm,
            dbuffunct3,
            dbuffunct7,
            branchmux,
            exresult,
            IO_WRITE
        );

        ebuf : entity work.EBUF
        PORT MAP (
            clock,
            reset,
            dbufopcode,
            dbufrd,
            dbufreadrs1,
            dbufreadrs2,
            dbufimm,
            dbuffunct3,
            dbuffunct7,
            exresult,
            ebufopcode,
            ebufrd,
            ebufreadrs1,
            ebufreadrs2,
            ebufimm,
            ebufresult,
            ebuffunct3,
            ebuffunct7
        );

        mem : entity work.Memory
        PORT MAP (
            clock,
            reset,
            ebufopcode,
            ebuffunct3,
            ebufreadrs2,
            ebufresult,
            memresult
        );

        mbuf : entity work.MBUF
        PORT MAP (
            clock,
            reset,
            ebufopcode,
            ebufrd,
            memresult,
            mbufopcode,
            mbufrd,
            mbufresult
        );

        wb : entity work.Writeback
        PORT MAP (
            mbufopcode,
            mbufrd,
            mbufresult,
            wren,
            wrdata,
            wraddress
        );

        regfile : entity work.DPRF
        PORT MAP (
            clock,
            reset,
            wren,
            decoders1,
            decoders2,
            wraddress,
            wrdata,
            decodereadrs1,
            decodereadrs2
        );

end a;
-------------------------------------------------------------------------------------
library ieee;
library altera_mf;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use altera_mf.altera_mf_components.all;
entity InstructionFetch is
    port(
        clock           : in std_logic;
        reset          : in std_logic;
        branch          : in std_logic_vector(31 downto 0);
		branch_mux		: in std_logic;
        PC              : out std_logic_vector(31 downto 0);
        instruction     : out std_logic_vector(31 downto 0)
    );
end InstructionFetch;

architecture a of InstructionFetch is

    signal program_counter  : std_logic_vector(31 downto 0);
    signal data             : std_logic_vector(31 downto 0);
    signal wren             : std_logic;
	begin

        altsyncram_component : altsyncram
        GENERIC MAP (
            clock_enable_input_a => "BYPASS",
            clock_enable_output_a => "BYPASS",
            init_file => "program.mif",
            intended_device_family => "MAX 10",
            lpm_hint => "ENABLE_RUNTIME_MOD=NO",
            lpm_type => "altsyncram",
            numwords_a => 1024,
            operation_mode => "SINGLE_PORT",
            outdata_aclr_a => "CLEAR0",
            outdata_reg_a => "UNREGISTERED",
            power_up_uninitialized => "FALSE",
            read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
            widthad_a => 10,
            width_a => 32,
            width_byteena_a => 1
        )
        PORT MAP (
            aclr0 => reset,
            address_a => program_counter(9 downto 0),
            clock0 => clock,
            data_a => data,
            wren_a => wren,
            q_a => instruction
        );
end a;
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FBUF is
    port(
        clock           : in std_logic;
        reset          : in std_logic;
        instructionin     : in std_logic_vector(31 downto 0);
        instructionout     : out std_logic_vector(31 downto 0)
    );
end FBUF;

architecture a of FBUF is

    signal instruction : std_logic_vector(31 downto 0);
	begin


        instructionout <= instruction;

        process (clock, reset)
        begin
            if (rising_edge(clock)) then
					 if (reset = '1') then
						instruction <= (others => '0');
                else
						instruction <= std_logic_vector(instructionin);
					 end if;
            end if;
        end process;
end a;
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity InstructionDecode is
    port(
        instruction     : in std_logic_vector(31 downto 0);
        opcode          : out std_logic_vector(6 downto 0);
    );
end InstructionDecode;

architecture a of InstructionDecode is

	begin

        opcode <= instruction(6 downto 0);

end a;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity DBUF is
    port(
        clock             : in std_logic;
        reset            : in std_logic;
        opcodein          : in std_logic_vector(6 downto 0);
        opcodeout          : out std_logic_vector(6 downto 0);
    );
end DBUF;

architecture a of DBUF is

    signal opcode : std_logic_vector(6 downto 0);

	begin

        opcodeout <= opcode;

        process (clock, reset)
        begin


            if (rising_edge(clock)) then
				    if (reset = '1') then
						 opcode <= (others => '0');
					 else
						 opcode <= opcodein;
					 end if;
            end if;
        end process;

end a;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity Execute is
    port(
		  PC					: in std_logic_vector(31 downto 0);
		  opcode          : in std_logic_vector(6 downto 0);
        rd              : in std_logic_vector(4 downto 0);
        readrs1,
        readrs2			: in std_logic_vector(31 downto 0);

        imm             : in std_logic_vector(31 downto 0);
        funct3          : in std_logic_vector(2 downto 0);
        funct7          : in std_logic_vector(6 downto 0);
		  branchmux       : out std_logic;
        result          : out std_logic_vector(31 downto 0);
		  IO_WRITE			: out std_logic
    );
end Execute;

architecture a of Execute is
    signal exresulti : std_logic_vector(31 downto 0);
    signal exresultr : std_logic_vector(31 downto 0);
	 signal subimm       : std_logic_vector(31 downto 0);
	 signal comparisonimm : std_logic;
	 signal subreg       : std_logic_vector(31 downto 0);
	 signal comparisonreg : std_logic;
	begin
		  branchmux <= '1' when opcode = "1101111" or opcode = "1100111" or opcode = "1100011" else '0';
		  IO_WRITE <= '1' when opcode = "0000001" else '0';
        with opcode select
            result <= imm when "0110111",
                      imm + PC when "0010111",
                      imm + PC when "1101111",
                      readrs1 + imm when "1100111",
                      readrs2 - readrs1 when "1100011",
                      readrs1 + imm when "0000011",
                      readrs1 + imm when "0100011",

                      exresulti when "0010011",
                      exresultr when "0110011",
							 readrs1 when "0000001",
                      (others => '0') when others;

end a;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity EBUF is
    port(
        clock             : in std_logic;
        reset            : in std_logic;
        opcodein          : in std_logic_vector(6 downto 0);
        rdin              : in std_logic_vector(4 downto 0);
        readrs1in         : in std_logic_vector(31 downto 0);
        readrs2in         : in std_logic_vector(31 downto 0);
        immin             : in std_logic_vector(31 downto 0);

        funct3in          : in std_logic_vector(2 downto 0);
        funct7in          : in std_logic_vector(6 downto 0);
		  exresultin        : in std_logic_vector(31 downto 0);
        opcodeout          : out std_logic_vector(6 downto 0);
        rdout              : out std_logic_vector(4 downto 0);
        readrs1out         : out std_logic_vector(31 downto 0);
        readrs2out         : out std_logic_vector(31 downto 0);
        immout             : out std_logic_vector(31 downto 0);
        exresultout        : out std_logic_vector(31 downto 0);
        funct3out          : out std_logic_vector(2 downto 0);
        funct7out          : out std_logic_vector(6 downto 0)
    );
end EBUF;

architecture a of EBUF is

    signal PC : std_logic_vector(31 downto 0);
    signal opcode : std_logic_vector(6 downto 0) := "0000000";
    signal rd : std_logic_vector(4 downto 0);
    signal readrs1 : std_logic_vector(31 downto 0);
    signal readrs2 : std_logic_vector(31 downto 0);
    signal imm : std_logic_vector(31 downto 0);
    signal exresult : std_logic_vector(31 downto 0);
    signal funct3 : std_logic_vector(2 downto 0);
    signal funct7 : std_logic_vector(6 downto 0);

	begin

 		opcodeout <= opcode;

        process (clock, reset)
        begin


            if (rising_edge(clock)) then
				    if (reset = '1') then
						 opcode <= (others => '0');
					 else
						 opcode <= opcodein;
					 end if;
            end if;
        end process;

end a;
library ieee;
library altera_mf;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use altera_mf.altera_mf_components.all;
entity Memory is
    port(
        clock           : in std_logic;
        reset          : in std_logic;
        opcode          : in std_logic_vector(6 downto 0);
        funct3          : in std_logic_vector(2 downto 0);
        readrs2         : in std_logic_vector(31 downto 0);
        ex_result       : in std_logic_vector(31 downto 0);
        mem_result      : out std_logic_vector(31 downto 0)
    );
end Memory;

architecture a of Memory is

    signal read_data        : std_logic_vector(31 downto 0);
    signal mem_out          : std_logic_vector(31 downto 0);
    signal byteena          : std_logic_vector(3 downto 0);
    signal wren             : std_logic;
	begin


	altsyncram_component : altsyncram
	GENERIC MAP (
		byte_size => 8,
		clock_enable_input_a => "BYPASS",
		clock_enable_output_a => "BYPASS",
		init_file => "memory.mif",
		intended_device_family => "MAX 10",
		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
		lpm_type => "altsyncram",
		numwords_a => 1024,
		operation_mode => "SINGLE_PORT",
		outdata_aclr_a => "CLEAR0",
		outdata_reg_a => "UNREGISTERED",
		power_up_uninitialized => "FALSE",
		read_during_write_mode_port_a => "OLD_DATA",
		widthad_a => 10,
		width_a => 32,
		width_byteena_a => 4
	)
	PORT MAP (
		aclr0 => reset,
		address_a => ex_result(9 downto 0),
		byteena_a => byteena,
		clock0 => clock,
		data_a => readrs2,
		wren_a => wren,
		q_a => read_data
	);
        wren <= '1' when opcode = "0100011" else '0';

        mem_result <= mem_out when opcode = "0000011" else
                      ex_result;
end a;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity MBUF is
    port(
        clock             : in std_logic;
        reset            : in std_logic;
        opcodein          : in std_logic_vector(6 downto 0);
        rdin              : in std_logic_vector(4 downto 0);
        memresultin        : in std_logic_vector(31 downto 0);
        opcodeout          : out std_logic_vector(6 downto 0);
        rdout              : out std_logic_vector(4 downto 0);
        memresultout        : out std_logic_vector(31 downto 0)
    );
end MBUF;

architecture a of MBUF is

    signal opcode : std_logic_vector(6 downto 0);
    signal rd : std_logic_vector(4 downto 0);
    signal memresult : std_logic_vector(31 downto 0);

	begin

        opcodeout <= opcode;

        process (clock, reset)
        begin
            if (rising_edge(clock)) then
				    if (reset = '1') then
						 opcode <= (others => '0');
					 else
						 opcode <= opcodein;
					 end if;
            end if;
        end process;

end a;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Writeback is
    port(
        opcode          : in std_logic_vector(6 downto 0);
        wren            : out std_logic;
        wrdata          : out std_logic_vector(31 downto 0);
        wraddress       : out std_logic_vector(4 downto 0)
    );
end Writeback;

architecture a of Writeback is

	begin

        wrdata <= mem_result;
        wraddress <= rd;
        wren <= '1' when opcode = "0110111" or
                         opcode = "0010111" or
                         opcode = "1101111" or
                         opcode = "1100111" or
                         opcode = "0000011" or
                         opcode = "0010011" or
                         opcode = "0110011" else
                '0';


end a;