library ieee;
use ieee.std_logic_1164.all;

entity fsm1 is

	port
	(
		-- Input ports
		clk 	: in std_logic;
		reset	: in  std_logic ;


		-- Output ports
		s_out	: out std_logic

	);
end fsm1;

-- najlakse da jedno stanje ima 1 jedinicu , 1 flip flop je on 0001 , 0010,0100,1000 lakse za kodovanje

architecture fsm1_bh of fsm1 is
type state_type is (s0,s1,s2,s3,s4,s5,s6,s7);
signal state_reg,next_state:state_type; --state_reg je trenutno


begin

--sekvencijalni proces promene trenutnog stanja
state_transition: process (clk,reset) is
begin

if(reset='1')then  --asinhroni reset

state_reg<=s0;

elsif (clk'event and clk='1') then  -- ili rising_edge(clk)
   state_reg<=next_state;
	end if;

end process state_transition;


	--kombinacioni ulazni proces, ulazi su samo clk i reset pa ovde nema dodatnog komb ulaza vec samo trenutno stanje
	next_state_logic: process(state_reg) is
	begin
	case (state_reg)is
	when s0=>
		next_state<=s1;
	when s1=>
		next_state<=s2;
	when s2=>
		next_state<=s3;
	when s3=>
		next_state<=s4;
	when s4=>
		next_state<=s5;
	when s5=>
		next_state<=s6;
	when s6=>
		next_state<=s7;
	when s7=>
		next_state<=s0;
	end case;


	end process next_state_logic;

	-- izlazni komb proces

	output_logic: process(state_reg) is
	begin
	s_out<='0';
	case (state_reg)is
	when s1=>
		s_out<='1';
	when s3=>
		s_out<='1';
	when s4=>
		s_out<='1';
	when s5=>
		s_out<='1';
	when others=>

	end case;


	end process output_logic;


end fsm1_bh;


test fajl:

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY fsm1_vhd_tst IS
END fsm1_vhd_tst;
ARCHITECTURE fsm1_arch OF fsm1_vhd_tst IS
-- constants
constant clk_period :  time := 20 ns;
-- signals
SIGNAL clk : STD_LOGIC:='0';
SIGNAL reset : STD_LOGIC:='1';
SIGNAL s_out : STD_LOGIC;
COMPONENT fsm1
	PORT (
	clk : IN STD_LOGIC;
	reset : IN STD_LOGIC;
	s_out : OUT STD_LOGIC
	);
END COMPONENT;

BEGIN
	i1 : fsm1
	PORT MAP (
-- list connections between master ports and signals
	clk => clk,
	reset => reset,
	s_out => s_out
	);


clk_gen : PROCESS

BEGIN
     wait for clk_period/2;
clk<='1';
wait for clk_period/2;
clk<='0';



-- wait znaci da se proces zavrsava i da nece opet da se izvrsi ali ovde treba da bude kontinualan pa nema wait
END PROCESS clk_gen;




always : PROCESS

BEGIN
    wait for clk_period*3;
reset<='0';
wait for clk_period*20;
reset<='1';
WAIT;
END PROCESS always;




END fsm1_arch;