Stereo FM

module topmodule(
    clock,
    reset,
    start,
    ready,
    clken48kHz,
    clken192kHz,
    Ks,
    Kd,
    Kp,
    Kf,
    stepWc,
    step,
    left,
    right,
    digital_out
);

input clock;
input reset;
input start;
input ready;
input clken48kHz;
input clken192kHz;

wire signed [17:0] interpolated_LpR;
wire signed [17:0] interpolated_LmR;

input [3:0] Ks;
input [3:0] Kd;
input [3:0] Kp;
input Kf;
input [29:0] stepWc;
input [29:0] step;
input signed [17:0] left;
input signed [17:0] right;

output [7:0] digital_out;

module_48kHz_1
(
    .clock(clock),
    .reset(reset),
    .start(start),
    .ready(ready),
    .Ks(Ks),
    .Kd(Kd),
    .clken48kHz(clken48kHz),
    .clken192kHz(clken192kHz),
    .left(left),
    .right(right),
    .interpolated_LpR(interpolated_LpR),
    .interpolated_LmR(interpolated_LmR)
 );

 module_192kHz_1
(
    .clock(clock),
    .reset(reset),
    .start(start),
    .ready(ready),
    .clken192kHz(clken192kHz),
    .interpolated_LpR(interpolated_LpR),
    .interpolated_LmR(interpolated_LmR),
    .Kp(Kp),
    .Kf(Kf),
    .stepWc(stepWc),
    .step(step)
 );

  dds  dds_final(
            .clock( clock ),
            .reset( reset ),
            .enableclk( clock ),
            .phaseinc( step ),
            .outsine( digital_out )
    );


endmodule